1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 TEST(MachineInstructionHorizontalReduction, IsCorrect) {
14   using namespace ARM;
15 
16   auto HorizontalReduction = [](unsigned Opcode) {
17     switch (Opcode) {
18     default:
19       break;
20     case MVE_VABAVs16:
21     case MVE_VABAVs32:
22     case MVE_VABAVs8:
23     case MVE_VABAVu16:
24     case MVE_VABAVu32:
25     case MVE_VABAVu8:
26     case MVE_VADDLVs32acc:
27     case MVE_VADDLVs32no_acc:
28     case MVE_VADDLVu32acc:
29     case MVE_VADDLVu32no_acc:
30     case MVE_VADDVs16acc:
31     case MVE_VADDVs16no_acc:
32     case MVE_VADDVs32acc:
33     case MVE_VADDVs32no_acc:
34     case MVE_VADDVs8acc:
35     case MVE_VADDVs8no_acc:
36     case MVE_VADDVu16acc:
37     case MVE_VADDVu16no_acc:
38     case MVE_VADDVu32acc:
39     case MVE_VADDVu32no_acc:
40     case MVE_VADDVu8acc:
41     case MVE_VADDVu8no_acc:
42     case MVE_VMAXAVs16:
43     case MVE_VMAXAVs32:
44     case MVE_VMAXAVs8:
45     case MVE_VMAXNMAVf16:
46     case MVE_VMAXNMAVf32:
47     case MVE_VMAXNMVf16:
48     case MVE_VMAXNMVf32:
49     case MVE_VMAXVs16:
50     case MVE_VMAXVs32:
51     case MVE_VMAXVs8:
52     case MVE_VMAXVu16:
53     case MVE_VMAXVu32:
54     case MVE_VMAXVu8:
55     case MVE_VMINAVs16:
56     case MVE_VMINAVs32:
57     case MVE_VMINAVs8:
58     case MVE_VMINNMAVf16:
59     case MVE_VMINNMAVf32:
60     case MVE_VMINNMVf16:
61     case MVE_VMINNMVf32:
62     case MVE_VMINVs16:
63     case MVE_VMINVs32:
64     case MVE_VMINVs8:
65     case MVE_VMINVu16:
66     case MVE_VMINVu32:
67     case MVE_VMINVu8:
68     case MVE_VMLADAVas16:
69     case MVE_VMLADAVas32:
70     case MVE_VMLADAVas8:
71     case MVE_VMLADAVau16:
72     case MVE_VMLADAVau32:
73     case MVE_VMLADAVau8:
74     case MVE_VMLADAVaxs16:
75     case MVE_VMLADAVaxs32:
76     case MVE_VMLADAVaxs8:
77     case MVE_VMLADAVs16:
78     case MVE_VMLADAVs32:
79     case MVE_VMLADAVs8:
80     case MVE_VMLADAVu16:
81     case MVE_VMLADAVu32:
82     case MVE_VMLADAVu8:
83     case MVE_VMLADAVxs16:
84     case MVE_VMLADAVxs32:
85     case MVE_VMLADAVxs8:
86     case MVE_VMLALDAVas16:
87     case MVE_VMLALDAVas32:
88     case MVE_VMLALDAVau16:
89     case MVE_VMLALDAVau32:
90     case MVE_VMLALDAVaxs16:
91     case MVE_VMLALDAVaxs32:
92     case MVE_VMLALDAVs16:
93     case MVE_VMLALDAVs32:
94     case MVE_VMLALDAVu16:
95     case MVE_VMLALDAVu32:
96     case MVE_VMLALDAVxs16:
97     case MVE_VMLALDAVxs32:
98     case MVE_VMLSDAVas16:
99     case MVE_VMLSDAVas32:
100     case MVE_VMLSDAVas8:
101     case MVE_VMLSDAVaxs16:
102     case MVE_VMLSDAVaxs32:
103     case MVE_VMLSDAVaxs8:
104     case MVE_VMLSDAVs16:
105     case MVE_VMLSDAVs32:
106     case MVE_VMLSDAVs8:
107     case MVE_VMLSDAVxs16:
108     case MVE_VMLSDAVxs32:
109     case MVE_VMLSDAVxs8:
110     case MVE_VMLSLDAVas16:
111     case MVE_VMLSLDAVas32:
112     case MVE_VMLSLDAVaxs16:
113     case MVE_VMLSLDAVaxs32:
114     case MVE_VMLSLDAVs16:
115     case MVE_VMLSLDAVs32:
116     case MVE_VMLSLDAVxs16:
117     case MVE_VMLSLDAVxs32:
118     case MVE_VRMLALDAVHas32:
119     case MVE_VRMLALDAVHau32:
120     case MVE_VRMLALDAVHaxs32:
121     case MVE_VRMLALDAVHs32:
122     case MVE_VRMLALDAVHu32:
123     case MVE_VRMLALDAVHxs32:
124     case MVE_VRMLSLDAVHas32:
125     case MVE_VRMLSLDAVHaxs32:
126     case MVE_VRMLSLDAVHs32:
127     case MVE_VRMLSLDAVHxs32:
128       return true;
129     }
130     return false;
131   };
132 
133   LLVMInitializeARMTargetInfo();
134   LLVMInitializeARMTarget();
135   LLVMInitializeARMTargetMC();
136 
137   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
138   std::string Error;
139   const Target *T = TargetRegistry::lookupTarget(TT, Error);
140   if (!T) {
141     dbgs() << Error;
142     return;
143   }
144 
145   TargetOptions Options;
146   auto TM = std::unique_ptr<LLVMTargetMachine>(
147     static_cast<LLVMTargetMachine*>(
148       T->createTargetMachine(TT, "generic", "", Options, None, None,
149                              CodeGenOpt::Default)));
150   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
151                   std::string(TM->getTargetFeatureString()),
152                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
153   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
154   auto MII = TM->getMCInstrInfo();
155 
156   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
157     const MCInstrDesc &Desc = TII->get(i);
158 
159     uint64_t Flags = Desc.TSFlags;
160     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
161       continue;
162 
163     bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
164     ASSERT_EQ(HorizontalReduction(i), Valid)
165               << MII->getName(i)
166               << ": mismatched expectation for tail-predicated safety\n";
167   }
168 }
169 
170 TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
171   using namespace ARM;
172 
173   auto RetainsPreviousHalfElement = [](unsigned Opcode) {
174     switch (Opcode) {
175     default:
176       break;
177     case MVE_VMOVNi16bh:
178     case MVE_VMOVNi16th:
179     case MVE_VMOVNi32bh:
180     case MVE_VMOVNi32th:
181     case MVE_VQMOVNs16bh:
182     case MVE_VQMOVNs16th:
183     case MVE_VQMOVNs32bh:
184     case MVE_VQMOVNs32th:
185     case MVE_VQMOVNu16bh:
186     case MVE_VQMOVNu16th:
187     case MVE_VQMOVNu32bh:
188     case MVE_VQMOVNu32th:
189     case MVE_VQMOVUNs16bh:
190     case MVE_VQMOVUNs16th:
191     case MVE_VQMOVUNs32bh:
192     case MVE_VQMOVUNs32th:
193     case MVE_VQRSHRNbhs16:
194     case MVE_VQRSHRNbhs32:
195     case MVE_VQRSHRNbhu16:
196     case MVE_VQRSHRNbhu32:
197     case MVE_VQRSHRNths16:
198     case MVE_VQRSHRNths32:
199     case MVE_VQRSHRNthu16:
200     case MVE_VQRSHRNthu32:
201     case MVE_VQRSHRUNs16bh:
202     case MVE_VQRSHRUNs16th:
203     case MVE_VQRSHRUNs32bh:
204     case MVE_VQRSHRUNs32th:
205     case MVE_VQSHRNbhs16:
206     case MVE_VQSHRNbhs32:
207     case MVE_VQSHRNbhu16:
208     case MVE_VQSHRNbhu32:
209     case MVE_VQSHRNths16:
210     case MVE_VQSHRNths32:
211     case MVE_VQSHRNthu16:
212     case MVE_VQSHRNthu32:
213     case MVE_VQSHRUNs16bh:
214     case MVE_VQSHRUNs16th:
215     case MVE_VQSHRUNs32bh:
216     case MVE_VQSHRUNs32th:
217     case MVE_VRSHRNi16bh:
218     case MVE_VRSHRNi16th:
219     case MVE_VRSHRNi32bh:
220     case MVE_VRSHRNi32th:
221     case MVE_VSHRNi16bh:
222     case MVE_VSHRNi16th:
223     case MVE_VSHRNi32bh:
224     case MVE_VSHRNi32th:
225     case MVE_VCVTf16f32bh:
226     case MVE_VCVTf16f32th:
227     case MVE_VCVTf32f16bh:
228     case MVE_VCVTf32f16th:
229       return true;
230     }
231     return false;
232   };
233 
234   LLVMInitializeARMTargetInfo();
235   LLVMInitializeARMTarget();
236   LLVMInitializeARMTargetMC();
237 
238   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
239   std::string Error;
240   const Target *T = TargetRegistry::lookupTarget(TT, Error);
241   if (!T) {
242     dbgs() << Error;
243     return;
244   }
245 
246   TargetOptions Options;
247   auto TM = std::unique_ptr<LLVMTargetMachine>(
248     static_cast<LLVMTargetMachine*>(
249       T->createTargetMachine(TT, "generic", "", Options, None, None,
250                              CodeGenOpt::Default)));
251   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
252                   std::string(TM->getTargetFeatureString()),
253                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
254   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
255   auto MII = TM->getMCInstrInfo();
256 
257   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
258     const MCInstrDesc &Desc = TII->get(i);
259 
260     uint64_t Flags = Desc.TSFlags;
261     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
262       continue;
263 
264     bool Valid = (Flags & ARMII::RetainsPreviousHalfElement) != 0;
265     ASSERT_EQ(RetainsPreviousHalfElement(i), Valid)
266               << MII->getName(i)
267               << ": mismatched expectation for tail-predicated safety\n";
268   }
269 }
270 // Test for instructions that aren't immediately obviously valid within a
271 // tail-predicated loop. This should be marked up in their tablegen
272 // descriptions. Currently we, conservatively, disallow:
273 // - cross beat carries.
274 // - complex operations.
275 // - horizontal operations.
276 // - byte swapping.
277 // - interleaved memory instructions.
278 // TODO: Add to this list once we can handle them safely.
279 TEST(MachineInstrValidTailPredication, IsCorrect) {
280 
281   using namespace ARM;
282 
283   auto IsValidTPOpcode = [](unsigned Opcode) {
284     switch (Opcode) {
285     default:
286       return false;
287     case MVE_ASRLi:
288     case MVE_ASRLr:
289     case MVE_LSRL:
290     case MVE_SQRSHR:
291     case MVE_SQSHL:
292     case MVE_SRSHR:
293     case MVE_UQRSHL:
294     case MVE_UQSHL:
295     case MVE_URSHR:
296     case MVE_VABDf16:
297     case MVE_VABDf32:
298     case MVE_VABDs16:
299     case MVE_VABDs32:
300     case MVE_VABDs8:
301     case MVE_VABDu16:
302     case MVE_VABDu32:
303     case MVE_VABDu8:
304     case MVE_VABSf16:
305     case MVE_VABSf32:
306     case MVE_VABSs16:
307     case MVE_VABSs32:
308     case MVE_VABSs8:
309     case MVE_VADD_qr_f16:
310     case MVE_VADD_qr_f32:
311     case MVE_VADD_qr_i16:
312     case MVE_VADD_qr_i32:
313     case MVE_VADD_qr_i8:
314     case MVE_VADDf16:
315     case MVE_VADDf32:
316     case MVE_VADDi16:
317     case MVE_VADDi32:
318     case MVE_VADDi8:
319     case MVE_VAND:
320     case MVE_VBIC:
321     case MVE_VBICimmi16:
322     case MVE_VBICimmi32:
323     case MVE_VBRSR16:
324     case MVE_VBRSR32:
325     case MVE_VBRSR8:
326     case MVE_VCLSs16:
327     case MVE_VCLSs32:
328     case MVE_VCLSs8:
329     case MVE_VCLZs16:
330     case MVE_VCLZs32:
331     case MVE_VCLZs8:
332     case MVE_VCMPf16:
333     case MVE_VCMPf16r:
334     case MVE_VCMPf32:
335     case MVE_VCMPf32r:
336     case MVE_VCMPi16:
337     case MVE_VCMPi16r:
338     case MVE_VCMPi32:
339     case MVE_VCMPi32r:
340     case MVE_VCMPi8:
341     case MVE_VCMPi8r:
342     case MVE_VCMPs16:
343     case MVE_VCMPs16r:
344     case MVE_VCMPs32:
345     case MVE_VCMPs32r:
346     case MVE_VCMPs8:
347     case MVE_VCMPs8r:
348     case MVE_VCMPu16:
349     case MVE_VCMPu16r:
350     case MVE_VCMPu32:
351     case MVE_VCMPu32r:
352     case MVE_VCMPu8:
353     case MVE_VCMPu8r:
354     case MVE_VCTP16:
355     case MVE_VCTP32:
356     case MVE_VCTP64:
357     case MVE_VCTP8:
358     case MVE_VCVTf16s16_fix:
359     case MVE_VCVTf16s16n:
360     case MVE_VCVTf16u16_fix:
361     case MVE_VCVTf16u16n:
362     case MVE_VCVTf32s32_fix:
363     case MVE_VCVTf32s32n:
364     case MVE_VCVTf32u32_fix:
365     case MVE_VCVTf32u32n:
366     case MVE_VCVTs16f16_fix:
367     case MVE_VCVTs16f16a:
368     case MVE_VCVTs16f16m:
369     case MVE_VCVTs16f16n:
370     case MVE_VCVTs16f16p:
371     case MVE_VCVTs16f16z:
372     case MVE_VCVTs32f32_fix:
373     case MVE_VCVTs32f32a:
374     case MVE_VCVTs32f32m:
375     case MVE_VCVTs32f32n:
376     case MVE_VCVTs32f32p:
377     case MVE_VCVTs32f32z:
378     case MVE_VCVTu16f16_fix:
379     case MVE_VCVTu16f16a:
380     case MVE_VCVTu16f16m:
381     case MVE_VCVTu16f16n:
382     case MVE_VCVTu16f16p:
383     case MVE_VCVTu16f16z:
384     case MVE_VCVTu32f32_fix:
385     case MVE_VCVTu32f32a:
386     case MVE_VCVTu32f32m:
387     case MVE_VCVTu32f32n:
388     case MVE_VCVTu32f32p:
389     case MVE_VCVTu32f32z:
390     case MVE_VDDUPu16:
391     case MVE_VDDUPu32:
392     case MVE_VDDUPu8:
393     case MVE_VDUP16:
394     case MVE_VDUP32:
395     case MVE_VDUP8:
396     case MVE_VDWDUPu16:
397     case MVE_VDWDUPu32:
398     case MVE_VDWDUPu8:
399     case MVE_VEOR:
400     case MVE_VFMA_qr_Sf16:
401     case MVE_VFMA_qr_Sf32:
402     case MVE_VFMA_qr_f16:
403     case MVE_VFMA_qr_f32:
404     case MVE_VFMAf16:
405     case MVE_VFMAf32:
406     case MVE_VFMSf16:
407     case MVE_VFMSf32:
408     case MVE_VMAXAs16:
409     case MVE_VMAXAs32:
410     case MVE_VMAXAs8:
411     case MVE_VMAXs16:
412     case MVE_VMAXs32:
413     case MVE_VMAXs8:
414     case MVE_VMAXu16:
415     case MVE_VMAXu32:
416     case MVE_VMAXu8:
417     case MVE_VMINAs16:
418     case MVE_VMINAs32:
419     case MVE_VMINAs8:
420     case MVE_VMINs16:
421     case MVE_VMINs32:
422     case MVE_VMINs8:
423     case MVE_VMINu16:
424     case MVE_VMINu32:
425     case MVE_VMINu8:
426     case MVE_VMLAS_qr_s16:
427     case MVE_VMLAS_qr_s32:
428     case MVE_VMLAS_qr_s8:
429     case MVE_VMLAS_qr_u16:
430     case MVE_VMLAS_qr_u32:
431     case MVE_VMLAS_qr_u8:
432     case MVE_VMLA_qr_s16:
433     case MVE_VMLA_qr_s32:
434     case MVE_VMLA_qr_s8:
435     case MVE_VMLA_qr_u16:
436     case MVE_VMLA_qr_u32:
437     case MVE_VMLA_qr_u8:
438     case MVE_VHADD_qr_s16:
439     case MVE_VHADD_qr_s32:
440     case MVE_VHADD_qr_s8:
441     case MVE_VHADD_qr_u16:
442     case MVE_VHADD_qr_u32:
443     case MVE_VHADD_qr_u8:
444     case MVE_VHADDs16:
445     case MVE_VHADDs32:
446     case MVE_VHADDs8:
447     case MVE_VHADDu16:
448     case MVE_VHADDu32:
449     case MVE_VHADDu8:
450     case MVE_VHSUB_qr_s16:
451     case MVE_VHSUB_qr_s32:
452     case MVE_VHSUB_qr_s8:
453     case MVE_VHSUB_qr_u16:
454     case MVE_VHSUB_qr_u32:
455     case MVE_VHSUB_qr_u8:
456     case MVE_VHSUBs16:
457     case MVE_VHSUBs32:
458     case MVE_VHSUBs8:
459     case MVE_VHSUBu16:
460     case MVE_VHSUBu32:
461     case MVE_VHSUBu8:
462     case MVE_VIDUPu16:
463     case MVE_VIDUPu32:
464     case MVE_VIDUPu8:
465     case MVE_VIWDUPu16:
466     case MVE_VIWDUPu32:
467     case MVE_VIWDUPu8:
468     case MVE_VLDRBS16:
469     case MVE_VLDRBS16_post:
470     case MVE_VLDRBS16_pre:
471     case MVE_VLDRBS16_rq:
472     case MVE_VLDRBS32:
473     case MVE_VLDRBS32_post:
474     case MVE_VLDRBS32_pre:
475     case MVE_VLDRBS32_rq:
476     case MVE_VLDRBU16:
477     case MVE_VLDRBU16_post:
478     case MVE_VLDRBU16_pre:
479     case MVE_VLDRBU16_rq:
480     case MVE_VLDRBU32:
481     case MVE_VLDRBU32_post:
482     case MVE_VLDRBU32_pre:
483     case MVE_VLDRBU32_rq:
484     case MVE_VLDRBU8:
485     case MVE_VLDRBU8_post:
486     case MVE_VLDRBU8_pre:
487     case MVE_VLDRBU8_rq:
488     case MVE_VLDRDU64_qi:
489     case MVE_VLDRDU64_qi_pre:
490     case MVE_VLDRDU64_rq:
491     case MVE_VLDRDU64_rq_u:
492     case MVE_VLDRHS32:
493     case MVE_VLDRHS32_post:
494     case MVE_VLDRHS32_pre:
495     case MVE_VLDRHS32_rq:
496     case MVE_VLDRHS32_rq_u:
497     case MVE_VLDRHU16:
498     case MVE_VLDRHU16_post:
499     case MVE_VLDRHU16_pre:
500     case MVE_VLDRHU16_rq:
501     case MVE_VLDRHU16_rq_u:
502     case MVE_VLDRHU32:
503     case MVE_VLDRHU32_post:
504     case MVE_VLDRHU32_pre:
505     case MVE_VLDRHU32_rq:
506     case MVE_VLDRHU32_rq_u:
507     case MVE_VLDRWU32:
508     case MVE_VLDRWU32_post:
509     case MVE_VLDRWU32_pre:
510     case MVE_VLDRWU32_qi:
511     case MVE_VLDRWU32_qi_pre:
512     case MVE_VLDRWU32_rq:
513     case MVE_VLDRWU32_rq_u:
514     case MVE_VMOVimmf32:
515     case MVE_VMOVimmi16:
516     case MVE_VMOVimmi32:
517     case MVE_VMOVimmi64:
518     case MVE_VMOVimmi8:
519     case MVE_VMOVNi16bh:
520     case MVE_VMOVNi16th:
521     case MVE_VMOVNi32bh:
522     case MVE_VMOVNi32th:
523     case MVE_VMULLBp16:
524     case MVE_VMULLBp8:
525     case MVE_VMULLBs16:
526     case MVE_VMULLBs32:
527     case MVE_VMULLBs8:
528     case MVE_VMULLBu16:
529     case MVE_VMULLBu32:
530     case MVE_VMULLBu8:
531     case MVE_VMULLTp16:
532     case MVE_VMULLTp8:
533     case MVE_VMULLTs16:
534     case MVE_VMULLTs32:
535     case MVE_VMULLTs8:
536     case MVE_VMULLTu16:
537     case MVE_VMULLTu32:
538     case MVE_VMULLTu8:
539     case MVE_VMUL_qr_f16:
540     case MVE_VMUL_qr_f32:
541     case MVE_VMUL_qr_i16:
542     case MVE_VMUL_qr_i32:
543     case MVE_VMUL_qr_i8:
544     case MVE_VMULf16:
545     case MVE_VMULf32:
546     case MVE_VMULi16:
547     case MVE_VMULi8:
548     case MVE_VMULi32:
549     case MVE_VMVN:
550     case MVE_VMVNimmi16:
551     case MVE_VMVNimmi32:
552     case MVE_VNEGf16:
553     case MVE_VNEGf32:
554     case MVE_VNEGs16:
555     case MVE_VNEGs32:
556     case MVE_VNEGs8:
557     case MVE_VORN:
558     case MVE_VORR:
559     case MVE_VORRimmi16:
560     case MVE_VORRimmi32:
561     case MVE_VPST:
562     case MVE_VQABSs16:
563     case MVE_VQABSs32:
564     case MVE_VQABSs8:
565     case MVE_VQADD_qr_s16:
566     case MVE_VQADD_qr_s32:
567     case MVE_VQADD_qr_s8:
568     case MVE_VQADD_qr_u16:
569     case MVE_VQADD_qr_u32:
570     case MVE_VQADD_qr_u8:
571     case MVE_VQADDs16:
572     case MVE_VQADDs32:
573     case MVE_VQADDs8:
574     case MVE_VQADDu16:
575     case MVE_VQADDu32:
576     case MVE_VQADDu8:
577     case MVE_VQDMULL_qr_s16bh:
578     case MVE_VQDMULL_qr_s16th:
579     case MVE_VQDMULL_qr_s32bh:
580     case MVE_VQDMULL_qr_s32th:
581     case MVE_VQDMULLs16bh:
582     case MVE_VQDMULLs16th:
583     case MVE_VQDMULLs32bh:
584     case MVE_VQDMULLs32th:
585     case MVE_VQNEGs16:
586     case MVE_VQNEGs32:
587     case MVE_VQNEGs8:
588     case MVE_VQMOVNs16bh:
589     case MVE_VQMOVNs16th:
590     case MVE_VQMOVNs32bh:
591     case MVE_VQMOVNs32th:
592     case MVE_VQMOVNu16bh:
593     case MVE_VQMOVNu16th:
594     case MVE_VQMOVNu32bh:
595     case MVE_VQMOVNu32th:
596     case MVE_VQMOVUNs16bh:
597     case MVE_VQMOVUNs16th:
598     case MVE_VQMOVUNs32bh:
599     case MVE_VQMOVUNs32th:
600     case MVE_VQRSHL_by_vecs16:
601     case MVE_VQRSHL_by_vecs32:
602     case MVE_VQRSHL_by_vecs8:
603     case MVE_VQRSHL_by_vecu16:
604     case MVE_VQRSHL_by_vecu32:
605     case MVE_VQRSHL_by_vecu8:
606     case MVE_VQRSHL_qrs16:
607     case MVE_VQRSHL_qrs32:
608     case MVE_VQRSHL_qrs8:
609     case MVE_VQRSHL_qru16:
610     case MVE_VQRSHL_qru8:
611     case MVE_VQRSHL_qru32:
612     case MVE_VQSHLU_imms16:
613     case MVE_VQSHLU_imms32:
614     case MVE_VQSHLU_imms8:
615     case MVE_VQSHLimms16:
616     case MVE_VQSHLimms32:
617     case MVE_VQSHLimms8:
618     case MVE_VQSHLimmu16:
619     case MVE_VQSHLimmu32:
620     case MVE_VQSHLimmu8:
621     case MVE_VQSHL_by_vecs16:
622     case MVE_VQSHL_by_vecs32:
623     case MVE_VQSHL_by_vecs8:
624     case MVE_VQSHL_by_vecu16:
625     case MVE_VQSHL_by_vecu32:
626     case MVE_VQSHL_by_vecu8:
627     case MVE_VQSHL_qrs16:
628     case MVE_VQSHL_qrs32:
629     case MVE_VQSHL_qrs8:
630     case MVE_VQSHL_qru16:
631     case MVE_VQSHL_qru32:
632     case MVE_VQSHL_qru8:
633     case MVE_VQRSHRNbhs16:
634     case MVE_VQRSHRNbhs32:
635     case MVE_VQRSHRNbhu16:
636     case MVE_VQRSHRNbhu32:
637     case MVE_VQRSHRNths16:
638     case MVE_VQRSHRNths32:
639     case MVE_VQRSHRNthu16:
640     case MVE_VQRSHRNthu32:
641     case MVE_VQRSHRUNs16bh:
642     case MVE_VQRSHRUNs16th:
643     case MVE_VQRSHRUNs32bh:
644     case MVE_VQRSHRUNs32th:
645     case MVE_VQSHRNbhs16:
646     case MVE_VQSHRNbhs32:
647     case MVE_VQSHRNbhu16:
648     case MVE_VQSHRNbhu32:
649     case MVE_VQSHRNths16:
650     case MVE_VQSHRNths32:
651     case MVE_VQSHRNthu16:
652     case MVE_VQSHRNthu32:
653     case MVE_VQSHRUNs16bh:
654     case MVE_VQSHRUNs16th:
655     case MVE_VQSHRUNs32bh:
656     case MVE_VQSHRUNs32th:
657     case MVE_VQSUB_qr_s16:
658     case MVE_VQSUB_qr_s32:
659     case MVE_VQSUB_qr_s8:
660     case MVE_VQSUB_qr_u16:
661     case MVE_VQSUB_qr_u32:
662     case MVE_VQSUB_qr_u8:
663     case MVE_VQSUBs16:
664     case MVE_VQSUBs32:
665     case MVE_VQSUBs8:
666     case MVE_VQSUBu16:
667     case MVE_VQSUBu32:
668     case MVE_VQSUBu8:
669     case MVE_VRHADDs16:
670     case MVE_VRHADDs32:
671     case MVE_VRHADDs8:
672     case MVE_VRHADDu16:
673     case MVE_VRHADDu32:
674     case MVE_VRHADDu8:
675     case MVE_VRINTf16A:
676     case MVE_VRINTf16M:
677     case MVE_VRINTf16N:
678     case MVE_VRINTf16P:
679     case MVE_VRINTf16X:
680     case MVE_VRINTf16Z:
681     case MVE_VRINTf32A:
682     case MVE_VRINTf32M:
683     case MVE_VRINTf32N:
684     case MVE_VRINTf32P:
685     case MVE_VRINTf32X:
686     case MVE_VRINTf32Z:
687     case MVE_VRSHL_by_vecs16:
688     case MVE_VRSHL_by_vecs32:
689     case MVE_VRSHL_by_vecs8:
690     case MVE_VRSHL_by_vecu16:
691     case MVE_VRSHL_by_vecu32:
692     case MVE_VRSHL_by_vecu8:
693     case MVE_VRSHL_qrs16:
694     case MVE_VRSHL_qrs32:
695     case MVE_VRSHL_qrs8:
696     case MVE_VRSHL_qru16:
697     case MVE_VRSHL_qru32:
698     case MVE_VRSHL_qru8:
699     case MVE_VRSHR_imms16:
700     case MVE_VRSHR_imms32:
701     case MVE_VRSHR_imms8:
702     case MVE_VRSHR_immu16:
703     case MVE_VRSHR_immu32:
704     case MVE_VRSHR_immu8:
705     case MVE_VRSHRNi16bh:
706     case MVE_VRSHRNi16th:
707     case MVE_VRSHRNi32bh:
708     case MVE_VRSHRNi32th:
709     case MVE_VSHL_by_vecs16:
710     case MVE_VSHL_by_vecs32:
711     case MVE_VSHL_by_vecs8:
712     case MVE_VSHL_by_vecu16:
713     case MVE_VSHL_by_vecu32:
714     case MVE_VSHL_by_vecu8:
715     case MVE_VSHL_immi16:
716     case MVE_VSHL_immi32:
717     case MVE_VSHL_immi8:
718     case MVE_VSHL_qrs16:
719     case MVE_VSHL_qrs32:
720     case MVE_VSHL_qrs8:
721     case MVE_VSHL_qru16:
722     case MVE_VSHL_qru32:
723     case MVE_VSHL_qru8:
724     case MVE_VSHR_imms16:
725     case MVE_VSHR_imms32:
726     case MVE_VSHR_imms8:
727     case MVE_VSHR_immu16:
728     case MVE_VSHR_immu32:
729     case MVE_VSHR_immu8:
730     case MVE_VSHRNi16bh:
731     case MVE_VSHRNi16th:
732     case MVE_VSHRNi32bh:
733     case MVE_VSHRNi32th:
734     case MVE_VSLIimm16:
735     case MVE_VSLIimm32:
736     case MVE_VSLIimm8:
737     case MVE_VSRIimm16:
738     case MVE_VSRIimm32:
739     case MVE_VSRIimm8:
740     case MVE_VSTRB16:
741     case MVE_VSTRB16_post:
742     case MVE_VSTRB16_pre:
743     case MVE_VSTRB16_rq:
744     case MVE_VSTRB32:
745     case MVE_VSTRB32_post:
746     case MVE_VSTRB32_pre:
747     case MVE_VSTRB32_rq:
748     case MVE_VSTRB8_rq:
749     case MVE_VSTRBU8:
750     case MVE_VSTRBU8_post:
751     case MVE_VSTRBU8_pre:
752     case MVE_VSTRD64_qi:
753     case MVE_VSTRD64_qi_pre:
754     case MVE_VSTRD64_rq:
755     case MVE_VSTRD64_rq_u:
756     case MVE_VSTRH16_rq:
757     case MVE_VSTRH16_rq_u:
758     case MVE_VSTRH32:
759     case MVE_VSTRH32_post:
760     case MVE_VSTRH32_pre:
761     case MVE_VSTRH32_rq:
762     case MVE_VSTRH32_rq_u:
763     case MVE_VSTRHU16:
764     case MVE_VSTRHU16_post:
765     case MVE_VSTRHU16_pre:
766     case MVE_VSTRW32_qi:
767     case MVE_VSTRW32_qi_pre:
768     case MVE_VSTRW32_rq:
769     case MVE_VSTRW32_rq_u:
770     case MVE_VSTRWU32:
771     case MVE_VSTRWU32_post:
772     case MVE_VSTRWU32_pre:
773     case MVE_VSUB_qr_f16:
774     case MVE_VSUB_qr_f32:
775     case MVE_VSUB_qr_i16:
776     case MVE_VSUB_qr_i32:
777     case MVE_VSUB_qr_i8:
778     case MVE_VSUBf16:
779     case MVE_VSUBf32:
780     case MVE_VSUBi16:
781     case MVE_VSUBi32:
782     case MVE_VSUBi8:
783       return true;
784     }
785   };
786 
787   LLVMInitializeARMTargetInfo();
788   LLVMInitializeARMTarget();
789   LLVMInitializeARMTargetMC();
790 
791   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
792   std::string Error;
793   const Target *T = TargetRegistry::lookupTarget(TT, Error);
794   if (!T) {
795     dbgs() << Error;
796     return;
797   }
798 
799   TargetOptions Options;
800   auto TM = std::unique_ptr<LLVMTargetMachine>(
801     static_cast<LLVMTargetMachine*>(
802       T->createTargetMachine(TT, "generic", "", Options, None, None,
803                              CodeGenOpt::Default)));
804   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
805                   std::string(TM->getTargetFeatureString()),
806                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
807   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
808   auto MII = TM->getMCInstrInfo();
809 
810   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
811     const MCInstrDesc &Desc = TII->get(i);
812 
813     for (auto &Op : Desc.operands()) {
814       // Only check instructions that access the MQPR regs.
815       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
816           Op.RegClass != ARM::MQPRRegClassID)
817         continue;
818 
819       uint64_t Flags = MII->get(i).TSFlags;
820       bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
821       ASSERT_EQ(IsValidTPOpcode(i), Valid)
822                 << MII->getName(i)
823                 << ": mismatched expectation for tail-predicated safety\n";
824       break;
825     }
826   }
827 }
828 
829 TEST(MachineInstr, HasSideEffects) {
830   using namespace ARM;
831   unsigned Opcodes[] = {
832       // MVE Loads/Stores
833       MVE_VLDRBS16,        MVE_VLDRBS16_post,   MVE_VLDRBS16_pre,
834       MVE_VLDRBS16_rq,     MVE_VLDRBS32,        MVE_VLDRBS32_post,
835       MVE_VLDRBS32_pre,    MVE_VLDRBS32_rq,     MVE_VLDRBU16,
836       MVE_VLDRBU16_post,   MVE_VLDRBU16_pre,    MVE_VLDRBU16_rq,
837       MVE_VLDRBU32,        MVE_VLDRBU32_post,   MVE_VLDRBU32_pre,
838       MVE_VLDRBU32_rq,     MVE_VLDRBU8,         MVE_VLDRBU8_post,
839       MVE_VLDRBU8_pre,     MVE_VLDRBU8_rq,      MVE_VLDRDU64_qi,
840       MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq,     MVE_VLDRDU64_rq_u,
841       MVE_VLDRHS32,        MVE_VLDRHS32_post,   MVE_VLDRHS32_pre,
842       MVE_VLDRHS32_rq,     MVE_VLDRHS32_rq_u,   MVE_VLDRHU16,
843       MVE_VLDRHU16_post,   MVE_VLDRHU16_pre,    MVE_VLDRHU16_rq,
844       MVE_VLDRHU16_rq_u,   MVE_VLDRHU32,        MVE_VLDRHU32_post,
845       MVE_VLDRHU32_pre,    MVE_VLDRHU32_rq,     MVE_VLDRHU32_rq_u,
846       MVE_VLDRWU32,        MVE_VLDRWU32_post,   MVE_VLDRWU32_pre,
847       MVE_VLDRWU32_qi,     MVE_VLDRWU32_qi_pre, MVE_VLDRWU32_rq,
848       MVE_VLDRWU32_rq_u,   MVE_VLD20_16,        MVE_VLD20_16_wb,
849       MVE_VLD20_32,        MVE_VLD20_32_wb,     MVE_VLD20_8,
850       MVE_VLD20_8_wb,      MVE_VLD21_16,        MVE_VLD21_16_wb,
851       MVE_VLD21_32,        MVE_VLD21_32_wb,     MVE_VLD21_8,
852       MVE_VLD21_8_wb,      MVE_VLD40_16,        MVE_VLD40_16_wb,
853       MVE_VLD40_32,        MVE_VLD40_32_wb,     MVE_VLD40_8,
854       MVE_VLD40_8_wb,      MVE_VLD41_16,        MVE_VLD41_16_wb,
855       MVE_VLD41_32,        MVE_VLD41_32_wb,     MVE_VLD41_8,
856       MVE_VLD41_8_wb,      MVE_VLD42_16,        MVE_VLD42_16_wb,
857       MVE_VLD42_32,        MVE_VLD42_32_wb,     MVE_VLD42_8,
858       MVE_VLD42_8_wb,      MVE_VLD43_16,        MVE_VLD43_16_wb,
859       MVE_VLD43_32,        MVE_VLD43_32_wb,     MVE_VLD43_8,
860       MVE_VLD43_8_wb,      MVE_VSTRB16,         MVE_VSTRB16_post,
861       MVE_VSTRB16_pre,     MVE_VSTRB16_rq,      MVE_VSTRB32,
862       MVE_VSTRB32_post,    MVE_VSTRB32_pre,     MVE_VSTRB32_rq,
863       MVE_VSTRB8_rq,       MVE_VSTRBU8,         MVE_VSTRBU8_post,
864       MVE_VSTRBU8_pre,     MVE_VSTRD64_qi,      MVE_VSTRD64_qi_pre,
865       MVE_VSTRD64_rq,      MVE_VSTRD64_rq_u,    MVE_VSTRH16_rq,
866       MVE_VSTRH16_rq_u,    MVE_VSTRH32,         MVE_VSTRH32_post,
867       MVE_VSTRH32_pre,     MVE_VSTRH32_rq,      MVE_VSTRH32_rq_u,
868       MVE_VSTRHU16,        MVE_VSTRHU16_post,   MVE_VSTRHU16_pre,
869       MVE_VSTRW32_qi,      MVE_VSTRW32_qi_pre,  MVE_VSTRW32_rq,
870       MVE_VSTRW32_rq_u,    MVE_VSTRWU32,        MVE_VSTRWU32_post,
871       MVE_VSTRWU32_pre,    MVE_VST20_16,        MVE_VST20_16_wb,
872       MVE_VST20_32,        MVE_VST20_32_wb,     MVE_VST20_8,
873       MVE_VST20_8_wb,      MVE_VST21_16,        MVE_VST21_16_wb,
874       MVE_VST21_32,        MVE_VST21_32_wb,     MVE_VST21_8,
875       MVE_VST21_8_wb,      MVE_VST40_16,        MVE_VST40_16_wb,
876       MVE_VST40_32,        MVE_VST40_32_wb,     MVE_VST40_8,
877       MVE_VST40_8_wb,      MVE_VST41_16,        MVE_VST41_16_wb,
878       MVE_VST41_32,        MVE_VST41_32_wb,     MVE_VST41_8,
879       MVE_VST41_8_wb,      MVE_VST42_16,        MVE_VST42_16_wb,
880       MVE_VST42_32,        MVE_VST42_32_wb,     MVE_VST42_8,
881       MVE_VST42_8_wb,      MVE_VST43_16,        MVE_VST43_16_wb,
882       MVE_VST43_32,        MVE_VST43_32_wb,     MVE_VST43_8,
883       MVE_VST43_8_wb,
884   };
885 
886   LLVMInitializeARMTargetInfo();
887   LLVMInitializeARMTarget();
888   LLVMInitializeARMTargetMC();
889 
890   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
891   std::string Error;
892   const Target *T = TargetRegistry::lookupTarget(TT, Error);
893   if (!T) {
894     dbgs() << Error;
895     return;
896   }
897 
898   TargetOptions Options;
899   auto TM = std::unique_ptr<LLVMTargetMachine>(
900       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
901           TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
902   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
903                   std::string(TM->getTargetFeatureString()),
904                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
905   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
906   auto MII = TM->getMCInstrInfo();
907 
908   for (unsigned Op : Opcodes) {
909     const MCInstrDesc &Desc = TII->get(Op);
910     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
911         << MII->getName(Op) << " has unexpected side effects";
912   }
913 }
914