1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
14   using namespace ARM;
15 
16   auto RetainsPreviousHalfElement = [](unsigned Opcode) {
17     switch (Opcode) {
18     default:
19       break;
20     case MVE_VMOVNi16bh:
21     case MVE_VMOVNi16th:
22     case MVE_VMOVNi32bh:
23     case MVE_VMOVNi32th:
24     case MVE_VQMOVNs16bh:
25     case MVE_VQMOVNs16th:
26     case MVE_VQMOVNs32bh:
27     case MVE_VQMOVNs32th:
28     case MVE_VQMOVNu16bh:
29     case MVE_VQMOVNu16th:
30     case MVE_VQMOVNu32bh:
31     case MVE_VQMOVNu32th:
32     case MVE_VQMOVUNs16bh:
33     case MVE_VQMOVUNs16th:
34     case MVE_VQMOVUNs32bh:
35     case MVE_VQMOVUNs32th:
36     case MVE_VQRSHRNbhs16:
37     case MVE_VQRSHRNbhs32:
38     case MVE_VQRSHRNbhu16:
39     case MVE_VQRSHRNbhu32:
40     case MVE_VQRSHRNths16:
41     case MVE_VQRSHRNths32:
42     case MVE_VQRSHRNthu16:
43     case MVE_VQRSHRNthu32:
44     case MVE_VQRSHRUNs16bh:
45     case MVE_VQRSHRUNs16th:
46     case MVE_VQRSHRUNs32bh:
47     case MVE_VQRSHRUNs32th:
48     case MVE_VQSHRNbhs16:
49     case MVE_VQSHRNbhs32:
50     case MVE_VQSHRNbhu16:
51     case MVE_VQSHRNbhu32:
52     case MVE_VQSHRNths16:
53     case MVE_VQSHRNths32:
54     case MVE_VQSHRNthu16:
55     case MVE_VQSHRNthu32:
56     case MVE_VQSHRUNs16bh:
57     case MVE_VQSHRUNs16th:
58     case MVE_VQSHRUNs32bh:
59     case MVE_VQSHRUNs32th:
60     case MVE_VRSHRNi16bh:
61     case MVE_VRSHRNi16th:
62     case MVE_VRSHRNi32bh:
63     case MVE_VRSHRNi32th:
64     case MVE_VSHRNi16bh:
65     case MVE_VSHRNi16th:
66     case MVE_VSHRNi32bh:
67     case MVE_VSHRNi32th:
68     case MVE_VCVTf16f32bh:
69     case MVE_VCVTf16f32th:
70     case MVE_VCVTf32f16bh:
71     case MVE_VCVTf32f16th:
72       return true;
73     }
74     return false;
75   };
76 
77   LLVMInitializeARMTargetInfo();
78   LLVMInitializeARMTarget();
79   LLVMInitializeARMTargetMC();
80 
81   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
82   std::string Error;
83   const Target *T = TargetRegistry::lookupTarget(TT, Error);
84   if (!T) {
85     dbgs() << Error;
86     return;
87   }
88 
89   TargetOptions Options;
90   auto TM = std::unique_ptr<LLVMTargetMachine>(
91     static_cast<LLVMTargetMachine*>(
92       T->createTargetMachine(TT, "generic", "", Options, None, None,
93                              CodeGenOpt::Default)));
94   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
95                   std::string(TM->getTargetFeatureString()),
96                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
97   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
98   auto MII = TM->getMCInstrInfo();
99 
100   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
101     const MCInstrDesc &Desc = TII->get(i);
102 
103     uint64_t Flags = Desc.TSFlags;
104     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
105       continue;
106 
107     bool Valid = (Flags & ARMII::RetainsPreviousHalfElement) != 0;
108     ASSERT_EQ(RetainsPreviousHalfElement(i), Valid)
109               << MII->getName(i)
110               << ": mismatched expectation for tail-predicated safety\n";
111   }
112 }
113 // Test for instructions that aren't immediately obviously valid within a
114 // tail-predicated loop. This should be marked up in their tablegen
115 // descriptions. Currently we, conservatively, disallow:
116 // - cross beat carries.
117 // - complex operations.
118 // - horizontal operations.
119 // - byte swapping.
120 // - interleaved memory instructions.
121 // TODO: Add to this list once we can handle them safely.
122 TEST(MachineInstrValidTailPredication, IsCorrect) {
123 
124   using namespace ARM;
125 
126   auto IsValidTPOpcode = [](unsigned Opcode) {
127     switch (Opcode) {
128     default:
129       return false;
130     case MVE_ASRLi:
131     case MVE_ASRLr:
132     case MVE_LSRL:
133     case MVE_SQRSHR:
134     case MVE_SQSHL:
135     case MVE_SRSHR:
136     case MVE_UQRSHL:
137     case MVE_UQSHL:
138     case MVE_URSHR:
139     case MVE_VABDf16:
140     case MVE_VABDf32:
141     case MVE_VABDs16:
142     case MVE_VABDs32:
143     case MVE_VABDs8:
144     case MVE_VABDu16:
145     case MVE_VABDu32:
146     case MVE_VABDu8:
147     case MVE_VABSf16:
148     case MVE_VABSf32:
149     case MVE_VABSs16:
150     case MVE_VABSs32:
151     case MVE_VABSs8:
152     case MVE_VADD_qr_f16:
153     case MVE_VADD_qr_f32:
154     case MVE_VADD_qr_i16:
155     case MVE_VADD_qr_i32:
156     case MVE_VADD_qr_i8:
157     case MVE_VADDf16:
158     case MVE_VADDf32:
159     case MVE_VADDi16:
160     case MVE_VADDi32:
161     case MVE_VADDi8:
162     case MVE_VAND:
163     case MVE_VBIC:
164     case MVE_VBICimmi16:
165     case MVE_VBICimmi32:
166     case MVE_VBRSR16:
167     case MVE_VBRSR32:
168     case MVE_VBRSR8:
169     case MVE_VCLSs16:
170     case MVE_VCLSs32:
171     case MVE_VCLSs8:
172     case MVE_VCLZs16:
173     case MVE_VCLZs32:
174     case MVE_VCLZs8:
175     case MVE_VCMPf16:
176     case MVE_VCMPf16r:
177     case MVE_VCMPf32:
178     case MVE_VCMPf32r:
179     case MVE_VCMPi16:
180     case MVE_VCMPi16r:
181     case MVE_VCMPi32:
182     case MVE_VCMPi32r:
183     case MVE_VCMPi8:
184     case MVE_VCMPi8r:
185     case MVE_VCMPs16:
186     case MVE_VCMPs16r:
187     case MVE_VCMPs32:
188     case MVE_VCMPs32r:
189     case MVE_VCMPs8:
190     case MVE_VCMPs8r:
191     case MVE_VCMPu16:
192     case MVE_VCMPu16r:
193     case MVE_VCMPu32:
194     case MVE_VCMPu32r:
195     case MVE_VCMPu8:
196     case MVE_VCMPu8r:
197     case MVE_VCTP16:
198     case MVE_VCTP32:
199     case MVE_VCTP64:
200     case MVE_VCTP8:
201     case MVE_VCVTf16s16_fix:
202     case MVE_VCVTf16s16n:
203     case MVE_VCVTf16u16_fix:
204     case MVE_VCVTf16u16n:
205     case MVE_VCVTf32s32_fix:
206     case MVE_VCVTf32s32n:
207     case MVE_VCVTf32u32_fix:
208     case MVE_VCVTf32u32n:
209     case MVE_VCVTs16f16_fix:
210     case MVE_VCVTs16f16a:
211     case MVE_VCVTs16f16m:
212     case MVE_VCVTs16f16n:
213     case MVE_VCVTs16f16p:
214     case MVE_VCVTs16f16z:
215     case MVE_VCVTs32f32_fix:
216     case MVE_VCVTs32f32a:
217     case MVE_VCVTs32f32m:
218     case MVE_VCVTs32f32n:
219     case MVE_VCVTs32f32p:
220     case MVE_VCVTs32f32z:
221     case MVE_VCVTu16f16_fix:
222     case MVE_VCVTu16f16a:
223     case MVE_VCVTu16f16m:
224     case MVE_VCVTu16f16n:
225     case MVE_VCVTu16f16p:
226     case MVE_VCVTu16f16z:
227     case MVE_VCVTu32f32_fix:
228     case MVE_VCVTu32f32a:
229     case MVE_VCVTu32f32m:
230     case MVE_VCVTu32f32n:
231     case MVE_VCVTu32f32p:
232     case MVE_VCVTu32f32z:
233     case MVE_VDDUPu16:
234     case MVE_VDDUPu32:
235     case MVE_VDDUPu8:
236     case MVE_VDUP16:
237     case MVE_VDUP32:
238     case MVE_VDUP8:
239     case MVE_VDWDUPu16:
240     case MVE_VDWDUPu32:
241     case MVE_VDWDUPu8:
242     case MVE_VEOR:
243     case MVE_VFMA_qr_Sf16:
244     case MVE_VFMA_qr_Sf32:
245     case MVE_VFMA_qr_f16:
246     case MVE_VFMA_qr_f32:
247     case MVE_VFMAf16:
248     case MVE_VFMAf32:
249     case MVE_VFMSf16:
250     case MVE_VFMSf32:
251     case MVE_VMAXAs16:
252     case MVE_VMAXAs32:
253     case MVE_VMAXAs8:
254     case MVE_VMAXs16:
255     case MVE_VMAXs32:
256     case MVE_VMAXs8:
257     case MVE_VMAXu16:
258     case MVE_VMAXu32:
259     case MVE_VMAXu8:
260     case MVE_VMINAs16:
261     case MVE_VMINAs32:
262     case MVE_VMINAs8:
263     case MVE_VMINs16:
264     case MVE_VMINs32:
265     case MVE_VMINs8:
266     case MVE_VMINu16:
267     case MVE_VMINu32:
268     case MVE_VMINu8:
269     case MVE_VMLAS_qr_s16:
270     case MVE_VMLAS_qr_s32:
271     case MVE_VMLAS_qr_s8:
272     case MVE_VMLAS_qr_u16:
273     case MVE_VMLAS_qr_u32:
274     case MVE_VMLAS_qr_u8:
275     case MVE_VMLA_qr_s16:
276     case MVE_VMLA_qr_s32:
277     case MVE_VMLA_qr_s8:
278     case MVE_VMLA_qr_u16:
279     case MVE_VMLA_qr_u32:
280     case MVE_VMLA_qr_u8:
281     case MVE_VHADD_qr_s16:
282     case MVE_VHADD_qr_s32:
283     case MVE_VHADD_qr_s8:
284     case MVE_VHADD_qr_u16:
285     case MVE_VHADD_qr_u32:
286     case MVE_VHADD_qr_u8:
287     case MVE_VHADDs16:
288     case MVE_VHADDs32:
289     case MVE_VHADDs8:
290     case MVE_VHADDu16:
291     case MVE_VHADDu32:
292     case MVE_VHADDu8:
293     case MVE_VHSUB_qr_s16:
294     case MVE_VHSUB_qr_s32:
295     case MVE_VHSUB_qr_s8:
296     case MVE_VHSUB_qr_u16:
297     case MVE_VHSUB_qr_u32:
298     case MVE_VHSUB_qr_u8:
299     case MVE_VHSUBs16:
300     case MVE_VHSUBs32:
301     case MVE_VHSUBs8:
302     case MVE_VHSUBu16:
303     case MVE_VHSUBu32:
304     case MVE_VHSUBu8:
305     case MVE_VIDUPu16:
306     case MVE_VIDUPu32:
307     case MVE_VIDUPu8:
308     case MVE_VIWDUPu16:
309     case MVE_VIWDUPu32:
310     case MVE_VIWDUPu8:
311     case MVE_VLDRBS16:
312     case MVE_VLDRBS16_post:
313     case MVE_VLDRBS16_pre:
314     case MVE_VLDRBS16_rq:
315     case MVE_VLDRBS32:
316     case MVE_VLDRBS32_post:
317     case MVE_VLDRBS32_pre:
318     case MVE_VLDRBS32_rq:
319     case MVE_VLDRBU16:
320     case MVE_VLDRBU16_post:
321     case MVE_VLDRBU16_pre:
322     case MVE_VLDRBU16_rq:
323     case MVE_VLDRBU32:
324     case MVE_VLDRBU32_post:
325     case MVE_VLDRBU32_pre:
326     case MVE_VLDRBU32_rq:
327     case MVE_VLDRBU8:
328     case MVE_VLDRBU8_post:
329     case MVE_VLDRBU8_pre:
330     case MVE_VLDRBU8_rq:
331     case MVE_VLDRDU64_qi:
332     case MVE_VLDRDU64_qi_pre:
333     case MVE_VLDRDU64_rq:
334     case MVE_VLDRDU64_rq_u:
335     case MVE_VLDRHS32:
336     case MVE_VLDRHS32_post:
337     case MVE_VLDRHS32_pre:
338     case MVE_VLDRHS32_rq:
339     case MVE_VLDRHS32_rq_u:
340     case MVE_VLDRHU16:
341     case MVE_VLDRHU16_post:
342     case MVE_VLDRHU16_pre:
343     case MVE_VLDRHU16_rq:
344     case MVE_VLDRHU16_rq_u:
345     case MVE_VLDRHU32:
346     case MVE_VLDRHU32_post:
347     case MVE_VLDRHU32_pre:
348     case MVE_VLDRHU32_rq:
349     case MVE_VLDRHU32_rq_u:
350     case MVE_VLDRWU32:
351     case MVE_VLDRWU32_post:
352     case MVE_VLDRWU32_pre:
353     case MVE_VLDRWU32_qi:
354     case MVE_VLDRWU32_qi_pre:
355     case MVE_VLDRWU32_rq:
356     case MVE_VLDRWU32_rq_u:
357     case MVE_VMOVimmf32:
358     case MVE_VMOVimmi16:
359     case MVE_VMOVimmi32:
360     case MVE_VMOVimmi64:
361     case MVE_VMOVimmi8:
362     case MVE_VMOVNi16bh:
363     case MVE_VMOVNi16th:
364     case MVE_VMOVNi32bh:
365     case MVE_VMOVNi32th:
366     case MVE_VMULLBp16:
367     case MVE_VMULLBp8:
368     case MVE_VMULLBs16:
369     case MVE_VMULLBs32:
370     case MVE_VMULLBs8:
371     case MVE_VMULLBu16:
372     case MVE_VMULLBu32:
373     case MVE_VMULLBu8:
374     case MVE_VMULLTp16:
375     case MVE_VMULLTp8:
376     case MVE_VMULLTs16:
377     case MVE_VMULLTs32:
378     case MVE_VMULLTs8:
379     case MVE_VMULLTu16:
380     case MVE_VMULLTu32:
381     case MVE_VMULLTu8:
382     case MVE_VMUL_qr_f16:
383     case MVE_VMUL_qr_f32:
384     case MVE_VMUL_qr_i16:
385     case MVE_VMUL_qr_i32:
386     case MVE_VMUL_qr_i8:
387     case MVE_VMULf16:
388     case MVE_VMULf32:
389     case MVE_VMULi16:
390     case MVE_VMULi8:
391     case MVE_VMULi32:
392     case MVE_VMVN:
393     case MVE_VMVNimmi16:
394     case MVE_VMVNimmi32:
395     case MVE_VNEGf16:
396     case MVE_VNEGf32:
397     case MVE_VNEGs16:
398     case MVE_VNEGs32:
399     case MVE_VNEGs8:
400     case MVE_VORN:
401     case MVE_VORR:
402     case MVE_VORRimmi16:
403     case MVE_VORRimmi32:
404     case MVE_VPST:
405     case MVE_VQABSs16:
406     case MVE_VQABSs32:
407     case MVE_VQABSs8:
408     case MVE_VQADD_qr_s16:
409     case MVE_VQADD_qr_s32:
410     case MVE_VQADD_qr_s8:
411     case MVE_VQADD_qr_u16:
412     case MVE_VQADD_qr_u32:
413     case MVE_VQADD_qr_u8:
414     case MVE_VQADDs16:
415     case MVE_VQADDs32:
416     case MVE_VQADDs8:
417     case MVE_VQADDu16:
418     case MVE_VQADDu32:
419     case MVE_VQADDu8:
420     case MVE_VQDMULL_qr_s16bh:
421     case MVE_VQDMULL_qr_s16th:
422     case MVE_VQDMULL_qr_s32bh:
423     case MVE_VQDMULL_qr_s32th:
424     case MVE_VQDMULLs16bh:
425     case MVE_VQDMULLs16th:
426     case MVE_VQDMULLs32bh:
427     case MVE_VQDMULLs32th:
428     case MVE_VQNEGs16:
429     case MVE_VQNEGs32:
430     case MVE_VQNEGs8:
431     case MVE_VQMOVNs16bh:
432     case MVE_VQMOVNs16th:
433     case MVE_VQMOVNs32bh:
434     case MVE_VQMOVNs32th:
435     case MVE_VQMOVNu16bh:
436     case MVE_VQMOVNu16th:
437     case MVE_VQMOVNu32bh:
438     case MVE_VQMOVNu32th:
439     case MVE_VQMOVUNs16bh:
440     case MVE_VQMOVUNs16th:
441     case MVE_VQMOVUNs32bh:
442     case MVE_VQMOVUNs32th:
443     case MVE_VQRSHL_by_vecs16:
444     case MVE_VQRSHL_by_vecs32:
445     case MVE_VQRSHL_by_vecs8:
446     case MVE_VQRSHL_by_vecu16:
447     case MVE_VQRSHL_by_vecu32:
448     case MVE_VQRSHL_by_vecu8:
449     case MVE_VQRSHL_qrs16:
450     case MVE_VQRSHL_qrs32:
451     case MVE_VQRSHL_qrs8:
452     case MVE_VQRSHL_qru16:
453     case MVE_VQRSHL_qru8:
454     case MVE_VQRSHL_qru32:
455     case MVE_VQSHLU_imms16:
456     case MVE_VQSHLU_imms32:
457     case MVE_VQSHLU_imms8:
458     case MVE_VQSHLimms16:
459     case MVE_VQSHLimms32:
460     case MVE_VQSHLimms8:
461     case MVE_VQSHLimmu16:
462     case MVE_VQSHLimmu32:
463     case MVE_VQSHLimmu8:
464     case MVE_VQSHL_by_vecs16:
465     case MVE_VQSHL_by_vecs32:
466     case MVE_VQSHL_by_vecs8:
467     case MVE_VQSHL_by_vecu16:
468     case MVE_VQSHL_by_vecu32:
469     case MVE_VQSHL_by_vecu8:
470     case MVE_VQSHL_qrs16:
471     case MVE_VQSHL_qrs32:
472     case MVE_VQSHL_qrs8:
473     case MVE_VQSHL_qru16:
474     case MVE_VQSHL_qru32:
475     case MVE_VQSHL_qru8:
476     case MVE_VQRSHRNbhs16:
477     case MVE_VQRSHRNbhs32:
478     case MVE_VQRSHRNbhu16:
479     case MVE_VQRSHRNbhu32:
480     case MVE_VQRSHRNths16:
481     case MVE_VQRSHRNths32:
482     case MVE_VQRSHRNthu16:
483     case MVE_VQRSHRNthu32:
484     case MVE_VQRSHRUNs16bh:
485     case MVE_VQRSHRUNs16th:
486     case MVE_VQRSHRUNs32bh:
487     case MVE_VQRSHRUNs32th:
488     case MVE_VQSHRNbhs16:
489     case MVE_VQSHRNbhs32:
490     case MVE_VQSHRNbhu16:
491     case MVE_VQSHRNbhu32:
492     case MVE_VQSHRNths16:
493     case MVE_VQSHRNths32:
494     case MVE_VQSHRNthu16:
495     case MVE_VQSHRNthu32:
496     case MVE_VQSHRUNs16bh:
497     case MVE_VQSHRUNs16th:
498     case MVE_VQSHRUNs32bh:
499     case MVE_VQSHRUNs32th:
500     case MVE_VQSUB_qr_s16:
501     case MVE_VQSUB_qr_s32:
502     case MVE_VQSUB_qr_s8:
503     case MVE_VQSUB_qr_u16:
504     case MVE_VQSUB_qr_u32:
505     case MVE_VQSUB_qr_u8:
506     case MVE_VQSUBs16:
507     case MVE_VQSUBs32:
508     case MVE_VQSUBs8:
509     case MVE_VQSUBu16:
510     case MVE_VQSUBu32:
511     case MVE_VQSUBu8:
512     case MVE_VRHADDs16:
513     case MVE_VRHADDs32:
514     case MVE_VRHADDs8:
515     case MVE_VRHADDu16:
516     case MVE_VRHADDu32:
517     case MVE_VRHADDu8:
518     case MVE_VRINTf16A:
519     case MVE_VRINTf16M:
520     case MVE_VRINTf16N:
521     case MVE_VRINTf16P:
522     case MVE_VRINTf16X:
523     case MVE_VRINTf16Z:
524     case MVE_VRINTf32A:
525     case MVE_VRINTf32M:
526     case MVE_VRINTf32N:
527     case MVE_VRINTf32P:
528     case MVE_VRINTf32X:
529     case MVE_VRINTf32Z:
530     case MVE_VRSHL_by_vecs16:
531     case MVE_VRSHL_by_vecs32:
532     case MVE_VRSHL_by_vecs8:
533     case MVE_VRSHL_by_vecu16:
534     case MVE_VRSHL_by_vecu32:
535     case MVE_VRSHL_by_vecu8:
536     case MVE_VRSHL_qrs16:
537     case MVE_VRSHL_qrs32:
538     case MVE_VRSHL_qrs8:
539     case MVE_VRSHL_qru16:
540     case MVE_VRSHL_qru32:
541     case MVE_VRSHL_qru8:
542     case MVE_VRSHR_imms16:
543     case MVE_VRSHR_imms32:
544     case MVE_VRSHR_imms8:
545     case MVE_VRSHR_immu16:
546     case MVE_VRSHR_immu32:
547     case MVE_VRSHR_immu8:
548     case MVE_VRSHRNi16bh:
549     case MVE_VRSHRNi16th:
550     case MVE_VRSHRNi32bh:
551     case MVE_VRSHRNi32th:
552     case MVE_VSHL_by_vecs16:
553     case MVE_VSHL_by_vecs32:
554     case MVE_VSHL_by_vecs8:
555     case MVE_VSHL_by_vecu16:
556     case MVE_VSHL_by_vecu32:
557     case MVE_VSHL_by_vecu8:
558     case MVE_VSHL_immi16:
559     case MVE_VSHL_immi32:
560     case MVE_VSHL_immi8:
561     case MVE_VSHL_qrs16:
562     case MVE_VSHL_qrs32:
563     case MVE_VSHL_qrs8:
564     case MVE_VSHL_qru16:
565     case MVE_VSHL_qru32:
566     case MVE_VSHL_qru8:
567     case MVE_VSHR_imms16:
568     case MVE_VSHR_imms32:
569     case MVE_VSHR_imms8:
570     case MVE_VSHR_immu16:
571     case MVE_VSHR_immu32:
572     case MVE_VSHR_immu8:
573     case MVE_VSHRNi16bh:
574     case MVE_VSHRNi16th:
575     case MVE_VSHRNi32bh:
576     case MVE_VSHRNi32th:
577     case MVE_VSLIimm16:
578     case MVE_VSLIimm32:
579     case MVE_VSLIimm8:
580     case MVE_VSRIimm16:
581     case MVE_VSRIimm32:
582     case MVE_VSRIimm8:
583     case MVE_VSTRB16:
584     case MVE_VSTRB16_post:
585     case MVE_VSTRB16_pre:
586     case MVE_VSTRB16_rq:
587     case MVE_VSTRB32:
588     case MVE_VSTRB32_post:
589     case MVE_VSTRB32_pre:
590     case MVE_VSTRB32_rq:
591     case MVE_VSTRB8_rq:
592     case MVE_VSTRBU8:
593     case MVE_VSTRBU8_post:
594     case MVE_VSTRBU8_pre:
595     case MVE_VSTRD64_qi:
596     case MVE_VSTRD64_qi_pre:
597     case MVE_VSTRD64_rq:
598     case MVE_VSTRD64_rq_u:
599     case MVE_VSTRH16_rq:
600     case MVE_VSTRH16_rq_u:
601     case MVE_VSTRH32:
602     case MVE_VSTRH32_post:
603     case MVE_VSTRH32_pre:
604     case MVE_VSTRH32_rq:
605     case MVE_VSTRH32_rq_u:
606     case MVE_VSTRHU16:
607     case MVE_VSTRHU16_post:
608     case MVE_VSTRHU16_pre:
609     case MVE_VSTRW32_qi:
610     case MVE_VSTRW32_qi_pre:
611     case MVE_VSTRW32_rq:
612     case MVE_VSTRW32_rq_u:
613     case MVE_VSTRWU32:
614     case MVE_VSTRWU32_post:
615     case MVE_VSTRWU32_pre:
616     case MVE_VSUB_qr_f16:
617     case MVE_VSUB_qr_f32:
618     case MVE_VSUB_qr_i16:
619     case MVE_VSUB_qr_i32:
620     case MVE_VSUB_qr_i8:
621     case MVE_VSUBf16:
622     case MVE_VSUBf32:
623     case MVE_VSUBi16:
624     case MVE_VSUBi32:
625     case MVE_VSUBi8:
626       return true;
627     }
628   };
629 
630   LLVMInitializeARMTargetInfo();
631   LLVMInitializeARMTarget();
632   LLVMInitializeARMTargetMC();
633 
634   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
635   std::string Error;
636   const Target *T = TargetRegistry::lookupTarget(TT, Error);
637   if (!T) {
638     dbgs() << Error;
639     return;
640   }
641 
642   TargetOptions Options;
643   auto TM = std::unique_ptr<LLVMTargetMachine>(
644     static_cast<LLVMTargetMachine*>(
645       T->createTargetMachine(TT, "generic", "", Options, None, None,
646                              CodeGenOpt::Default)));
647   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
648                   std::string(TM->getTargetFeatureString()),
649                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
650   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
651   auto MII = TM->getMCInstrInfo();
652 
653   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
654     const MCInstrDesc &Desc = TII->get(i);
655 
656     for (auto &Op : Desc.operands()) {
657       // Only check instructions that access the MQPR regs.
658       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
659           Op.RegClass != ARM::MQPRRegClassID)
660         continue;
661 
662       uint64_t Flags = MII->get(i).TSFlags;
663       bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
664       ASSERT_EQ(IsValidTPOpcode(i), Valid)
665                 << MII->getName(i)
666                 << ": mismatched expectation for tail-predicated safety\n";
667       break;
668     }
669   }
670 }
671 
672 TEST(MachineInstr, HasSideEffects) {
673   using namespace ARM;
674   unsigned Opcodes[] = {
675       // MVE Loads/Stores
676       MVE_VLDRBS16,        MVE_VLDRBS16_post,   MVE_VLDRBS16_pre,
677       MVE_VLDRBS16_rq,     MVE_VLDRBS32,        MVE_VLDRBS32_post,
678       MVE_VLDRBS32_pre,    MVE_VLDRBS32_rq,     MVE_VLDRBU16,
679       MVE_VLDRBU16_post,   MVE_VLDRBU16_pre,    MVE_VLDRBU16_rq,
680       MVE_VLDRBU32,        MVE_VLDRBU32_post,   MVE_VLDRBU32_pre,
681       MVE_VLDRBU32_rq,     MVE_VLDRBU8,         MVE_VLDRBU8_post,
682       MVE_VLDRBU8_pre,     MVE_VLDRBU8_rq,      MVE_VLDRDU64_qi,
683       MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq,     MVE_VLDRDU64_rq_u,
684       MVE_VLDRHS32,        MVE_VLDRHS32_post,   MVE_VLDRHS32_pre,
685       MVE_VLDRHS32_rq,     MVE_VLDRHS32_rq_u,   MVE_VLDRHU16,
686       MVE_VLDRHU16_post,   MVE_VLDRHU16_pre,    MVE_VLDRHU16_rq,
687       MVE_VLDRHU16_rq_u,   MVE_VLDRHU32,        MVE_VLDRHU32_post,
688       MVE_VLDRHU32_pre,    MVE_VLDRHU32_rq,     MVE_VLDRHU32_rq_u,
689       MVE_VLDRWU32,        MVE_VLDRWU32_post,   MVE_VLDRWU32_pre,
690       MVE_VLDRWU32_qi,     MVE_VLDRWU32_qi_pre, MVE_VLDRWU32_rq,
691       MVE_VLDRWU32_rq_u,   MVE_VLD20_16,        MVE_VLD20_16_wb,
692       MVE_VLD20_32,        MVE_VLD20_32_wb,     MVE_VLD20_8,
693       MVE_VLD20_8_wb,      MVE_VLD21_16,        MVE_VLD21_16_wb,
694       MVE_VLD21_32,        MVE_VLD21_32_wb,     MVE_VLD21_8,
695       MVE_VLD21_8_wb,      MVE_VLD40_16,        MVE_VLD40_16_wb,
696       MVE_VLD40_32,        MVE_VLD40_32_wb,     MVE_VLD40_8,
697       MVE_VLD40_8_wb,      MVE_VLD41_16,        MVE_VLD41_16_wb,
698       MVE_VLD41_32,        MVE_VLD41_32_wb,     MVE_VLD41_8,
699       MVE_VLD41_8_wb,      MVE_VLD42_16,        MVE_VLD42_16_wb,
700       MVE_VLD42_32,        MVE_VLD42_32_wb,     MVE_VLD42_8,
701       MVE_VLD42_8_wb,      MVE_VLD43_16,        MVE_VLD43_16_wb,
702       MVE_VLD43_32,        MVE_VLD43_32_wb,     MVE_VLD43_8,
703       MVE_VLD43_8_wb,      MVE_VSTRB16,         MVE_VSTRB16_post,
704       MVE_VSTRB16_pre,     MVE_VSTRB16_rq,      MVE_VSTRB32,
705       MVE_VSTRB32_post,    MVE_VSTRB32_pre,     MVE_VSTRB32_rq,
706       MVE_VSTRB8_rq,       MVE_VSTRBU8,         MVE_VSTRBU8_post,
707       MVE_VSTRBU8_pre,     MVE_VSTRD64_qi,      MVE_VSTRD64_qi_pre,
708       MVE_VSTRD64_rq,      MVE_VSTRD64_rq_u,    MVE_VSTRH16_rq,
709       MVE_VSTRH16_rq_u,    MVE_VSTRH32,         MVE_VSTRH32_post,
710       MVE_VSTRH32_pre,     MVE_VSTRH32_rq,      MVE_VSTRH32_rq_u,
711       MVE_VSTRHU16,        MVE_VSTRHU16_post,   MVE_VSTRHU16_pre,
712       MVE_VSTRW32_qi,      MVE_VSTRW32_qi_pre,  MVE_VSTRW32_rq,
713       MVE_VSTRW32_rq_u,    MVE_VSTRWU32,        MVE_VSTRWU32_post,
714       MVE_VSTRWU32_pre,    MVE_VST20_16,        MVE_VST20_16_wb,
715       MVE_VST20_32,        MVE_VST20_32_wb,     MVE_VST20_8,
716       MVE_VST20_8_wb,      MVE_VST21_16,        MVE_VST21_16_wb,
717       MVE_VST21_32,        MVE_VST21_32_wb,     MVE_VST21_8,
718       MVE_VST21_8_wb,      MVE_VST40_16,        MVE_VST40_16_wb,
719       MVE_VST40_32,        MVE_VST40_32_wb,     MVE_VST40_8,
720       MVE_VST40_8_wb,      MVE_VST41_16,        MVE_VST41_16_wb,
721       MVE_VST41_32,        MVE_VST41_32_wb,     MVE_VST41_8,
722       MVE_VST41_8_wb,      MVE_VST42_16,        MVE_VST42_16_wb,
723       MVE_VST42_32,        MVE_VST42_32_wb,     MVE_VST42_8,
724       MVE_VST42_8_wb,      MVE_VST43_16,        MVE_VST43_16_wb,
725       MVE_VST43_32,        MVE_VST43_32_wb,     MVE_VST43_8,
726       MVE_VST43_8_wb,
727   };
728 
729   LLVMInitializeARMTargetInfo();
730   LLVMInitializeARMTarget();
731   LLVMInitializeARMTargetMC();
732 
733   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
734   std::string Error;
735   const Target *T = TargetRegistry::lookupTarget(TT, Error);
736   if (!T) {
737     dbgs() << Error;
738     return;
739   }
740 
741   TargetOptions Options;
742   auto TM = std::unique_ptr<LLVMTargetMachine>(
743       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
744           TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
745   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
746                   std::string(TM->getTargetFeatureString()),
747                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
748   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
749   auto MII = TM->getMCInstrInfo();
750 
751   for (unsigned Op : Opcodes) {
752     const MCInstrDesc &Desc = TII->get(Op);
753     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
754         << MII->getName(Op) << " has unexpected side effects";
755   }
756 }
757