1 //===- MachineOperandTest.cpp ---------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/ADT/ilist_node.h"
11 #include "llvm/CodeGen/MachineOperand.h"
12 #include "llvm/IR/Constants.h"
13 #include "llvm/IR/LLVMContext.h"
14 #include "llvm/IR/ModuleSlotTracker.h"
15 #include "llvm/Support/raw_ostream.h"
16 #include "gtest/gtest.h"
17 
18 using namespace llvm;
19 
20 namespace {
21 
22 TEST(MachineOperandTest, ChangeToTargetIndexTest) {
23   // Creating a MachineOperand to change it to TargetIndex
24   MachineOperand MO = MachineOperand::CreateImm(50);
25 
26   // Checking some precondition on the newly created
27   // MachineOperand.
28   ASSERT_TRUE(MO.isImm());
29   ASSERT_TRUE(MO.getImm() == 50);
30   ASSERT_FALSE(MO.isTargetIndex());
31 
32   // Changing to TargetIndex with some arbitrary values
33   // for index, offset and flags.
34   MO.ChangeToTargetIndex(74, 57, 12);
35 
36   // Checking that the mutation to TargetIndex happened
37   // correctly.
38   ASSERT_TRUE(MO.isTargetIndex());
39   ASSERT_TRUE(MO.getIndex() == 74);
40   ASSERT_TRUE(MO.getOffset() == 57);
41   ASSERT_TRUE(MO.getTargetFlags() == 12);
42 }
43 
44 TEST(MachineOperandTest, PrintRegisterMask) {
45   uint32_t Dummy;
46   MachineOperand MO = MachineOperand::CreateRegMask(&Dummy);
47 
48   // Checking some preconditions on the newly created
49   // MachineOperand.
50   ASSERT_TRUE(MO.isRegMask());
51   ASSERT_TRUE(MO.getRegMask() == &Dummy);
52 
53   // Print a MachineOperand containing a RegMask. Here we check that without a
54   // TRI and IntrinsicInfo we still print a less detailed regmask.
55   std::string str;
56   raw_string_ostream OS(str);
57   MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
58   ASSERT_TRUE(OS.str() == "<regmask ...>");
59 }
60 
61 TEST(MachineOperandTest, PrintSubReg) {
62   // Create a MachineOperand with RegNum=1 and SubReg=5.
63   MachineOperand MO = MachineOperand::CreateReg(
64       /*Reg=*/1, /*isDef=*/false, /*isImp=*/false, /*isKill=*/false,
65       /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/false,
66       /*SubReg=*/5, /*isDebug=*/false, /*isInternalRead=*/false);
67 
68   // Checking some preconditions on the newly created
69   // MachineOperand.
70   ASSERT_TRUE(MO.isReg());
71   ASSERT_TRUE(MO.getReg() == 1);
72   ASSERT_TRUE(MO.getSubReg() == 5);
73 
74   // Print a MachineOperand containing a SubReg. Here we check that without a
75   // TRI and IntrinsicInfo we can still print the subreg index.
76   std::string str;
77   raw_string_ostream OS(str);
78   MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
79   ASSERT_TRUE(OS.str() == "%physreg1.subreg5");
80 }
81 
82 TEST(MachineOperandTest, PrintCImm) {
83   LLVMContext Context;
84   APInt Int(128, UINT64_MAX);
85   ++Int;
86   ConstantInt *CImm = ConstantInt::get(Context, Int);
87   // Create a MachineOperand with an Imm=(UINT64_MAX + 1)
88   MachineOperand MO = MachineOperand::CreateCImm(CImm);
89 
90   // Checking some preconditions on the newly created
91   // MachineOperand.
92   ASSERT_TRUE(MO.isCImm());
93   ASSERT_TRUE(MO.getCImm() == CImm);
94   ASSERT_TRUE(MO.getCImm()->getValue() == Int);
95 
96   // Print a MachineOperand containing a SubReg. Here we check that without a
97   // TRI and IntrinsicInfo we can still print the subreg index.
98   std::string str;
99   raw_string_ostream OS(str);
100   MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
101   ASSERT_TRUE(OS.str() == "i128 18446744073709551616");
102 }
103 
104 TEST(MachineOperandTest, PrintSubRegIndex) {
105   // Create a MachineOperand with an immediate and print it as a subreg index.
106   MachineOperand MO = MachineOperand::CreateImm(3);
107 
108   // Checking some preconditions on the newly created
109   // MachineOperand.
110   ASSERT_TRUE(MO.isImm());
111   ASSERT_TRUE(MO.getImm() == 3);
112 
113   // Print a MachineOperand containing a SubRegIdx. Here we check that without a
114   // TRI and IntrinsicInfo we can print the operand as a subreg index.
115   std::string str;
116   raw_string_ostream OS(str);
117   ModuleSlotTracker DummyMST(nullptr);
118   MachineOperand::printSubregIdx(OS, MO.getImm(), nullptr);
119   ASSERT_TRUE(OS.str() == "%subreg.3");
120 }
121 
122 } // end namespace
123