1 //===- MachineInstrTest.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/CodeGen/MachineBasicBlock.h"
10 #include "llvm/CodeGen/MachineInstr.h"
11 #include "llvm/CodeGen/MachineFunction.h"
12 #include "llvm/CodeGen/MachineMemOperand.h"
13 #include "llvm/CodeGen/MachineModuleInfo.h"
14 #include "llvm/CodeGen/TargetFrameLowering.h"
15 #include "llvm/CodeGen/TargetInstrInfo.h"
16 #include "llvm/CodeGen/TargetLowering.h"
17 #include "llvm/CodeGen/TargetSubtargetInfo.h"
18 #include "llvm/IR/DebugInfoMetadata.h"
19 #include "llvm/IR/ModuleSlotTracker.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Support/TargetSelect.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "gtest/gtest.h"
27 
28 using namespace llvm;
29 
30 namespace {
31 // Add a few Bogus backend classes so we can create MachineInstrs without
32 // depending on a real target.
33 class BogusTargetLowering : public TargetLowering {
34 public:
35   BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
36 };
37 
38 class BogusFrameLowering : public TargetFrameLowering {
39 public:
40   BogusFrameLowering()
41       : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 4) {}
42 
43   void emitPrologue(MachineFunction &MF,
44                     MachineBasicBlock &MBB) const override {}
45   void emitEpilogue(MachineFunction &MF,
46                     MachineBasicBlock &MBB) const override {}
47   bool hasFP(const MachineFunction &MF) const override { return false; }
48 };
49 
50 static TargetRegisterClass *const BogusRegisterClasses[] = {nullptr};
51 
52 class BogusRegisterInfo : public TargetRegisterInfo {
53 public:
54   BogusRegisterInfo()
55       : TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses,
56                            nullptr, nullptr, LaneBitmask(~0u), nullptr) {
57     InitMCRegisterInfo(nullptr, 0, 0, 0, nullptr, 0, nullptr, 0, nullptr,
58                        nullptr, nullptr, nullptr, nullptr, 0, nullptr, nullptr);
59   }
60 
61   const MCPhysReg *
62   getCalleeSavedRegs(const MachineFunction *MF) const override {
63     return nullptr;
64   }
65   ArrayRef<const uint32_t *> getRegMasks() const override { return None; }
66   ArrayRef<const char *> getRegMaskNames() const override { return None; }
67   BitVector getReservedRegs(const MachineFunction &MF) const override {
68     return BitVector();
69   }
70   const RegClassWeight &
71   getRegClassWeight(const TargetRegisterClass *RC) const override {
72     static RegClassWeight Bogus{1, 16};
73     return Bogus;
74   }
75   unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
76   unsigned getNumRegPressureSets() const override { return 0; }
77   const char *getRegPressureSetName(unsigned Idx) const override {
78     return "bogus";
79   }
80   unsigned getRegPressureSetLimit(const MachineFunction &MF,
81                                   unsigned Idx) const override {
82     return 0;
83   }
84   const int *
85   getRegClassPressureSets(const TargetRegisterClass *RC) const override {
86     static const int Bogus[] = {0, -1};
87     return &Bogus[0];
88   }
89   const int *getRegUnitPressureSets(unsigned RegUnit) const override {
90     static const int Bogus[] = {0, -1};
91     return &Bogus[0];
92   }
93 
94   Register getFrameRegister(const MachineFunction &MF) const override {
95     return 0;
96   }
97   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
98                            unsigned FIOperandNum,
99                            RegScavenger *RS = nullptr) const override {}
100 };
101 
102 class BogusSubtarget : public TargetSubtargetInfo {
103 public:
104   BogusSubtarget(TargetMachine &TM)
105       : TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
106                             nullptr, nullptr, nullptr, nullptr),
107         FL(), TL(TM) {}
108   ~BogusSubtarget() override {}
109 
110   const TargetFrameLowering *getFrameLowering() const override { return &FL; }
111 
112   const TargetLowering *getTargetLowering() const override { return &TL; }
113 
114   const TargetInstrInfo *getInstrInfo() const override { return &TII; }
115 
116   const TargetRegisterInfo *getRegisterInfo() const override { return &TRI; }
117 
118 private:
119   BogusFrameLowering FL;
120   BogusRegisterInfo TRI;
121   BogusTargetLowering TL;
122   TargetInstrInfo TII;
123 };
124 
125 class BogusTargetMachine : public LLVMTargetMachine {
126 public:
127   BogusTargetMachine()
128       : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(),
129                           Reloc::Static, CodeModel::Small, CodeGenOpt::Default),
130         ST(*this) {}
131 
132   ~BogusTargetMachine() override {}
133 
134   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
135     return &ST;
136   }
137 
138 private:
139   BogusSubtarget ST;
140 };
141 
142 std::unique_ptr<MCContext> createMCContext(MCAsmInfo *AsmInfo) {
143   return std::make_unique<MCContext>(
144       AsmInfo, nullptr, nullptr, nullptr, nullptr, false);
145 }
146 
147 std::unique_ptr<BogusTargetMachine> createTargetMachine() {
148   return std::make_unique<BogusTargetMachine>();
149 }
150 
151 std::unique_ptr<MachineFunction> createMachineFunction() {
152   LLVMContext Ctx;
153   Module M("Module", Ctx);
154   auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
155   auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M);
156 
157   auto TM = createTargetMachine();
158   unsigned FunctionNum = 42;
159   MachineModuleInfo MMI(TM.get());
160   const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F);
161 
162   return std::make_unique<MachineFunction>(*F, *TM, STI, FunctionNum, MMI);
163 }
164 
165 // This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
166 // for various combinations of IgnoreDefs, and also that it is symmetrical.
167 TEST(IsIdenticalToTest, DifferentDefs) {
168   auto MF = createMachineFunction();
169 
170   unsigned short NumOps = 2;
171   unsigned char NumDefs = 1;
172   MCOperandInfo OpInfo[] = {
173       {0, 0, MCOI::OPERAND_REGISTER, 0},
174       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
175   MCInstrDesc MCID = {
176       0, NumOps,  NumDefs, 0,      0, 1ULL << MCID::HasOptionalDef,
177       0, nullptr, nullptr, OpInfo, 0, nullptr};
178 
179   // Create two MIs with different virtual reg defs and the same uses.
180   unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
181   unsigned VirtualDef2 = -43;
182   unsigned VirtualUse = -44;
183 
184   auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
185   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
186   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
187 
188   auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
189   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
190   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
191 
192   // Check that they are identical when we ignore virtual register defs, but not
193   // when we check defs.
194   ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
195   ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
196 
197   ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
198   ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
199 
200   // Create two MIs with different virtual reg defs, and a def or use of a
201   // sentinel register.
202   unsigned SentinelReg = 0;
203 
204   auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
205   MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
206   MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
207 
208   auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
209   MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
210   MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
211 
212   // Check that they are never identical.
213   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
214   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
215 
216   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
217   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
218 }
219 
220 // Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
221 // MachineInstrExpressionTrait::getHashValue
222 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
223   bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
224   bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
225 
226   ASSERT_EQ(IsEqual1, IsEqual2);
227 
228   auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
229   auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
230 
231   ASSERT_EQ(IsEqual1, Hash1 == Hash2);
232 }
233 
234 // This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
235 // with MachineInstrExpressionTraits::getHashValue.
236 TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
237   auto MF = createMachineFunction();
238 
239   unsigned short NumOps = 2;
240   unsigned char NumDefs = 1;
241   MCOperandInfo OpInfo[] = {
242       {0, 0, MCOI::OPERAND_REGISTER, 0},
243       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
244   MCInstrDesc MCID = {
245       0, NumOps,  NumDefs, 0,      0, 1ULL << MCID::HasOptionalDef,
246       0, nullptr, nullptr, OpInfo, 0, nullptr};
247 
248   // Define a series of instructions with different kinds of operands and make
249   // sure that the hash function is consistent with isEqual for various
250   // combinations of them.
251   unsigned VirtualDef1 = -42;
252   unsigned VirtualDef2 = -43;
253   unsigned VirtualReg = -44;
254   unsigned SentinelReg = 0;
255   unsigned PhysicalReg = 45;
256 
257   auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
258   VD1VU->addOperand(*MF,
259                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
260   VD1VU->addOperand(*MF,
261                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
262 
263   auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
264   VD2VU->addOperand(*MF,
265                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
266   VD2VU->addOperand(*MF,
267                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
268 
269   auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
270   VD1SU->addOperand(*MF,
271                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
272   VD1SU->addOperand(*MF,
273                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
274 
275   auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
276   VD1SD->addOperand(*MF,
277                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
278   VD1SD->addOperand(*MF,
279                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
280 
281   auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
282   VD2PU->addOperand(*MF,
283                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
284   VD2PU->addOperand(*MF,
285                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
286 
287   auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
288   VD2PD->addOperand(*MF,
289                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
290   VD2PD->addOperand(*MF,
291                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
292 
293   checkHashAndIsEqualMatch(VD1VU, VD2VU);
294   checkHashAndIsEqualMatch(VD1VU, VD1SU);
295   checkHashAndIsEqualMatch(VD1VU, VD1SD);
296   checkHashAndIsEqualMatch(VD1VU, VD2PU);
297   checkHashAndIsEqualMatch(VD1VU, VD2PD);
298 
299   checkHashAndIsEqualMatch(VD2VU, VD1SU);
300   checkHashAndIsEqualMatch(VD2VU, VD1SD);
301   checkHashAndIsEqualMatch(VD2VU, VD2PU);
302   checkHashAndIsEqualMatch(VD2VU, VD2PD);
303 
304   checkHashAndIsEqualMatch(VD1SU, VD1SD);
305   checkHashAndIsEqualMatch(VD1SU, VD2PU);
306   checkHashAndIsEqualMatch(VD1SU, VD2PD);
307 
308   checkHashAndIsEqualMatch(VD1SD, VD2PU);
309   checkHashAndIsEqualMatch(VD1SD, VD2PD);
310 
311   checkHashAndIsEqualMatch(VD2PU, VD2PD);
312 }
313 
314 TEST(MachineInstrPrintingTest, DebugLocPrinting) {
315   auto MF = createMachineFunction();
316 
317   MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
318   MCInstrDesc MCID = {0, 1,       1,       0,       0, 0,
319                       0, nullptr, nullptr, &OpInfo, 0, nullptr};
320 
321   LLVMContext Ctx;
322   DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
323   DISubprogram *DIS = DISubprogram::getDistinct(
324       Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
325       DISubprogram::SPFlagZero, nullptr);
326   DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
327   DebugLoc DL(DIL);
328   MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
329   MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
330 
331   std::string str;
332   raw_string_ostream OS(str);
333   MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
334             /*AddNewLine*/false);
335   ASSERT_TRUE(
336       StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
337   ASSERT_TRUE(
338       StringRef(OS.str()).endswith("filename:1:5"));
339 }
340 
341 TEST(MachineInstrSpan, DistanceBegin) {
342   auto MF = createMachineFunction();
343   auto MBB = MF->CreateMachineBasicBlock();
344 
345   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
346                       0, nullptr, nullptr, nullptr, 0, nullptr};
347 
348   auto MII = MBB->begin();
349   MachineInstrSpan MIS(MII, MBB);
350   ASSERT_TRUE(MIS.empty());
351 
352   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
353   MBB->insert(MII, MI);
354   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
355 }
356 
357 TEST(MachineInstrSpan, DistanceEnd) {
358   auto MF = createMachineFunction();
359   auto MBB = MF->CreateMachineBasicBlock();
360 
361   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
362                       0, nullptr, nullptr, nullptr, 0, nullptr};
363 
364   auto MII = MBB->end();
365   MachineInstrSpan MIS(MII, MBB);
366   ASSERT_TRUE(MIS.empty());
367 
368   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
369   MBB->insert(MII, MI);
370   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
371 }
372 
373 TEST(MachineInstrExtraInfo, AddExtraInfo) {
374   auto MF = createMachineFunction();
375   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
376                       0, nullptr, nullptr, nullptr, 0, nullptr};
377 
378   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
379   auto MAI = MCAsmInfo();
380   auto MC = createMCContext(&MAI);
381   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
382                                       MachineMemOperand::MOLoad, 8, 8);
383   SmallVector<MachineMemOperand *, 2> MMOs;
384   MMOs.push_back(MMO);
385   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
386   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
387   LLVMContext Ctx;
388   MDNode *MDN = MDNode::getDistinct(Ctx, None);
389 
390   ASSERT_TRUE(MI->memoperands_empty());
391   ASSERT_FALSE(MI->getPreInstrSymbol());
392   ASSERT_FALSE(MI->getPostInstrSymbol());
393   ASSERT_FALSE(MI->getHeapAllocMarker());
394 
395   MI->setMemRefs(*MF, MMOs);
396   ASSERT_TRUE(MI->memoperands().size() == 1);
397   ASSERT_FALSE(MI->getPreInstrSymbol());
398   ASSERT_FALSE(MI->getPostInstrSymbol());
399   ASSERT_FALSE(MI->getHeapAllocMarker());
400 
401   MI->setPreInstrSymbol(*MF, Sym1);
402   ASSERT_TRUE(MI->memoperands().size() == 1);
403   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
404   ASSERT_FALSE(MI->getPostInstrSymbol());
405   ASSERT_FALSE(MI->getHeapAllocMarker());
406 
407   MI->setPostInstrSymbol(*MF, Sym2);
408   ASSERT_TRUE(MI->memoperands().size() == 1);
409   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
410   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
411   ASSERT_FALSE(MI->getHeapAllocMarker());
412 
413   MI->setHeapAllocMarker(*MF, MDN);
414   ASSERT_TRUE(MI->memoperands().size() == 1);
415   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
416   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
417   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
418 }
419 
420 TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
421   auto MF = createMachineFunction();
422   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
423                       0, nullptr, nullptr, nullptr, 0, nullptr};
424 
425   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
426   auto MAI = MCAsmInfo();
427   auto MC = createMCContext(&MAI);
428   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
429                                       MachineMemOperand::MOLoad, 8, 8);
430   SmallVector<MachineMemOperand *, 2> MMOs;
431   MMOs.push_back(MMO);
432   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
433   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
434   LLVMContext Ctx;
435   MDNode *MDN = MDNode::getDistinct(Ctx, None);
436 
437   MI->setMemRefs(*MF, MMOs);
438   MI->setPreInstrSymbol(*MF, Sym1);
439   MI->setPostInstrSymbol(*MF, Sym2);
440   MI->setHeapAllocMarker(*MF, MDN);
441 
442   MMOs.push_back(MMO);
443 
444   MI->setMemRefs(*MF, MMOs);
445   ASSERT_TRUE(MI->memoperands().size() == 2);
446   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
447   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
448   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
449 
450   MI->setPostInstrSymbol(*MF, Sym1);
451   ASSERT_TRUE(MI->memoperands().size() == 2);
452   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
453   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1);
454   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
455 }
456 
457 TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
458   auto MF = createMachineFunction();
459   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
460                       0, nullptr, nullptr, nullptr, 0, nullptr};
461 
462   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
463   auto MAI = MCAsmInfo();
464   auto MC = createMCContext(&MAI);
465   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
466                                       MachineMemOperand::MOLoad, 8, 8);
467   SmallVector<MachineMemOperand *, 2> MMOs;
468   MMOs.push_back(MMO);
469   MMOs.push_back(MMO);
470   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
471   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
472   LLVMContext Ctx;
473   MDNode *MDN = MDNode::getDistinct(Ctx, None);
474 
475   MI->setMemRefs(*MF, MMOs);
476   MI->setPreInstrSymbol(*MF, Sym1);
477   MI->setPostInstrSymbol(*MF, Sym2);
478   MI->setHeapAllocMarker(*MF, MDN);
479 
480   MI->setPostInstrSymbol(*MF, nullptr);
481   ASSERT_TRUE(MI->memoperands().size() == 2);
482   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
483   ASSERT_FALSE(MI->getPostInstrSymbol());
484   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
485 
486   MI->setHeapAllocMarker(*MF, nullptr);
487   ASSERT_TRUE(MI->memoperands().size() == 2);
488   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
489   ASSERT_FALSE(MI->getPostInstrSymbol());
490   ASSERT_FALSE(MI->getHeapAllocMarker());
491 
492   MI->setPreInstrSymbol(*MF, nullptr);
493   ASSERT_TRUE(MI->memoperands().size() == 2);
494   ASSERT_FALSE(MI->getPreInstrSymbol());
495   ASSERT_FALSE(MI->getPostInstrSymbol());
496   ASSERT_FALSE(MI->getHeapAllocMarker());
497 
498   MI->setMemRefs(*MF, {});
499   ASSERT_TRUE(MI->memoperands_empty());
500   ASSERT_FALSE(MI->getPreInstrSymbol());
501   ASSERT_FALSE(MI->getPostInstrSymbol());
502   ASSERT_FALSE(MI->getHeapAllocMarker());
503 }
504 
505 static_assert(is_trivially_copyable<MCOperand>::value, "trivially copyable");
506 
507 } // end namespace
508