1 //===- MachineInstrTest.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/CodeGen/MachineBasicBlock.h"
10 #include "llvm/CodeGen/MachineInstr.h"
11 #include "llvm/CodeGen/MachineFunction.h"
12 #include "llvm/CodeGen/MachineMemOperand.h"
13 #include "llvm/CodeGen/MachineModuleInfo.h"
14 #include "llvm/CodeGen/TargetFrameLowering.h"
15 #include "llvm/CodeGen/TargetInstrInfo.h"
16 #include "llvm/CodeGen/TargetLowering.h"
17 #include "llvm/CodeGen/TargetSubtargetInfo.h"
18 #include "llvm/IR/DebugInfoMetadata.h"
19 #include "llvm/IR/ModuleSlotTracker.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Support/TargetSelect.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "gtest/gtest.h"
27 
28 using namespace llvm;
29 
30 namespace {
31 // Add a few Bogus backend classes so we can create MachineInstrs without
32 // depending on a real target.
33 class BogusTargetLowering : public TargetLowering {
34 public:
35   BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
36 };
37 
38 class BogusFrameLowering : public TargetFrameLowering {
39 public:
40   BogusFrameLowering()
41       : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 4) {}
42 
43   void emitPrologue(MachineFunction &MF,
44                     MachineBasicBlock &MBB) const override {}
45   void emitEpilogue(MachineFunction &MF,
46                     MachineBasicBlock &MBB) const override {}
47   bool hasFP(const MachineFunction &MF) const override { return false; }
48 };
49 
50 static TargetRegisterClass *const BogusRegisterClasses[] = {nullptr};
51 
52 class BogusRegisterInfo : public TargetRegisterInfo {
53 public:
54   BogusRegisterInfo()
55       : TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses,
56                            nullptr, nullptr, LaneBitmask(~0u), nullptr) {
57     InitMCRegisterInfo(nullptr, 0, 0, 0, nullptr, 0, nullptr, 0, nullptr,
58                        nullptr, nullptr, nullptr, nullptr, 0, nullptr, nullptr);
59   }
60 
61   const MCPhysReg *
62   getCalleeSavedRegs(const MachineFunction *MF) const override {
63     return nullptr;
64   }
65   ArrayRef<const uint32_t *> getRegMasks() const override { return None; }
66   ArrayRef<const char *> getRegMaskNames() const override { return None; }
67   BitVector getReservedRegs(const MachineFunction &MF) const override {
68     return BitVector();
69   }
70   const RegClassWeight &
71   getRegClassWeight(const TargetRegisterClass *RC) const override {
72     static RegClassWeight Bogus{1, 16};
73     return Bogus;
74   }
75   unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
76   unsigned getNumRegPressureSets() const override { return 0; }
77   const char *getRegPressureSetName(unsigned Idx) const override {
78     return "bogus";
79   }
80   unsigned getRegPressureSetLimit(const MachineFunction &MF,
81                                   unsigned Idx) const override {
82     return 0;
83   }
84   const int *
85   getRegClassPressureSets(const TargetRegisterClass *RC) const override {
86     static const int Bogus[] = {0, -1};
87     return &Bogus[0];
88   }
89   const int *getRegUnitPressureSets(unsigned RegUnit) const override {
90     static const int Bogus[] = {0, -1};
91     return &Bogus[0];
92   }
93 
94   Register getFrameRegister(const MachineFunction &MF) const override {
95     return 0;
96   }
97   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
98                            unsigned FIOperandNum,
99                            RegScavenger *RS = nullptr) const override {}
100 };
101 
102 class BogusSubtarget : public TargetSubtargetInfo {
103 public:
104   BogusSubtarget(TargetMachine &TM)
105       : TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
106                             nullptr, nullptr, nullptr, nullptr),
107         FL(), TL(TM) {}
108   ~BogusSubtarget() override {}
109 
110   const TargetFrameLowering *getFrameLowering() const override { return &FL; }
111 
112   const TargetLowering *getTargetLowering() const override { return &TL; }
113 
114   const TargetInstrInfo *getInstrInfo() const override { return &TII; }
115 
116   const TargetRegisterInfo *getRegisterInfo() const override { return &TRI; }
117 
118 private:
119   BogusFrameLowering FL;
120   BogusRegisterInfo TRI;
121   BogusTargetLowering TL;
122   TargetInstrInfo TII;
123 };
124 
125 class BogusTargetMachine : public LLVMTargetMachine {
126 public:
127   BogusTargetMachine()
128       : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(),
129                           Reloc::Static, CodeModel::Small, CodeGenOpt::Default),
130         ST(*this) {}
131 
132   ~BogusTargetMachine() override {}
133 
134   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
135     return &ST;
136   }
137 
138 private:
139   BogusSubtarget ST;
140 };
141 
142 static MCAsmInfo AsmInfo = MCAsmInfo();
143 
144 std::unique_ptr<MCContext> createMCContext() {
145   return std::make_unique<MCContext>(
146       &AsmInfo, nullptr, nullptr, nullptr, nullptr, false);
147 }
148 
149 std::unique_ptr<BogusTargetMachine> createTargetMachine() {
150   return std::make_unique<BogusTargetMachine>();
151 }
152 
153 std::unique_ptr<MachineFunction> createMachineFunction() {
154   LLVMContext Ctx;
155   Module M("Module", Ctx);
156   auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
157   auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M);
158 
159   auto TM = createTargetMachine();
160   unsigned FunctionNum = 42;
161   MachineModuleInfo MMI(TM.get());
162   const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F);
163 
164   return std::make_unique<MachineFunction>(*F, *TM, STI, FunctionNum, MMI);
165 }
166 
167 // This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
168 // for various combinations of IgnoreDefs, and also that it is symmetrical.
169 TEST(IsIdenticalToTest, DifferentDefs) {
170   auto MF = createMachineFunction();
171 
172   unsigned short NumOps = 2;
173   unsigned char NumDefs = 1;
174   MCOperandInfo OpInfo[] = {
175       {0, 0, MCOI::OPERAND_REGISTER, 0},
176       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
177   MCInstrDesc MCID = {
178       0, NumOps,  NumDefs, 0,      0, 1ULL << MCID::HasOptionalDef,
179       0, nullptr, nullptr, OpInfo, 0, nullptr};
180 
181   // Create two MIs with different virtual reg defs and the same uses.
182   unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
183   unsigned VirtualDef2 = -43;
184   unsigned VirtualUse = -44;
185 
186   auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
187   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
188   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
189 
190   auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
191   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
192   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
193 
194   // Check that they are identical when we ignore virtual register defs, but not
195   // when we check defs.
196   ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
197   ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
198 
199   ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
200   ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
201 
202   // Create two MIs with different virtual reg defs, and a def or use of a
203   // sentinel register.
204   unsigned SentinelReg = 0;
205 
206   auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
207   MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
208   MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
209 
210   auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
211   MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
212   MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
213 
214   // Check that they are never identical.
215   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
216   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
217 
218   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
219   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
220 }
221 
222 // Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
223 // MachineInstrExpressionTrait::getHashValue
224 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
225   bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
226   bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
227 
228   ASSERT_EQ(IsEqual1, IsEqual2);
229 
230   auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
231   auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
232 
233   ASSERT_EQ(IsEqual1, Hash1 == Hash2);
234 }
235 
236 // This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
237 // with MachineInstrExpressionTraits::getHashValue.
238 TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
239   auto MF = createMachineFunction();
240 
241   unsigned short NumOps = 2;
242   unsigned char NumDefs = 1;
243   MCOperandInfo OpInfo[] = {
244       {0, 0, MCOI::OPERAND_REGISTER, 0},
245       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
246   MCInstrDesc MCID = {
247       0, NumOps,  NumDefs, 0,      0, 1ULL << MCID::HasOptionalDef,
248       0, nullptr, nullptr, OpInfo, 0, nullptr};
249 
250   // Define a series of instructions with different kinds of operands and make
251   // sure that the hash function is consistent with isEqual for various
252   // combinations of them.
253   unsigned VirtualDef1 = -42;
254   unsigned VirtualDef2 = -43;
255   unsigned VirtualReg = -44;
256   unsigned SentinelReg = 0;
257   unsigned PhysicalReg = 45;
258 
259   auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
260   VD1VU->addOperand(*MF,
261                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
262   VD1VU->addOperand(*MF,
263                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
264 
265   auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
266   VD2VU->addOperand(*MF,
267                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
268   VD2VU->addOperand(*MF,
269                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
270 
271   auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
272   VD1SU->addOperand(*MF,
273                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
274   VD1SU->addOperand(*MF,
275                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
276 
277   auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
278   VD1SD->addOperand(*MF,
279                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
280   VD1SD->addOperand(*MF,
281                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
282 
283   auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
284   VD2PU->addOperand(*MF,
285                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
286   VD2PU->addOperand(*MF,
287                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
288 
289   auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
290   VD2PD->addOperand(*MF,
291                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
292   VD2PD->addOperand(*MF,
293                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
294 
295   checkHashAndIsEqualMatch(VD1VU, VD2VU);
296   checkHashAndIsEqualMatch(VD1VU, VD1SU);
297   checkHashAndIsEqualMatch(VD1VU, VD1SD);
298   checkHashAndIsEqualMatch(VD1VU, VD2PU);
299   checkHashAndIsEqualMatch(VD1VU, VD2PD);
300 
301   checkHashAndIsEqualMatch(VD2VU, VD1SU);
302   checkHashAndIsEqualMatch(VD2VU, VD1SD);
303   checkHashAndIsEqualMatch(VD2VU, VD2PU);
304   checkHashAndIsEqualMatch(VD2VU, VD2PD);
305 
306   checkHashAndIsEqualMatch(VD1SU, VD1SD);
307   checkHashAndIsEqualMatch(VD1SU, VD2PU);
308   checkHashAndIsEqualMatch(VD1SU, VD2PD);
309 
310   checkHashAndIsEqualMatch(VD1SD, VD2PU);
311   checkHashAndIsEqualMatch(VD1SD, VD2PD);
312 
313   checkHashAndIsEqualMatch(VD2PU, VD2PD);
314 }
315 
316 TEST(MachineInstrPrintingTest, DebugLocPrinting) {
317   auto MF = createMachineFunction();
318 
319   MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
320   MCInstrDesc MCID = {0, 1,       1,       0,       0, 0,
321                       0, nullptr, nullptr, &OpInfo, 0, nullptr};
322 
323   LLVMContext Ctx;
324   DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
325   DISubprogram *DIS = DISubprogram::getDistinct(
326       Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
327       DISubprogram::SPFlagZero, nullptr);
328   DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
329   DebugLoc DL(DIL);
330   MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
331   MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
332 
333   std::string str;
334   raw_string_ostream OS(str);
335   MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
336             /*AddNewLine*/false);
337   ASSERT_TRUE(
338       StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
339   ASSERT_TRUE(
340       StringRef(OS.str()).endswith("filename:1:5"));
341 }
342 
343 TEST(MachineInstrSpan, DistanceBegin) {
344   auto MF = createMachineFunction();
345   auto MBB = MF->CreateMachineBasicBlock();
346 
347   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
348                       0, nullptr, nullptr, nullptr, 0, nullptr};
349 
350   auto MII = MBB->begin();
351   MachineInstrSpan MIS(MII, MBB);
352   ASSERT_TRUE(MIS.empty());
353 
354   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
355   MBB->insert(MII, MI);
356   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
357 }
358 
359 TEST(MachineInstrSpan, DistanceEnd) {
360   auto MF = createMachineFunction();
361   auto MBB = MF->CreateMachineBasicBlock();
362 
363   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
364                       0, nullptr, nullptr, nullptr, 0, nullptr};
365 
366   auto MII = MBB->end();
367   MachineInstrSpan MIS(MII, MBB);
368   ASSERT_TRUE(MIS.empty());
369 
370   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
371   MBB->insert(MII, MI);
372   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
373 }
374 
375 TEST(MachineInstrExtraInfo, AddExtraInfo) {
376   auto MF = createMachineFunction();
377   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
378                       0, nullptr, nullptr, nullptr, 0, nullptr};
379 
380   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
381   auto MC = createMCContext();
382   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
383                                       MachineMemOperand::MOLoad, 8, 8);
384   SmallVector<MachineMemOperand *, 2> MMOs;
385   MMOs.push_back(MMO);
386   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
387   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
388   LLVMContext Ctx;
389   MDNode *MDN = MDNode::getDistinct(Ctx, None);
390 
391   ASSERT_TRUE(MI->memoperands_empty());
392   ASSERT_FALSE(MI->getPreInstrSymbol());
393   ASSERT_FALSE(MI->getPostInstrSymbol());
394   ASSERT_FALSE(MI->getHeapAllocMarker());
395 
396   MI->setMemRefs(*MF, MMOs);
397   ASSERT_TRUE(MI->memoperands().size() == 1);
398   ASSERT_FALSE(MI->getPreInstrSymbol());
399   ASSERT_FALSE(MI->getPostInstrSymbol());
400   ASSERT_FALSE(MI->getHeapAllocMarker());
401 
402   MI->setPreInstrSymbol(*MF, Sym1);
403   ASSERT_TRUE(MI->memoperands().size() == 1);
404   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
405   ASSERT_FALSE(MI->getPostInstrSymbol());
406   ASSERT_FALSE(MI->getHeapAllocMarker());
407 
408   MI->setPostInstrSymbol(*MF, Sym2);
409   ASSERT_TRUE(MI->memoperands().size() == 1);
410   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
411   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
412   ASSERT_FALSE(MI->getHeapAllocMarker());
413 
414   MI->setHeapAllocMarker(*MF, MDN);
415   ASSERT_TRUE(MI->memoperands().size() == 1);
416   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
417   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
418   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
419 }
420 
421 TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
422   auto MF = createMachineFunction();
423   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
424                       0, nullptr, nullptr, nullptr, 0, nullptr};
425 
426   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
427   auto MC = createMCContext();
428   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
429                                       MachineMemOperand::MOLoad, 8, 8);
430   SmallVector<MachineMemOperand *, 2> MMOs;
431   MMOs.push_back(MMO);
432   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
433   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
434   LLVMContext Ctx;
435   MDNode *MDN = MDNode::getDistinct(Ctx, None);
436 
437   MI->setMemRefs(*MF, MMOs);
438   MI->setPreInstrSymbol(*MF, Sym1);
439   MI->setPostInstrSymbol(*MF, Sym2);
440   MI->setHeapAllocMarker(*MF, MDN);
441 
442   MMOs.push_back(MMO);
443 
444   MI->setMemRefs(*MF, MMOs);
445   ASSERT_TRUE(MI->memoperands().size() == 2);
446   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
447   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
448   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
449 
450   MI->setPostInstrSymbol(*MF, Sym1);
451   ASSERT_TRUE(MI->memoperands().size() == 2);
452   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
453   ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1);
454   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
455 }
456 
457 TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
458   auto MF = createMachineFunction();
459   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
460                       0, nullptr, nullptr, nullptr, 0, nullptr};
461 
462   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
463   auto MC = createMCContext();
464   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
465                                       MachineMemOperand::MOLoad, 8, 8);
466   SmallVector<MachineMemOperand *, 2> MMOs;
467   MMOs.push_back(MMO);
468   MMOs.push_back(MMO);
469   MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
470   MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
471   LLVMContext Ctx;
472   MDNode *MDN = MDNode::getDistinct(Ctx, None);
473 
474   MI->setMemRefs(*MF, MMOs);
475   MI->setPreInstrSymbol(*MF, Sym1);
476   MI->setPostInstrSymbol(*MF, Sym2);
477   MI->setHeapAllocMarker(*MF, MDN);
478 
479   MI->setPostInstrSymbol(*MF, nullptr);
480   ASSERT_TRUE(MI->memoperands().size() == 2);
481   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
482   ASSERT_FALSE(MI->getPostInstrSymbol());
483   ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
484 
485   MI->setHeapAllocMarker(*MF, nullptr);
486   ASSERT_TRUE(MI->memoperands().size() == 2);
487   ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
488   ASSERT_FALSE(MI->getPostInstrSymbol());
489   ASSERT_FALSE(MI->getHeapAllocMarker());
490 
491   MI->setPreInstrSymbol(*MF, nullptr);
492   ASSERT_TRUE(MI->memoperands().size() == 2);
493   ASSERT_FALSE(MI->getPreInstrSymbol());
494   ASSERT_FALSE(MI->getPostInstrSymbol());
495   ASSERT_FALSE(MI->getHeapAllocMarker());
496 
497   MI->setMemRefs(*MF, {});
498   ASSERT_TRUE(MI->memoperands_empty());
499   ASSERT_FALSE(MI->getPreInstrSymbol());
500   ASSERT_FALSE(MI->getPostInstrSymbol());
501   ASSERT_FALSE(MI->getHeapAllocMarker());
502 }
503 
504 static_assert(is_trivially_copyable<MCOperand>::value, "trivially copyable");
505 
506 } // end namespace
507