1 //===- KnownBitsTest.cpp -------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "GISelMITest.h" 10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" 11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 12 13 TEST_F(AArch64GISelMITest, TestKnownBitsBuildVector) { 14 StringRef MIRString = R"( 15 %ptr:_(p0) = G_IMPLICIT_DEF 16 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8)) 17 %mask0:_(s8) = G_CONSTANT i8 24 18 %mask1:_(s8) = G_CONSTANT i8 224 19 %tmp0:_(s8) = G_AND %unknown, %mask0 20 %val0:_(s8) = G_OR %tmp0, %mask1 21 %mask2:_(s8) = G_CONSTANT i8 146 22 %mask3:_(s8) = G_CONSTANT i8 36 23 %tmp1:_(s8) = G_AND %unknown, %mask2 24 %val1:_(s8) = G_OR %tmp1, %mask3 25 %vector:_(<2 x s8>) = G_BUILD_VECTOR %val0, %val1 26 %copy_vector:_(<2 x s8>) = COPY %vector 27 )"; 28 29 setUp(MIRString); 30 if (!TM) 31 return; 32 33 Register CopyReg = Copies[Copies.size() - 1]; 34 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 35 Register SrcReg = FinalCopy->getOperand(1).getReg(); 36 GISelKnownBits Info(*MF); 37 KnownBits Res = Info.getKnownBits(SrcReg); 38 // BuildVector KnownBits takes common bits of all elements. 39 // 111??000 40 // common ?01?01?0 41 // = ??1????0 42 EXPECT_EQ(0x20u, Res.One.getZExtValue()); 43 EXPECT_EQ(0x01u, Res.Zero.getZExtValue()); 44 } 45 46 // Vector KnownBits track bits that are common for all vector scalar elements. 47 // For tests below KnownBits analysis is same as for scalar/pointer types, tests 48 // are mostly copied from KnownBitsTest.cpp using splat vectors and have the 49 // same result. 50 51 TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHI) { 52 StringRef MIRString = R"( 53 bb.10: 54 %10:_(s8) = G_CONSTANT i8 3 55 %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8) 56 %12:_(s1) = G_IMPLICIT_DEF 57 G_BRCOND %12(s1), %bb.11 58 G_BR %bb.12 59 60 bb.11: 61 %13:_(s8) = G_CONSTANT i8 2 62 %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8) 63 G_BR %bb.12 64 65 bb.12: 66 %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11 67 %16:_(<2 x s8>) = COPY %15 68 )"; 69 70 setUp(MIRString); 71 if (!TM) 72 return; 73 74 Register CopyReg = Copies[Copies.size() - 1]; 75 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 76 Register SrcReg = FinalCopy->getOperand(1).getReg(); 77 Register DstReg = FinalCopy->getOperand(0).getReg(); 78 GISelKnownBits Info(*MF); 79 KnownBits Res = Info.getKnownBits(SrcReg); 80 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue()); 81 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue()); 82 83 KnownBits Res2 = Info.getKnownBits(DstReg); 84 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 85 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 86 } 87 88 TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIToNonGenericReg) { 89 StringRef MIRString = R"( 90 bb.10: 91 %10:gpr32 = MOVi32imm 771 92 %11:_(s1) = G_IMPLICIT_DEF 93 G_BRCOND %11(s1), %bb.11 94 G_BR %bb.12 95 96 bb.11: 97 %12:_(s16) = G_CONSTANT i16 2 98 %13:_(<2 x s16>) = G_BUILD_VECTOR %12:_(s16), %12:_(s16) 99 G_BR %bb.12 100 101 bb.12: 102 %15:_(<2 x s16>) = PHI %10, %bb.10, %13(<2 x s16>), %bb.11 103 %16:_(<2 x s16>) = COPY %15 104 )"; 105 106 setUp(MIRString); 107 if (!TM) 108 return; 109 110 Register CopyReg = Copies[Copies.size() - 1]; 111 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 112 Register SrcReg = FinalCopy->getOperand(1).getReg(); 113 Register DstReg = FinalCopy->getOperand(0).getReg(); 114 GISelKnownBits Info(*MF); 115 KnownBits Res = Info.getKnownBits(SrcReg); 116 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 117 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 118 119 KnownBits Res2 = Info.getKnownBits(DstReg); 120 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 121 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 122 } 123 124 TEST_F(AArch64GISelMITest, TestKnownBitsVectorUnknownPHI) { 125 StringRef MIRString = R"( 126 bb.10: 127 %10:_(<2 x s32>) = G_BITCAST %0 128 %11:_(s1) = G_IMPLICIT_DEF 129 G_BRCOND %11(s1), %bb.11 130 G_BR %bb.12 131 132 bb.11: 133 %12:_(s32) = G_CONSTANT i32 2 134 %13:_(<2 x s32>) = G_BUILD_VECTOR %12:_(s32), %12:_(s32) 135 G_BR %bb.12 136 137 bb.12: 138 %14:_(<2 x s32>) = PHI %10(<2 x s32>), %bb.10, %13(<2 x s32>), %bb.11 139 %15:_(<2 x s32>) = COPY %14 140 )"; 141 142 setUp(MIRString); 143 if (!TM) 144 return; 145 146 Register CopyReg = Copies[Copies.size() - 1]; 147 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 148 Register SrcReg = FinalCopy->getOperand(1).getReg(); 149 Register DstReg = FinalCopy->getOperand(0).getReg(); 150 GISelKnownBits Info(*MF); 151 KnownBits Res = Info.getKnownBits(SrcReg); 152 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 153 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 154 155 KnownBits Res2 = Info.getKnownBits(DstReg); 156 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 157 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 158 } 159 160 TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIWithLoop) { 161 StringRef MIRString = R"( 162 bb.10: 163 %10:_(s8) = G_CONSTANT i8 3 164 %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8) 165 %12:_(s1) = G_IMPLICIT_DEF 166 G_BRCOND %12(s1), %bb.11 167 G_BR %bb.12 168 169 bb.11: 170 %13:_(s8) = G_CONSTANT i8 2 171 %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8) 172 G_BR %bb.12 173 174 bb.12: 175 %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11, %16(<2 x s8>), %bb.12 176 %16:_(<2 x s8>) = COPY %15 177 G_BR %bb.12 178 )"; 179 180 setUp(MIRString); 181 if (!TM) 182 return; 183 184 Register CopyReg = Copies[Copies.size() - 1]; 185 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 186 Register SrcReg = FinalCopy->getOperand(1).getReg(); 187 Register DstReg = FinalCopy->getOperand(0).getReg(); 188 GISelKnownBits Info(*MF); 189 KnownBits Res = Info.getKnownBits(SrcReg); 190 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 191 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 192 193 KnownBits Res2 = Info.getKnownBits(DstReg); 194 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 195 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 196 } 197 198 TEST_F(AArch64GISelMITest, TestKnownBitsVectorDecreasingCstPHIWithLoop) { 199 StringRef MIRString = R"( 200 bb.10: 201 %10:_(s8) = G_CONSTANT i8 5 202 %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8) 203 %12:_(s8) = G_CONSTANT i8 1 204 205 bb.12: 206 %13:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.12 207 %14:_(<2 x s8>) = G_LSHR %13, %12 208 %15:_(<2 x s8>) = COPY %14 209 G_BR %bb.12 210 )"; 211 212 setUp(MIRString); 213 if (!TM) 214 return; 215 Register CopyReg = Copies[Copies.size() - 1]; 216 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 217 Register SrcReg = FinalCopy->getOperand(1).getReg(); 218 Register DstReg = FinalCopy->getOperand(0).getReg(); 219 GISelKnownBits Info(*MF, /*MaxDepth=*/24); 220 KnownBits Res = Info.getKnownBits(SrcReg); 221 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 222 EXPECT_EQ((uint64_t)0xC0, Res.Zero.getZExtValue()); 223 224 KnownBits Res2 = Info.getKnownBits(DstReg); 225 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 226 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 227 } 228 229 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAND) { 230 StringRef MIRString = R"( 231 %ptr:_(p0) = G_IMPLICIT_DEF 232 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 233 %mask0:_(s8) = G_CONSTANT i8 52 234 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 235 %mask1:_(s8) = G_CONSTANT i8 10 236 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 237 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 238 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 239 %mask2:_(s8) = G_CONSTANT i8 32 240 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 241 %mask3:_(s8) = G_CONSTANT i8 24 242 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 243 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 244 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 245 %and:_(<2 x s8>) = G_AND %val0, %val1 246 %copy_and:_(<2 x s8>) = COPY %and 247 )"; 248 249 setUp(MIRString); 250 if (!TM) 251 return; 252 253 Register CopyReg = Copies[Copies.size() - 1]; 254 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 255 Register SrcReg = FinalCopy->getOperand(1).getReg(); 256 GISelKnownBits Info(*MF); 257 KnownBits Res = Info.getKnownBits(SrcReg); 258 EXPECT_EQ(0x08u, Res.One.getZExtValue()); 259 EXPECT_EQ(0xC7u, Res.Zero.getZExtValue()); 260 } 261 262 TEST_F(AArch64GISelMITest, TestKnownBitsVectorOR) { 263 StringRef MIRString = R"( 264 %ptr:_(p0) = G_IMPLICIT_DEF 265 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 266 %mask0:_(s8) = G_CONSTANT i8 52 267 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 268 %mask1:_(s8) = G_CONSTANT i8 10 269 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 270 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 271 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 272 %mask2:_(s8) = G_CONSTANT i8 32 273 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 274 %mask3:_(s8) = G_CONSTANT i8 24 275 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 276 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 277 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 278 %or:_(<2 x s8>) = G_OR %val0, %val1 279 %copy_or:_(<2 x s8>) = COPY %or 280 )"; 281 282 setUp(MIRString); 283 if (!TM) 284 return; 285 286 Register CopyReg = Copies[Copies.size() - 1]; 287 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 288 Register SrcReg = FinalCopy->getOperand(1).getReg(); 289 GISelKnownBits Info(*MF); 290 KnownBits Res = Info.getKnownBits(SrcReg); 291 EXPECT_EQ(0x1Au, Res.One.getZExtValue()); 292 EXPECT_EQ(0xC1u, Res.Zero.getZExtValue()); 293 } 294 295 TEST_F(AArch64GISelMITest, TestKnownBitsVectorXOR) { 296 StringRef MIRString = R"( 297 %ptr:_(p0) = G_IMPLICIT_DEF 298 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 299 %mask0:_(s8) = G_CONSTANT i8 52 300 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 301 %mask1:_(s8) = G_CONSTANT i8 10 302 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 303 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 304 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 305 %mask2:_(s8) = G_CONSTANT i8 32 306 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 307 %mask3:_(s8) = G_CONSTANT i8 24 308 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 309 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 310 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 311 %xor:_(<2 x s8>) = G_XOR %val0, %val1 312 %copy_xor:_(<2 x s8>) = COPY %xor 313 )"; 314 315 setUp(MIRString); 316 if (!TM) 317 return; 318 319 Register CopyReg = Copies[Copies.size() - 1]; 320 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 321 Register SrcReg = FinalCopy->getOperand(1).getReg(); 322 GISelKnownBits Info(*MF); 323 KnownBits Res = Info.getKnownBits(SrcReg); 324 EXPECT_EQ(0x02u, Res.One.getZExtValue()); 325 EXPECT_EQ(0xC9u, Res.Zero.getZExtValue()); 326 } 327 328 TEST_F(AArch64GISelMITest, TestKnownBitsVectorXORConstant) { 329 StringRef MIRString = R"( 330 %3:_(s8) = G_CONSTANT i8 4 331 %4:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %3:_(s8) 332 %5:_(s8) = G_CONSTANT i8 7 333 %6:_(<2 x s8>) = G_BUILD_VECTOR %5:_(s8), %5:_(s8) 334 %7:_(<2 x s8>) = G_XOR %4, %6 335 %8:_(<2 x s8>) = COPY %7 336 337 %9:_(s8) = G_CONSTANT i8 12 338 %10:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %9:_(s8) 339 %11:_(<2 x s8>) = G_XOR %10, %6 340 %12:_(<2 x s8>) = COPY %11 341 )"; 342 343 setUp(MIRString); 344 if (!TM) 345 return; 346 347 GISelKnownBits Info(*MF); 348 Register CopySplatReg = Copies[Copies.size() - 2]; 349 MachineInstr *FinalSplatCopy = MRI->getVRegDef(CopySplatReg); 350 Register SrcSplatReg = FinalSplatCopy->getOperand(1).getReg(); 351 KnownBits ResNonSplat = Info.getKnownBits(SrcSplatReg); 352 EXPECT_EQ(3u, ResNonSplat.One.getZExtValue()); 353 EXPECT_EQ(252u, ResNonSplat.Zero.getZExtValue()); 354 355 Register CopyNonSplatReg = Copies[Copies.size() - 1]; 356 MachineInstr *FinalNonSplatCopy = MRI->getVRegDef(CopyNonSplatReg); 357 Register SrcNonSplatReg = FinalNonSplatCopy->getOperand(1).getReg(); 358 KnownBits ResSplat = Info.getKnownBits(SrcNonSplatReg); 359 EXPECT_EQ(3u, ResSplat.One.getZExtValue()); 360 EXPECT_EQ(244u, ResSplat.Zero.getZExtValue()); 361 } 362 363 TEST_F(AArch64GISelMITest, TestKnownBitsVectorASHR) { 364 StringRef MIRString = R"( 365 %ptr:_(p0) = G_IMPLICIT_DEF 366 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 367 %mask0:_(s8) = G_CONSTANT i8 38 368 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 369 %mask1:_(s8) = G_CONSTANT i8 202 370 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 371 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 372 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 373 %cst0:_(s8) = G_CONSTANT i8 2 374 %cst0_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst0, %cst0 375 %ashr0:_(<2 x s8>) = G_ASHR %val0, %cst0_splat 376 %copy_ashr0:_(<2 x s8>) = COPY %ashr0 377 378 %mask2:_(s8) = G_CONSTANT i8 204 379 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 380 %mask3:_(s8) = G_CONSTANT i8 18 381 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 382 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 383 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 384 %ashr1:_(<2 x s8>) = G_ASHR %val1, %cst0_splat 385 %copy_ashr1:_(<2 x s8>) = COPY %ashr1 386 )"; 387 388 setUp(MIRString); 389 if (!TM) 390 return; 391 392 Register CopyReg0 = Copies[Copies.size() - 2]; 393 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0); 394 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); 395 GISelKnownBits Info(*MF); 396 KnownBits Res0 = Info.getKnownBits(SrcReg0); 397 EXPECT_EQ(0xF2u, Res0.One.getZExtValue()); 398 EXPECT_EQ(0x04u, Res0.Zero.getZExtValue()); 399 400 Register CopyReg1 = Copies[Copies.size() - 1]; 401 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1); 402 Register SrcReg1 = FinalCopy1->getOperand(1).getReg(); 403 KnownBits Res1 = Info.getKnownBits(SrcReg1); 404 EXPECT_EQ(0x04u, Res1.One.getZExtValue()); 405 EXPECT_EQ(0x08u, Res1.Zero.getZExtValue()); 406 } 407 408 TEST_F(AArch64GISelMITest, TestKnownBitsVectorLSHR) { 409 StringRef MIRString = R"( 410 %ptr:_(p0) = G_IMPLICIT_DEF 411 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 412 %mask0:_(s8) = G_CONSTANT i8 38 413 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 414 %mask1:_(s8) = G_CONSTANT i8 202 415 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 416 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 417 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 418 %cst0:_(s8) = G_CONSTANT i8 2 419 %cst0_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst0, %cst0 420 %lshr0:_(<2 x s8>) = G_LSHR %val0, %cst0_splat 421 %copy_lshr0:_(<2 x s8>) = COPY %lshr0 422 423 %mask2:_(s8) = G_CONSTANT i8 204 424 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 425 %mask3:_(s8) = G_CONSTANT i8 18 426 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 427 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 428 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 429 %lshr1:_(<2 x s8>) = G_LSHR %val1, %cst0_splat 430 %copy_lshr1:_(<2 x s8>) = COPY %lshr1 431 )"; 432 433 setUp(MIRString); 434 if (!TM) 435 return; 436 437 Register CopyReg0 = Copies[Copies.size() - 2]; 438 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0); 439 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); 440 GISelKnownBits Info(*MF); 441 KnownBits Res0 = Info.getKnownBits(SrcReg0); 442 EXPECT_EQ(0x32u, Res0.One.getZExtValue()); 443 EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue()); 444 445 Register CopyReg1 = Copies[Copies.size() - 1]; 446 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1); 447 Register SrcReg1 = FinalCopy1->getOperand(1).getReg(); 448 KnownBits Res1 = Info.getKnownBits(SrcReg1); 449 EXPECT_EQ(0x04u, Res1.One.getZExtValue()); 450 EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue()); 451 } 452 453 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSHL) { 454 StringRef MIRString = R"( 455 %ptr:_(p0) = G_IMPLICIT_DEF 456 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 457 %mask0:_(s8) = G_CONSTANT i8 51 458 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 459 %mask1:_(s8) = G_CONSTANT i8 72 460 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 461 %tmp:_(<2 x s8>) = G_AND %unknown, %mask0_splat 462 %val:_(<2 x s8>) = G_OR %tmp, %mask1_splat 463 %cst:_(s8) = G_CONSTANT i8 3 464 %cst_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst, %cst 465 %shl:_(<2 x s8>) = G_SHL %val, %cst_splat 466 %copy_shl:_(<2 x s8>) = COPY %shl 467 )"; 468 469 setUp(MIRString); 470 if (!TM) 471 return; 472 473 Register CopyReg = Copies[Copies.size() - 1]; 474 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 475 Register SrcReg = FinalCopy->getOperand(1).getReg(); 476 GISelKnownBits Info(*MF); 477 KnownBits Res = Info.getKnownBits(SrcReg); 478 EXPECT_EQ(0x40u, Res.One.getZExtValue()); 479 EXPECT_EQ(0x27u, Res.Zero.getZExtValue()); 480 } 481 482 TEST_F(AArch64GISelMITest, TestKnownBitsVectorADD) { 483 StringRef MIRString = R"( 484 %ptr:_(p0) = G_IMPLICIT_DEF 485 %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>)) 486 %mask0:_(s16) = G_CONSTANT i16 4642 487 %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0 488 %mask1:_(s16) = G_CONSTANT i16 9536 489 %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1 490 %tmp0:_(<2 x s16>) = G_AND %unknown, %mask0_splat 491 %val0:_(<2 x s16>) = G_OR %tmp0, %mask1_splat 492 %mask2:_(s16) = G_CONSTANT i16 4096 493 %mask2_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask2, %mask2 494 %mask3:_(s16) = G_CONSTANT i16 371 495 %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3 496 %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat 497 %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat 498 %add:_(<2 x s16>) = G_ADD %val0, %val1 499 %copy_add:_(<2 x s16>) = COPY %add 500 )"; 501 502 setUp(MIRString); 503 if (!TM) 504 return; 505 506 Register CopyReg = Copies[Copies.size() - 1]; 507 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 508 Register SrcReg = FinalCopy->getOperand(1).getReg(); 509 GISelKnownBits Info(*MF); 510 KnownBits Res = Info.getKnownBits(SrcReg); 511 EXPECT_EQ(0x0091u, Res.One.getZExtValue()); 512 EXPECT_EQ(0x8108u, Res.Zero.getZExtValue()); 513 } 514 515 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSUB) { 516 StringRef MIRString = R"( 517 %ptr:_(p0) = G_IMPLICIT_DEF 518 %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>)) 519 %mask0:_(s16) = G_CONSTANT i16 4642 520 %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0 521 %mask1:_(s16) = G_CONSTANT i16 9536 522 %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1 523 %tmp0:_(<2 x s16>) = G_AND %unknown, %mask0_splat 524 %val0:_(<2 x s16>) = G_OR %tmp0, %mask1_splat 525 %mask2:_(s16) = G_CONSTANT i16 4096 526 %mask2_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask2, %mask2 527 %mask3:_(s16) = G_CONSTANT i16 371 528 %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3 529 %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat 530 %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat 531 %sub:_(<2 x s16>) = G_SUB %val0, %val1 532 %copy_sub:_(<2 x s16>) = COPY %sub 533 )"; 534 535 setUp(MIRString); 536 if (!TM) 537 return; 538 539 Register CopyReg = Copies[Copies.size() - 1]; 540 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 541 Register SrcReg = FinalCopy->getOperand(1).getReg(); 542 GISelKnownBits Info(*MF); 543 KnownBits Res = Info.getKnownBits(SrcReg); 544 EXPECT_EQ(0x01CDu, Res.One.getZExtValue()); 545 EXPECT_EQ(0xC810u, Res.Zero.getZExtValue()); 546 } 547 548 TEST_F(AArch64GISelMITest, TestKnownBitsVectorMUL) { 549 StringRef MIRString = R"( 550 %ptr:_(p0) = G_IMPLICIT_DEF 551 %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>)) 552 %mask0:_(s16) = G_CONSTANT i16 4 553 %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0 554 %mask1:_(s16) = G_CONSTANT i16 18 555 %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1 556 %tmp:_(<2 x s16>) = G_AND %unknown, %mask0_splat 557 %val0:_(<2 x s16>) = G_OR %tmp, %mask1_splat 558 %cst:_(s16) = G_CONSTANT i16 12 559 %cst_splat:_(<2 x s16>) = G_BUILD_VECTOR %cst, %cst 560 %mul:_(<2 x s16>) = G_MUL %val0, %cst_splat 561 %copy_mul:_(<2 x s16>) = COPY %mul 562 )"; 563 564 setUp(MIRString); 565 if (!TM) 566 return; 567 568 Register CopyReg = Copies[Copies.size() - 1]; 569 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 570 Register SrcReg = FinalCopy->getOperand(1).getReg(); 571 GISelKnownBits Info(*MF); 572 KnownBits Res = Info.getKnownBits(SrcReg); 573 EXPECT_EQ(0x0008u, Res.One.getZExtValue()); 574 EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue()); 575 } 576 577 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSelect) { 578 StringRef MIRString = R"( 579 %ptr:_(p0) = G_IMPLICIT_DEF 580 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 581 %mask0:_(s8) = G_CONSTANT i8 24 582 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 583 %mask1:_(s8) = G_CONSTANT i8 224 584 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 585 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 586 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 587 %mask2:_(s8) = G_CONSTANT i8 146 588 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 589 %mask3:_(s8) = G_CONSTANT i8 36 590 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 591 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 592 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 593 %cond:_(s1) = G_CONSTANT i1 false 594 %cond_splat:_(<2 x s1>) = G_BUILD_VECTOR %cond, %cond 595 %select:_(<2 x s8>) = G_SELECT %cond_splat, %val0, %val1 596 %copy_select:_(<2 x s8>) = COPY %select 597 )"; 598 599 setUp(MIRString); 600 if (!TM) 601 return; 602 603 Register CopyReg = Copies[Copies.size() - 1]; 604 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 605 Register SrcReg = FinalCopy->getOperand(1).getReg(); 606 GISelKnownBits Info(*MF); 607 KnownBits Res = Info.getKnownBits(SrcReg); 608 EXPECT_EQ(0x20u, Res.One.getZExtValue()); 609 EXPECT_EQ(0x01u, Res.Zero.getZExtValue()); 610 } 611 612 TEST_F(AArch64GISelMITest, TestVectorSignBitIsZero) { 613 setUp(); 614 if (!TM) 615 return; 616 617 const LLT V2S32 = LLT::fixed_vector(2, 32); 618 // Vector buildConstant makes splat G_BUILD_VECTOR instruction. 619 auto SignBit = B.buildConstant(V2S32, 0x80000000); 620 auto Zero = B.buildConstant(V2S32, 0); 621 622 const LLT S32 = LLT::scalar(32); 623 auto NonSplat = 624 B.buildBuildVector(V2S32, {B.buildConstant(S32, 1).getReg(0), 625 B.buildConstant(S32, 2).getReg(0)}); 626 auto NonSplat2 = 627 B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0), 628 B.buildConstant(S32, 0x80000004).getReg(0)}); 629 // signBitIsZero is true for elt 0 and false for elt 1 GISelKnownBits takes 630 // common bits so this is false. 631 auto NonSplat3 = 632 B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0), 633 B.buildConstant(S32, 0x8).getReg(0)}); 634 GISelKnownBits KnownBits(*MF); 635 636 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0))); 637 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0))); 638 EXPECT_TRUE(KnownBits.signBitIsZero(NonSplat.getReg(0))); 639 EXPECT_FALSE(KnownBits.signBitIsZero(NonSplat2.getReg(0))); 640 EXPECT_FALSE(KnownBits.signBitIsZero(NonSplat3.getReg(0))); 641 } 642 643 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsConstant) { 644 StringRef MIRString = R"( 645 %3:_(s8) = G_CONSTANT i8 1 646 %4:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %3:_(s8) 647 %5:_(<2 x s8>) = COPY %4 648 649 %6:_(s8) = G_CONSTANT i8 -1 650 %7:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %6:_(s8) 651 %8:_(<2 x s8>) = COPY %7 652 653 %9:_(s8) = G_CONSTANT i8 127 654 %10:_(<2 x s8>) = G_BUILD_VECTOR %9:_(s8), %9:_(s8) 655 %11:_(<2 x s8>) = COPY %10 656 657 %12:_(s8) = G_CONSTANT i8 32 658 %13:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %12:_(s8) 659 %14:_(<2 x s8>) = COPY %13 660 661 %15:_(s8) = G_CONSTANT i8 -32 662 %16:_(<2 x s8>) = G_BUILD_VECTOR %15:_(s8), %15:_(s8) 663 %17:_(<2 x s8>) = COPY %16 664 665 %18:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %15:_(s8) 666 %19:_(<2 x s8>) = COPY %18 667 668 %20:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %15:_(s8) 669 %21:_(<2 x s8>) = COPY %20 670 )"; 671 672 setUp(MIRString); 673 if (!TM) 674 return; 675 676 Register CopyReg1 = Copies[Copies.size() - 7]; 677 Register CopyRegNeg1 = Copies[Copies.size() - 6]; 678 Register CopyReg127 = Copies[Copies.size() - 5]; 679 Register CopyReg32 = Copies[Copies.size() - 4]; 680 Register CopyRegNeg32 = Copies[Copies.size() - 3]; 681 Register NonSplatSameSign = Copies[Copies.size() - 2]; 682 Register NonSplatDifferentSign = Copies[Copies.size() - 1]; 683 684 GISelKnownBits Info(*MF); 685 // If it is known that all elts have same sign looks at common bits and 686 // effectively returns smallest NumSignBits of all the elts. Otherwise returns 687 // default value 1. 688 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1)); 689 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1)); 690 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127)); 691 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32)); 692 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32)); 693 EXPECT_EQ(3u, Info.computeNumSignBits(NonSplatSameSign)); 694 EXPECT_EQ(1u, Info.computeNumSignBits(NonSplatDifferentSign)); 695 } 696 697 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSext) { 698 StringRef MIRString = R"( 699 %3:_(p0) = G_IMPLICIT_DEF 700 %4:_(<2 x s8>) = G_LOAD %3 :: (load (<2 x s8>)) 701 %5:_(<2 x s32>) = G_SEXT %4 702 %6:_(<2 x s32>) = COPY %5 703 704 %7:_(s8) = G_CONSTANT i8 -1 705 %8:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %7:_(s8) 706 %9:_(<2 x s32>) = G_SEXT %8 707 %10:_(<2 x s32>) = COPY %9 708 709 %11:_(s8) = G_CONSTANT i8 -10 710 %12:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %11:_(s8) 711 %13:_(<2 x s32>) = G_SEXT %12 712 %14:_(<2 x s32>) = COPY %13 713 )"; 714 715 setUp(MIRString); 716 if (!TM) 717 return; 718 Register CopySextLoad = Copies[Copies.size() - 3]; 719 Register CopySextNeg1 = Copies[Copies.size() - 2]; 720 Register CopySextNonSplat = Copies[Copies.size() - 1]; 721 722 GISelKnownBits Info(*MF); 723 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad)); 724 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1)); 725 EXPECT_EQ(28u, Info.computeNumSignBits(CopySextNonSplat)); 726 } 727 728 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSextInReg) { 729 StringRef MIRString = R"( 730 %ptr:_(p0) = G_IMPLICIT_DEF 731 %load2x4:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>)) 732 733 %inreg7:_(<2 x s32>) = G_SEXT_INREG %load2x4, 7 734 %copy_inreg7:_(<2 x s32>) = COPY %inreg7 735 736 %inreg8:_(<2 x s32>) = G_SEXT_INREG %load2x4, 8 737 %copy_inreg8:_(<2 x s32>) = COPY %inreg8 738 739 %inreg9:_(<2 x s32>) = G_SEXT_INREG %load2x4, 9 740 %copy_inreg9:_(<2 x s32>) = COPY %inreg9 741 742 %inreg31:_(<2 x s32>) = G_SEXT_INREG %load2x4, 31 743 %copy_inreg31:_(<2 x s32>) = COPY %inreg31 744 745 %load2x1:_(<2 x s8>) = G_LOAD %ptr :: (load (<2 x s8>)) 746 %sext_load2x1:_(<2 x s32>) = G_SEXT %load2x1 747 748 %inreg6_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 6 749 %copy_inreg6_sext:_(<2 x s32>) = COPY %inreg6_sext 750 751 %inreg7_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 7 752 %copy_inreg7_sext:_(<2 x s32>) = COPY %inreg7_sext 753 754 %inreg8_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 8 755 %copy_inreg8_sext:_(<2 x s32>) = COPY %inreg8_sext 756 757 %inreg9_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 9 758 %copy_inreg9_sext:_(<2 x s32>) = COPY %inreg9_sext 759 760 %inreg31_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 31 761 %copy_inreg31_sext:_(<2 x s32>) = COPY %inreg31_sext 762 )"; 763 764 setUp(MIRString); 765 if (!TM) 766 return; 767 768 Register CopyInReg7 = Copies[Copies.size() - 9]; 769 Register CopyInReg8 = Copies[Copies.size() - 8]; 770 Register CopyInReg9 = Copies[Copies.size() - 7]; 771 Register CopyInReg31 = Copies[Copies.size() - 6]; 772 773 Register CopyInReg6Sext = Copies[Copies.size() - 5]; 774 Register CopyInReg7Sext = Copies[Copies.size() - 4]; 775 Register CopyInReg8Sext = Copies[Copies.size() - 3]; 776 Register CopyInReg9Sext = Copies[Copies.size() - 2]; 777 Register CopyInReg31Sext = Copies[Copies.size() - 1]; 778 779 GISelKnownBits Info(*MF); 780 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7)); 781 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8)); 782 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9)); 783 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31)); 784 785 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext)); 786 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext)); 787 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext)); 788 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext)); 789 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext)); 790 } 791 792 TEST_F(AArch64GISelMITest, TestNumSignBitsVectorAssertSext) { 793 StringRef MIRString = R"( 794 %ptr:_(p0) = G_IMPLICIT_DEF 795 %load2x4:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>)) 796 797 %assert_sext1:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 1 798 %copy_assert_sext1:_(<2 x s32>) = COPY %assert_sext1 799 800 %assert_sext7:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 7 801 %copy_assert_sext7:_(<2 x s32>) = COPY %assert_sext7 802 803 %assert_sext8:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 8 804 %copy_assert_sext8:_(<2 x s32>) = COPY %assert_sext8 805 806 %assert_sext9:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 9 807 %copy_assert_sext9:_(<2 x s32>) = COPY %assert_sext9 808 809 %assert_sext31:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 31 810 %copy_assert_sext31:_(<2 x s32>) = COPY %assert_sext31 811 812 %load2x1:_(<2 x s8>) = G_LOAD %ptr :: (load (<2 x s8>)) 813 %sext_load2x1:_(<2 x s32>) = G_SEXT %load2x1 814 815 %assert_sext6_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 6 816 %copy_assert_sext6_sext:_(<2 x s32>) = COPY %assert_sext6_sext 817 818 %assert_sext7_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 7 819 %copy_assert_sext7_sext:_(<2 x s32>) = COPY %assert_sext7_sext 820 821 %assert_sext8_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 8 822 %copy_assert_sext8_sext:_(<2 x s32>) = COPY %assert_sext8_sext 823 824 %assert_sext9_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 9 825 %copy_assert_sext9_sext:_(<2 x s32>) = COPY %assert_sext9_sext 826 827 %assert_sext31_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 31 828 %copy_assert_sext31_sext:_(<2 x s32>) = COPY %assert_sext31_sext 829 )"; 830 831 setUp(MIRString); 832 if (!TM) 833 return; 834 835 Register CopyInReg1 = Copies[Copies.size() - 10]; 836 Register CopyInReg7 = Copies[Copies.size() - 9]; 837 Register CopyInReg8 = Copies[Copies.size() - 8]; 838 Register CopyInReg9 = Copies[Copies.size() - 7]; 839 Register CopyInReg31 = Copies[Copies.size() - 6]; 840 841 Register CopyInReg6Sext = Copies[Copies.size() - 5]; 842 Register CopyInReg7Sext = Copies[Copies.size() - 4]; 843 Register CopyInReg8Sext = Copies[Copies.size() - 3]; 844 Register CopyInReg9Sext = Copies[Copies.size() - 2]; 845 Register CopyInReg31Sext = Copies[Copies.size() - 1]; 846 847 GISelKnownBits Info(*MF); 848 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1)); 849 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7)); 850 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8)); 851 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9)); 852 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31)); 853 854 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext)); 855 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext)); 856 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext)); 857 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext)); 858 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext)); 859 } 860 861 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsTrunc) { 862 StringRef MIRString = R"( 863 %3:_(p0) = G_IMPLICIT_DEF 864 %4:_(<2 x s32>) = G_LOAD %3 :: (load (<2 x s32>)) 865 %5:_(<2 x s8>) = G_TRUNC %4 866 %6:_(<2 x s8>) = COPY %5 867 868 %7:_(s32) = G_CONSTANT i32 -1 869 %8:_(<2 x s32>) = G_BUILD_VECTOR %7:_(s32), %7:_(s32) 870 %9:_(<2 x s8>) = G_TRUNC %8 871 %10:_(<2 x s8>) = COPY %9 872 873 %11:_(s32) = G_CONSTANT i32 7 874 %12:_(<2 x s32>) = G_BUILD_VECTOR %11:_(s32), %11:_(s32) 875 %13:_(<2 x s8>) = G_TRUNC %12 876 %14:_(<2 x s8>) = COPY %13 877 )"; 878 879 setUp(MIRString); 880 if (!TM) 881 return; 882 883 Register CopyTruncLoad = Copies[Copies.size() - 3]; 884 Register CopyTruncNeg1 = Copies[Copies.size() - 2]; 885 Register CopyTrunc7 = Copies[Copies.size() - 1]; 886 887 GISelKnownBits Info(*MF); 888 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad)); 889 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1)); 890 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7)); 891 } 892 893 TEST_F(AMDGPUGISelMITest, TestVectorIsKnownToBeAPowerOfTwo) { 894 895 StringRef MIRString = R"( 896 %zero:_(s32) = G_CONSTANT i32 0 897 %zero_splat:_(<2 x s32>) = G_BUILD_VECTOR %zero:_(s32), %zero:_(s32) 898 %one:_(s32) = G_CONSTANT i32 1 899 %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one:_(s32), %one:_(s32) 900 %two:_(s32) = G_CONSTANT i32 2 901 %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two:_(s32), %two:_(s32) 902 %three:_(s32) = G_CONSTANT i32 3 903 %three_splat:_(<2 x s32>) = G_BUILD_VECTOR %three:_(s32), %three:_(s32) 904 %five:_(s32) = G_CONSTANT i32 5 905 %five_splat:_(<2 x s32>) = G_BUILD_VECTOR %five:_(s32), %five:_(s32) 906 %copy_zero_splat:_(<2 x s32>) = COPY %zero_splat 907 %copy_one_splat:_(<2 x s32>) = COPY %one_splat 908 %copy_two_splat:_(<2 x s32>) = COPY %two_splat 909 %copy_three_splat:_(<2 x s32>) = COPY %three_splat 910 911 %trunc_two_splat:_(<2 x s1>) = G_TRUNC %two_splat 912 %trunc_three_splat:_(<2 x s1>) = G_TRUNC %three_splat 913 %trunc_five_splat:_(<2 x s1>) = G_TRUNC %five_splat 914 915 %copy_trunc_two_splat:_(<2 x s1>) = COPY %trunc_two_splat 916 %copy_trunc_three_splat:_(<2 x s1>) = COPY %trunc_three_splat 917 %copy_trunc_five_splat:_(<2 x s1>) = COPY %trunc_five_splat 918 919 %ptr:_(p1) = G_IMPLICIT_DEF 920 %shift_amt:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>), addrspace 1) 921 922 %shl_1:_(<2 x s32>) = G_SHL %one_splat, %shift_amt 923 %copy_shl_1:_(<2 x s32>) = COPY %shl_1 924 925 %shl_2:_(<2 x s32>) = G_SHL %two_splat, %shift_amt 926 %copy_shl_2:_(<2 x s32>) = COPY %shl_2 927 928 %not_sign_mask:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>), addrspace 1) 929 %sign_mask:_(s32) = G_CONSTANT i32 -2147483648 930 %sign_mask_splat:_(<2 x s32>) = G_BUILD_VECTOR %sign_mask:_(s32), %sign_mask:_(s32) 931 932 %lshr_not_sign_mask:_(<2 x s32>) = G_LSHR %not_sign_mask, %shift_amt 933 %copy_lshr_not_sign_mask:_(<2 x s32>) = COPY %lshr_not_sign_mask 934 935 %lshr_sign_mask:_(<2 x s32>) = G_LSHR %sign_mask_splat, %shift_amt 936 %copy_lshr_sign_mask:_(<2 x s32>) = COPY %lshr_sign_mask 937 938 %or_pow2:_(<2 x s32>) = G_OR %zero_splat, %two_splat 939 %copy_or_pow2:_(<2 x s32>) = COPY %or_pow2 940 )"; 941 942 setUp(MIRString); 943 if (!TM) 944 return; 945 946 GISelKnownBits KB(*MF); 947 948 Register CopyZero = Copies[Copies.size() - 12]; 949 Register CopyOne = Copies[Copies.size() - 11]; 950 Register CopyTwo = Copies[Copies.size() - 10]; 951 Register CopyThree = Copies[Copies.size() - 9]; 952 Register CopyTruncTwo = Copies[Copies.size() - 8]; 953 Register CopyTruncThree = Copies[Copies.size() - 7]; 954 Register CopyTruncFive = Copies[Copies.size() - 6]; 955 956 Register CopyShl1 = Copies[Copies.size() - 5]; 957 Register CopyShl2 = Copies[Copies.size() - 4]; 958 959 Register CopyLShrNotSignMask = Copies[Copies.size() - 3]; 960 Register CopyLShrSignMask = Copies[Copies.size() - 2]; 961 Register CopyOrPow2 = Copies[Copies.size() - 1]; 962 963 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &KB)); 964 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &KB)); 965 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &KB)); 966 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &KB)); 967 968 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &KB)); 969 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &KB)); 970 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &KB)); 971 // TODO: check for vector(splat) shift amount. 972 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &KB)); 973 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &KB)); 974 975 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &KB)); 976 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &KB)); 977 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &KB)); 978 } 979 980 TEST_F(AArch64GISelMITest, TestVectorMetadata) { 981 StringRef MIRString = R"( 982 %imp:_(p0) = G_IMPLICIT_DEF 983 %load:_(<2 x s8>) = G_LOAD %imp(p0) :: (load (<2 x s8>)) 984 %ext:_(<2 x s32>) = G_ZEXT %load(<2 x s8>) 985 %cst_elt:_(s32) = G_CONSTANT i32 1 986 %cst:_(<2 x s32>) = G_BUILD_VECTOR %cst_elt:_(s32), %cst_elt:_(s32) 987 %and:_(<2 x s32>) = G_AND %ext, %cst 988 %copy:_(<2 x s32>) = COPY %and(<2 x s32>) 989 )"; 990 991 setUp(MIRString); 992 if (!TM) 993 return; 994 995 Register CopyReg = Copies[Copies.size() - 1]; 996 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 997 Register SrcReg = FinalCopy->getOperand(1).getReg(); 998 999 MachineInstr *And = MRI->getVRegDef(SrcReg); 1000 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg()); 1001 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg()); 1002 IntegerType *Int8Ty = Type::getInt8Ty(Context); 1003 1004 Metadata *LowAndHigh[] = { 1005 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)), 1006 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))}; 1007 auto *NewMDNode = MDNode::get(Context, LowAndHigh); 1008 const MachineMemOperand *OldMMO = *Load->memoperands_begin(); 1009 MachineMemOperand NewMMO(OldMMO->getPointerInfo(), OldMMO->getFlags(), 1010 OldMMO->getSizeInBits(), OldMMO->getAlign(), 1011 OldMMO->getAAInfo(), NewMDNode); 1012 MachineIRBuilder MIB(*Load); 1013 MIB.buildLoad(Load->getOperand(0), Load->getOperand(1), NewMMO); 1014 Load->eraseFromParent(); 1015 1016 GISelKnownBits Info(*MF); 1017 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg()); 1018 1019 EXPECT_TRUE(Res.One.isZero()); 1020 1021 APInt Mask(Res.getBitWidth(), 1); 1022 Mask.flipAllBits(); 1023 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue()); 1024 } 1025 1026 TEST_F(AArch64GISelMITest, TestVectorKnownBitsExt) { 1027 StringRef MIRString = R"( 1028 %c1:_(s16) = G_CONSTANT i16 1 1029 %c1_splat:_(<2 x s16>) = G_BUILD_VECTOR %c1:_(s16), %c1:_(s16) 1030 %x:_(<2 x s16>) = G_IMPLICIT_DEF 1031 %y:_(<2 x s16>) = G_AND %x, %c1_splat 1032 %anyext:_(<2 x s32>) = G_ANYEXT %y(<2 x s16>) 1033 %r1:_(<2 x s32>) = COPY %anyext 1034 %zext:_(<2 x s32>) = G_ZEXT %y(<2 x s16>) 1035 %r2:_(<2 x s32>) = COPY %zext 1036 %sext:_(<2 x s32>) = G_SEXT %y(<2 x s16>) 1037 %r3:_(<2 x s32>) = COPY %sext 1038 )"; 1039 1040 setUp(MIRString); 1041 if (!TM) 1042 return; 1043 Register CopyRegAny = Copies[Copies.size() - 3]; 1044 Register CopyRegZ = Copies[Copies.size() - 2]; 1045 Register CopyRegS = Copies[Copies.size() - 1]; 1046 1047 GISelKnownBits Info(*MF); 1048 MachineInstr *Copy; 1049 Register SrcReg; 1050 KnownBits Res; 1051 1052 Copy = MRI->getVRegDef(CopyRegAny); 1053 SrcReg = Copy->getOperand(1).getReg(); 1054 Res = Info.getKnownBits(SrcReg); 1055 EXPECT_EQ((uint64_t)32, Res.getBitWidth()); 1056 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 1057 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue()); 1058 1059 Copy = MRI->getVRegDef(CopyRegZ); 1060 SrcReg = Copy->getOperand(1).getReg(); 1061 Res = Info.getKnownBits(SrcReg); 1062 EXPECT_EQ((uint64_t)32, Res.getBitWidth()); 1063 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 1064 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue()); 1065 1066 Copy = MRI->getVRegDef(CopyRegS); 1067 SrcReg = Copy->getOperand(1).getReg(); 1068 Res = Info.getKnownBits(SrcReg); 1069 EXPECT_EQ((uint64_t)32, Res.getBitWidth()); 1070 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 1071 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue()); 1072 } 1073 1074 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSextInReg) { 1075 StringRef MIRString = R"( 1076 ; 000...0001 1077 %one:_(s32) = G_CONSTANT i32 1 1078 %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one:_(s32), %one:_(s32) 1079 1080 ; 000...0010 1081 %two:_(s32) = G_CONSTANT i32 2 1082 %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two:_(s32), %two:_(s32) 1083 1084 ; 000...1010 1085 %ten:_(s32) = G_CONSTANT i32 10 1086 %ten_splat:_(<2 x s32>) = G_BUILD_VECTOR %ten:_(s32), %ten:_(s32) 1087 1088 ; ???...???? 1089 %x0:_(<2 x s32>) = COPY $x0 1090 1091 ; ???...?1? 1092 %or:_(<2 x s32>) = G_OR %x0, %two_splat 1093 1094 ; All bits are known. 1095 %inreg1:_(<2 x s32>) = G_SEXT_INREG %one_splat, 1 1096 %copy_inreg1:_(<2 x s32>) = COPY %inreg1 1097 1098 ; All bits unknown 1099 %inreg2:_(<2 x s32>) = G_SEXT_INREG %or, 1 1100 %copy_inreg2:_(<2 x s32>) = COPY %inreg2 1101 1102 ; Extending from the only (known) set bit 1103 ; 111...11? 1104 %inreg3:_(<2 x s32>) = G_SEXT_INREG %or, 2 1105 %copy_inreg3:_(<2 x s32>) = COPY %inreg3 1106 1107 ; Extending from a known set bit, overwriting all of the high set bits. 1108 ; 111...1110 1109 %inreg4:_(<2 x s32>) = G_SEXT_INREG %ten_splat, 2 1110 %copy_inreg4:_(<2 x s32>) = COPY %inreg4 1111 1112 )"; 1113 setUp(MIRString); 1114 if (!TM) 1115 return; 1116 GISelKnownBits Info(*MF); 1117 KnownBits Res; 1118 auto GetKB = [&](unsigned Idx) { 1119 Register CopyReg = Copies[Idx]; 1120 auto *Copy = MRI->getVRegDef(CopyReg); 1121 return Info.getKnownBits(Copy->getOperand(1).getReg()); 1122 }; 1123 1124 Res = GetKB(Copies.size() - 4); 1125 EXPECT_EQ(32u, Res.getBitWidth()); 1126 EXPECT_TRUE(Res.isAllOnes()); 1127 1128 Res = GetKB(Copies.size() - 3); 1129 EXPECT_EQ(32u, Res.getBitWidth()); 1130 EXPECT_TRUE(Res.isUnknown()); 1131 1132 Res = GetKB(Copies.size() - 2); 1133 EXPECT_EQ(32u, Res.getBitWidth()); 1134 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue()); 1135 EXPECT_EQ(0u, Res.Zero.getZExtValue()); 1136 1137 Res = GetKB(Copies.size() - 1); 1138 EXPECT_EQ(32u, Res.getBitWidth()); 1139 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue()); 1140 EXPECT_EQ(1u, Res.Zero.getZExtValue()); 1141 } 1142 1143 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertSext) { 1144 StringRef MIRString = R"( 1145 ; 000...0001 1146 %one:_(s32) = G_CONSTANT i32 1 1147 %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one, %one 1148 1149 ; 000...0010 1150 %two:_(s32) = G_CONSTANT i32 2 1151 %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two, %two 1152 1153 ; 000...1010 1154 %ten:_(s32) = G_CONSTANT i32 10 1155 %ten_splat:_(<2 x s32>) = G_BUILD_VECTOR %ten, %ten 1156 1157 ; ???...???? 1158 %x0:_(<2 x s32>) = COPY $x0 1159 1160 ; ???...?1? 1161 %or:_(<2 x s32>) = G_OR %x0, %two_splat 1162 1163 ; All bits are known. 1164 %assert_sext1:_(<2 x s32>) = G_ASSERT_SEXT %one_splat, 1 1165 %copy_assert_sext1:_(<2 x s32>) = COPY %assert_sext1 1166 1167 ; All bits unknown 1168 %assert_sext2:_(<2 x s32>) = G_ASSERT_SEXT %or, 1 1169 %copy_assert_sext2:_(<2 x s32>) = COPY %assert_sext2 1170 1171 ; Extending from the only (known) set bit 1172 ; 111...11? 1173 %assert_sext3:_(<2 x s32>) = G_ASSERT_SEXT %or, 2 1174 %copy_assert_sext3:_(<2 x s32>) = COPY %assert_sext3 1175 1176 ; Extending from a known set bit, overwriting all of the high set bits. 1177 ; 111...1110 1178 %assert_sext4:_(<2 x s32>) = G_ASSERT_SEXT %ten_splat, 2 1179 %copy_assert_sext4:_(<2 x s32>) = COPY %assert_sext4 1180 )"; 1181 setUp(MIRString); 1182 if (!TM) 1183 return; 1184 GISelKnownBits Info(*MF); 1185 KnownBits Res; 1186 auto GetKB = [&](unsigned Idx) { 1187 Register CopyReg = Copies[Idx]; 1188 auto *Copy = MRI->getVRegDef(CopyReg); 1189 return Info.getKnownBits(Copy->getOperand(1).getReg()); 1190 }; 1191 1192 // Every bit is known to be a 1. 1193 Res = GetKB(Copies.size() - 4); 1194 EXPECT_EQ(32u, Res.getBitWidth()); 1195 EXPECT_TRUE(Res.isAllOnes()); 1196 1197 // All bits are unknown 1198 Res = GetKB(Copies.size() - 3); 1199 EXPECT_EQ(32u, Res.getBitWidth()); 1200 EXPECT_TRUE(Res.isUnknown()); 1201 1202 // Extending from the only known set bit 1203 // 111...11? 1204 Res = GetKB(Copies.size() - 2); 1205 EXPECT_EQ(32u, Res.getBitWidth()); 1206 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue()); 1207 EXPECT_EQ(0u, Res.Zero.getZExtValue()); 1208 1209 // Extending from a known set bit, overwriting all of the high set bits. 1210 // 111...1110 1211 Res = GetKB(Copies.size() - 1); 1212 EXPECT_EQ(32u, Res.getBitWidth()); 1213 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue()); 1214 EXPECT_EQ(1u, Res.Zero.getZExtValue()); 1215 } 1216 1217 TEST_F(AArch64GISelMITest, TestVectorKnownBitsBSwapBitReverse) { 1218 StringRef MIRString = R"( 1219 %const:_(s32) = G_CONSTANT i32 287454020 1220 %const_splat:_(<2 x s32>) = G_BUILD_VECTOR %const:_(s32), %const:_(s32) 1221 %bswap:_(<2 x s32>) = G_BSWAP %const_splat 1222 %bitreverse:_(<2 x s32>) = G_BITREVERSE %const_splat 1223 %copy_bswap:_(<2 x s32>) = COPY %bswap 1224 %copy_bitreverse:_(<2 x s32>) = COPY %bitreverse 1225 )"; 1226 setUp(MIRString); 1227 if (!TM) 1228 return; 1229 1230 const uint32_t ByteSwappedVal = 0x44332211; 1231 const uint32_t BitSwappedVal = 0x22cc4488; 1232 1233 Register CopyBSwap = Copies[Copies.size() - 2]; 1234 Register CopyBitReverse = Copies[Copies.size() - 1]; 1235 1236 GISelKnownBits Info(*MF); 1237 1238 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap); 1239 EXPECT_EQ(32u, BSwapKnown.getBitWidth()); 1240 EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue()); 1241 EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue()); 1242 1243 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse); 1244 EXPECT_EQ(32u, BitReverseKnown.getBitWidth()); 1245 EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue()); 1246 EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue()); 1247 } 1248 1249 TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMAX) { 1250 StringRef MIRString = R"( 1251 %ptr:_(p0) = G_IMPLICIT_DEF 1252 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 1253 %mask0:_(s8) = G_CONSTANT i8 10 1254 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 1255 %mask1:_(s8) = G_CONSTANT i8 1 1256 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 1257 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 1258 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 1259 %mask2:_(s8) = G_CONSTANT i8 3 1260 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 1261 %mask3:_(s8) = G_CONSTANT i8 12 1262 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 1263 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 1264 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 1265 %umax0:_(<2 x s8>) = G_UMAX %val0, %val1 1266 %copy_umax0:_(<2 x s8>) = COPY %umax0 1267 1268 %mask4:_(s8) = G_CONSTANT i8 14 1269 %mask4_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask4, %mask4 1270 %mask5:_(s8) = G_CONSTANT i8 2 1271 %mask5_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask5, %mask5 1272 %tmp3:_(<2 x s8>) = G_AND %unknown, %mask4_splat 1273 %val3:_(<2 x s8>) = G_OR %tmp3, %mask5_splat 1274 %mask6:_(s8) = G_CONSTANT i8 4 1275 %mask6_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask6, %mask6 1276 %mask7:_(s8) = G_CONSTANT i8 11 1277 %mask7_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask7, %mask7 1278 %tmp4:_(<2 x s8>) = G_AND %unknown, %mask6_splat 1279 %val4:_(<2 x s8>) = G_OR %tmp4, %mask7_splat 1280 %umax1:_(<2 x s8>) = G_UMAX %val3, %val4 1281 %copy_umax1:_(<2 x s8>) = COPY %umax1 1282 )"; 1283 1284 setUp(MIRString); 1285 if (!TM) 1286 return; 1287 1288 Register CopyReg0 = Copies[Copies.size() - 2]; 1289 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0); 1290 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); 1291 GISelKnownBits Info(*MF); 1292 KnownBits Res0 = Info.getKnownBits(SrcReg0); 1293 EXPECT_EQ(0x0Cu, Res0.One.getZExtValue()); 1294 EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue()); 1295 1296 Register CopyReg1 = Copies[Copies.size() - 1]; 1297 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1); 1298 Register SrcReg1 = FinalCopy1->getOperand(1).getReg(); 1299 KnownBits Res1 = Info.getKnownBits(SrcReg1); 1300 EXPECT_EQ(0x0Au, Res1.One.getZExtValue()); 1301 EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue()); 1302 } 1303 1304 TEST_F(AArch64GISelMITest, TestVectorKnownBitsUMax) { 1305 StringRef MIRString = R"( 1306 %val:_(<2 x s32>) = COPY $x0 1307 %zext:_(<2 x s64>) = G_ZEXT %val 1308 %const:_(s64) = G_CONSTANT i64 -256 1309 %const_splat:_(<2 x s64>) = G_BUILD_VECTOR %const:_(s64), %const:_(s64) 1310 %umax:_(<2 x s64>) = G_UMAX %zext, %const_splat 1311 %copy_umax:_(<2 x s64>) = COPY %umax 1312 )"; 1313 1314 setUp(MIRString); 1315 if (!TM) 1316 return; 1317 1318 Register CopyUMax = Copies[Copies.size() - 1]; 1319 GISelKnownBits Info(*MF); 1320 1321 KnownBits KnownUmax = Info.getKnownBits(CopyUMax); 1322 EXPECT_EQ(64u, KnownUmax.getBitWidth()); 1323 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue()); 1324 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue()); 1325 1326 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue()); 1327 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue()); 1328 } 1329 1330 TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMIN) { 1331 StringRef MIRString = R"( 1332 %ptr:_(p0) = G_IMPLICIT_DEF 1333 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 1334 %mask0:_(s8) = G_CONSTANT i8 10 1335 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 1336 %mask1:_(s8) = G_CONSTANT i8 1 1337 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 1338 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 1339 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 1340 %mask2:_(s8) = G_CONSTANT i8 3 1341 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 1342 %mask3:_(s8) = G_CONSTANT i8 12 1343 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 1344 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 1345 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 1346 %umin:_(<2 x s8>) = G_UMIN %val0, %val1 1347 %copy_umin:_(<2 x s8>) = COPY %umin 1348 )"; 1349 1350 setUp(MIRString); 1351 if (!TM) 1352 return; 1353 1354 Register CopyReg0 = Copies[Copies.size() - 1]; 1355 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0); 1356 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); 1357 GISelKnownBits Info(*MF); 1358 KnownBits Res0 = Info.getKnownBits(SrcReg0); 1359 EXPECT_EQ(0x01u, Res0.One.getZExtValue()); 1360 EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue()); 1361 } 1362 1363 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMAX) { 1364 StringRef MIRString = R"( 1365 %ptr:_(p0) = G_IMPLICIT_DEF 1366 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 1367 %mask0:_(s8) = G_CONSTANT i8 128 1368 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 1369 %mask1:_(s8) = G_CONSTANT i8 64 1370 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 1371 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 1372 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 1373 %mask2:_(s8) = G_CONSTANT i8 1 1374 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 1375 %mask3:_(s8) = G_CONSTANT i8 128 1376 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 1377 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 1378 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 1379 %smax:_(<2 x s8>) = G_SMAX %val0, %val1 1380 %copy_smax:_(<2 x s8>) = COPY %smax 1381 )"; 1382 1383 setUp(MIRString); 1384 if (!TM) 1385 return; 1386 1387 Register CopyReg0 = Copies[Copies.size() - 1]; 1388 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0); 1389 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); 1390 GISelKnownBits Info(*MF); 1391 KnownBits Res0 = Info.getKnownBits(SrcReg0); 1392 EXPECT_EQ(0x40u, Res0.One.getZExtValue()); 1393 EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue()); 1394 } 1395 1396 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMIN) { 1397 StringRef MIRString = R"( 1398 %ptr:_(p0) = G_IMPLICIT_DEF 1399 %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>)) 1400 %mask0:_(s8) = G_CONSTANT i8 128 1401 %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0 1402 %mask1:_(s8) = G_CONSTANT i8 64 1403 %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1 1404 %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat 1405 %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat 1406 %mask2:_(s8) = G_CONSTANT i8 1 1407 %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2 1408 %mask3:_(s8) = G_CONSTANT i8 128 1409 %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3 1410 %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat 1411 %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat 1412 %smin:_(<2 x s8>) = G_SMIN %val0, %val1 1413 %copy_smin:_(<2 x s8>) = COPY %smin 1414 )"; 1415 1416 setUp(MIRString); 1417 if (!TM) 1418 return; 1419 1420 Register CopyReg0 = Copies[Copies.size() - 1]; 1421 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0); 1422 Register SrcReg0 = FinalCopy0->getOperand(1).getReg(); 1423 GISelKnownBits Info(*MF); 1424 KnownBits Res0 = Info.getKnownBits(SrcReg0); 1425 EXPECT_EQ(0x80u, Res0.One.getZExtValue()); 1426 EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue()); 1427 } 1428 1429 TEST_F(AArch64GISelMITest, TestVectorInvalidQueries) { 1430 StringRef MIRString = R"( 1431 %src:_(<2 x s32>) = COPY $x0 1432 %thirty2:_(s32) = G_CONSTANT i32 32 1433 %thirty2_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty2:_(s32), %thirty2:_(s32) 1434 %equalSized:_(<2 x s32>) = G_SHL %src, %thirty2_splat 1435 %copy1:_(<2 x s32>) = COPY %equalSized 1436 %thirty3:_(s32) = G_CONSTANT i32 33 1437 %thirty3_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty3:_(s32), %thirty3:_(s32) 1438 %biggerSized:_(<2 x s32>) = G_SHL %src, %thirty3_splat 1439 %copy2:_(<2 x s32>) = COPY %biggerSized 1440 )"; 1441 setUp(MIRString); 1442 if (!TM) 1443 return; 1444 1445 Register EqSizedCopyReg = Copies[Copies.size() - 2]; 1446 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg); 1447 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg(); 1448 1449 Register BiggerSizedCopyReg = Copies[Copies.size() - 1]; 1450 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg); 1451 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg(); 1452 1453 GISelKnownBits Info(*MF); 1454 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl); 1455 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl); 1456 1457 EXPECT_TRUE(EqSizeRes.One.isZero()); 1458 EXPECT_TRUE(EqSizeRes.Zero.isZero()); 1459 1460 EXPECT_TRUE(BiggerSizeRes.One.isZero()); 1461 EXPECT_TRUE(BiggerSizeRes.Zero.isZero()); 1462 } 1463 1464 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertZext) { 1465 StringRef MIRString = R"( 1466 %copy_x0:_(s64) = COPY $x0 1467 %copy_x1:_(s64) = COPY $x1 1468 %x0_x1:_(<2 x s64>) = G_BUILD_VECTOR %copy_x0, %copy_x1 1469 1470 %assert8:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 8 1471 %copy_assert8:_(<2 x s64>) = COPY %assert8 1472 1473 %assert1:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 1 1474 %copy_assert1:_(<2 x s64>) = COPY %assert1 1475 1476 %assert63:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 63 1477 %copy_assert63:_(<2 x s64>) = COPY %assert63 1478 1479 %assert3:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 3 1480 %copy_assert3:_(<2 x s64>) = COPY %assert3 1481 )"; 1482 1483 setUp(MIRString); 1484 if (!TM) 1485 return; 1486 1487 Register CopyAssert8 = Copies[Copies.size() - 4]; 1488 Register CopyAssert1 = Copies[Copies.size() - 3]; 1489 Register CopyAssert63 = Copies[Copies.size() - 2]; 1490 Register CopyAssert3 = Copies[Copies.size() - 1]; 1491 1492 GISelKnownBits Info(*MF); 1493 MachineInstr *Copy; 1494 Register SrcReg; 1495 KnownBits Res; 1496 1497 // Assert zero-extension from an 8-bit value. 1498 Copy = MRI->getVRegDef(CopyAssert8); 1499 SrcReg = Copy->getOperand(1).getReg(); 1500 Res = Info.getKnownBits(SrcReg); 1501 EXPECT_EQ(64u, Res.getBitWidth()); 1502 EXPECT_EQ(0u, Res.One.getZExtValue()); 1503 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue()); 1504 1505 // Assert zero-extension from a 1-bit value. 1506 Copy = MRI->getVRegDef(CopyAssert1); 1507 SrcReg = Copy->getOperand(1).getReg(); 1508 Res = Info.getKnownBits(SrcReg); 1509 EXPECT_EQ(64u, Res.getBitWidth()); 1510 EXPECT_EQ(0u, Res.One.getZExtValue()); 1511 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue()); 1512 1513 // Assert zero-extension from a 63-bit value. 1514 Copy = MRI->getVRegDef(CopyAssert63); 1515 SrcReg = Copy->getOperand(1).getReg(); 1516 Res = Info.getKnownBits(SrcReg); 1517 EXPECT_EQ(64u, Res.getBitWidth()); 1518 EXPECT_EQ(0u, Res.One.getZExtValue()); 1519 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue()); 1520 1521 // Assert zero-extension from a 3-bit value. 1522 Copy = MRI->getVRegDef(CopyAssert3); 1523 SrcReg = Copy->getOperand(1).getReg(); 1524 Res = Info.getKnownBits(SrcReg); 1525 EXPECT_EQ(64u, Res.getBitWidth()); 1526 EXPECT_EQ(0u, Res.One.getZExtValue()); 1527 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue()); 1528 } 1529