1 //===- KnownBitsTest.cpp -------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "GISelMITest.h" 10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" 11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 12 13 TEST_F(AArch64GISelMITest, TestKnownBitsCst) { 14 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n" 15 " %4:_(s8) = COPY %3\n"; 16 setUp(MIRString); 17 if (!TM) 18 return; 19 unsigned CopyReg = Copies[Copies.size() - 1]; 20 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 21 unsigned SrcReg = FinalCopy->getOperand(1).getReg(); 22 unsigned DstReg = FinalCopy->getOperand(0).getReg(); 23 GISelKnownBits Info(*MF); 24 KnownBits Res = Info.getKnownBits(SrcReg); 25 EXPECT_EQ((uint64_t)1, Res.One.getZExtValue()); 26 EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue()); 27 28 KnownBits Res2 = Info.getKnownBits(DstReg); 29 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 30 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 31 } 32 33 TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) { 34 StringRef MIRString = " %10:gpr32 = MOVi32imm 1\n" 35 " %4:_(s32) = COPY %10\n"; 36 setUp(MIRString); 37 if (!TM) 38 return; 39 unsigned CopyReg = Copies[Copies.size() - 1]; 40 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 41 unsigned SrcReg = FinalCopy->getOperand(1).getReg(); 42 unsigned DstReg = FinalCopy->getOperand(0).getReg(); 43 GISelKnownBits Info(*MF); 44 KnownBits Res = Info.getKnownBits(SrcReg); 45 // We can't analyze %3 due to the register class constraint. We will get a 46 // default-constructed KnownBits back. 47 EXPECT_EQ((uint64_t)1, Res.getBitWidth()); 48 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 49 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 50 51 KnownBits Res2 = Info.getKnownBits(DstReg); 52 // We still don't know the values due to the register class constraint but %4 53 // did reveal the size of %3. 54 EXPECT_EQ((uint64_t)32, Res2.getBitWidth()); 55 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 56 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 57 } 58 59 // Check that we are able to track bits through PHIs 60 // and get the intersections of everything we know on each operand. 61 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHI) { 62 StringRef MIRString = " bb.10:\n" 63 " %10:_(s8) = G_CONSTANT i8 3\n" 64 " %11:_(s1) = G_IMPLICIT_DEF\n" 65 " G_BRCOND %11(s1), %bb.11\n" 66 " G_BR %bb.12\n" 67 "\n" 68 " bb.11:\n" 69 " %12:_(s8) = G_CONSTANT i8 2\n" 70 " G_BR %bb.12\n" 71 "\n" 72 " bb.12:\n" 73 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n" 74 " %14:_(s8) = COPY %13\n"; 75 setUp(MIRString); 76 if (!TM) 77 return; 78 Register CopyReg = Copies[Copies.size() - 1]; 79 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 80 Register SrcReg = FinalCopy->getOperand(1).getReg(); 81 Register DstReg = FinalCopy->getOperand(0).getReg(); 82 GISelKnownBits Info(*MF); 83 KnownBits Res = Info.getKnownBits(SrcReg); 84 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue()); 85 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue()); 86 87 KnownBits Res2 = Info.getKnownBits(DstReg); 88 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 89 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 90 } 91 92 // Check that we report we know nothing when we hit a 93 // non-generic register. 94 // Note: this could be improved though! 95 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIToNonGenericReg) { 96 StringRef MIRString = " bb.10:\n" 97 " %10:gpr32 = MOVi32imm 3\n" 98 " %11:_(s1) = G_IMPLICIT_DEF\n" 99 " G_BRCOND %11(s1), %bb.11\n" 100 " G_BR %bb.12\n" 101 "\n" 102 " bb.11:\n" 103 " %12:_(s8) = G_CONSTANT i8 2\n" 104 " G_BR %bb.12\n" 105 "\n" 106 " bb.12:\n" 107 " %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n" 108 " %14:_(s8) = COPY %13\n"; 109 setUp(MIRString); 110 if (!TM) 111 return; 112 Register CopyReg = Copies[Copies.size() - 1]; 113 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 114 Register SrcReg = FinalCopy->getOperand(1).getReg(); 115 Register DstReg = FinalCopy->getOperand(0).getReg(); 116 GISelKnownBits Info(*MF); 117 KnownBits Res = Info.getKnownBits(SrcReg); 118 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 119 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 120 121 KnownBits Res2 = Info.getKnownBits(DstReg); 122 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 123 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 124 } 125 126 // Check that we know nothing when at least one value of a PHI 127 // comes from something we cannot analysis. 128 // This test is not particularly interesting, it is just 129 // here to cover the code that stops the analysis of PHIs 130 // earlier. In that case, we would not even look at the 131 // second incoming value. 132 TEST_F(AArch64GISelMITest, TestKnownBitsUnknownPHI) { 133 StringRef MIRString = 134 " bb.10:\n" 135 " %10:_(s64) = COPY %0\n" 136 " %11:_(s1) = G_IMPLICIT_DEF\n" 137 " G_BRCOND %11(s1), %bb.11\n" 138 " G_BR %bb.12\n" 139 "\n" 140 " bb.11:\n" 141 " %12:_(s64) = G_CONSTANT i64 2\n" 142 " G_BR %bb.12\n" 143 "\n" 144 " bb.12:\n" 145 " %13:_(s64) = PHI %10(s64), %bb.10, %12(s64), %bb.11\n" 146 " %14:_(s64) = COPY %13\n"; 147 setUp(MIRString); 148 if (!TM) 149 return; 150 Register CopyReg = Copies[Copies.size() - 1]; 151 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 152 Register SrcReg = FinalCopy->getOperand(1).getReg(); 153 Register DstReg = FinalCopy->getOperand(0).getReg(); 154 GISelKnownBits Info(*MF); 155 KnownBits Res = Info.getKnownBits(SrcReg); 156 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 157 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 158 159 KnownBits Res2 = Info.getKnownBits(DstReg); 160 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 161 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 162 } 163 164 // Check that we manage to process PHIs that loop on themselves. 165 // For now, the analysis just stops and assumes it knows nothing, 166 // eventually we could teach it how to properly track phis that 167 // loop back. 168 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIWithLoop) { 169 StringRef MIRString = 170 " bb.10:\n" 171 " %10:_(s8) = G_CONSTANT i8 3\n" 172 " %11:_(s1) = G_IMPLICIT_DEF\n" 173 " G_BRCOND %11(s1), %bb.11\n" 174 " G_BR %bb.12\n" 175 "\n" 176 " bb.11:\n" 177 " %12:_(s8) = G_CONSTANT i8 2\n" 178 " G_BR %bb.12\n" 179 "\n" 180 " bb.12:\n" 181 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11, %14(s8), %bb.12\n" 182 " %14:_(s8) = COPY %13\n" 183 " G_BR %bb.12\n"; 184 setUp(MIRString); 185 if (!TM) 186 return; 187 Register CopyReg = Copies[Copies.size() - 1]; 188 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 189 Register SrcReg = FinalCopy->getOperand(1).getReg(); 190 Register DstReg = FinalCopy->getOperand(0).getReg(); 191 GISelKnownBits Info(*MF); 192 KnownBits Res = Info.getKnownBits(SrcReg); 193 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 194 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); 195 196 KnownBits Res2 = Info.getKnownBits(DstReg); 197 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 198 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 199 } 200 201 // Check that we don't try to analysis PHIs progression. 202 // Setting a deep enough max depth would allow to effectively simulate 203 // what happens in the loop. 204 // Thus, with a deep enough depth, we could actually figure out 205 // that %14's zero known bits are actually at least what we know 206 // for %10, right shifted by one. 207 // However, this process is super expensive compile-time wise and 208 // we don't want to reach that conclusion while playing with max depth. 209 // For now, the analysis just stops and assumes it knows nothing 210 // on PHIs, but eventually we could teach it how to properly track 211 // phis that loop back without relying on the luck effect of max 212 // depth. 213 TEST_F(AArch64GISelMITest, TestKnownBitsDecreasingCstPHIWithLoop) { 214 StringRef MIRString = " bb.10:\n" 215 " %10:_(s8) = G_CONSTANT i8 5\n" 216 " %11:_(s8) = G_CONSTANT i8 1\n" 217 "\n" 218 " bb.12:\n" 219 " %13:_(s8) = PHI %10(s8), %bb.10, %14(s8), %bb.12\n" 220 " %14:_(s8) = G_LSHR %13, %11\n" 221 " %15:_(s8) = COPY %14\n" 222 " G_BR %bb.12\n"; 223 setUp(MIRString); 224 if (!TM) 225 return; 226 Register CopyReg = Copies[Copies.size() - 1]; 227 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 228 Register SrcReg = FinalCopy->getOperand(1).getReg(); 229 Register DstReg = FinalCopy->getOperand(0).getReg(); 230 GISelKnownBits Info(*MF, /*MaxDepth=*/24); 231 KnownBits Res = Info.getKnownBits(SrcReg); 232 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 233 // A single iteration on the PHI (%13) gives: 234 // %10 has known zero of 0xFA 235 // %12 has known zero of 0x80 (we shift right by one so high bit is zero) 236 // Therefore, %14's known zero are 0x80 shifted by one 0xC0. 237 // If we had simulated the loop we could have more zero bits, basically 238 // up to 0xFC (count leading zero of 5, + 1). 239 EXPECT_EQ((uint64_t)0xC0, Res.Zero.getZExtValue()); 240 241 KnownBits Res2 = Info.getKnownBits(DstReg); 242 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); 243 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); 244 } 245 246 TEST_F(AArch64GISelMITest, TestKnownBitsPtrToIntViceVersa) { 247 StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n" 248 " %4:_(p0) = G_INTTOPTR %3\n" 249 " %5:_(s32) = G_PTRTOINT %4\n" 250 " %6:_(s32) = COPY %5\n"; 251 setUp(MIRString); 252 if (!TM) 253 return; 254 unsigned CopyReg = Copies[Copies.size() - 1]; 255 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 256 unsigned SrcReg = FinalCopy->getOperand(1).getReg(); 257 GISelKnownBits Info(*MF); 258 KnownBits Res = Info.getKnownBits(SrcReg); 259 EXPECT_EQ(256u, Res.One.getZExtValue()); 260 EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue()); 261 } 262 TEST_F(AArch64GISelMITest, TestKnownBitsXOR) { 263 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 4\n" 264 " %4:_(s8) = G_CONSTANT i8 7\n" 265 " %5:_(s8) = G_XOR %3, %4\n" 266 " %6:_(s8) = COPY %5\n"; 267 setUp(MIRString); 268 if (!TM) 269 return; 270 unsigned CopyReg = Copies[Copies.size() - 1]; 271 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 272 unsigned SrcReg = FinalCopy->getOperand(1).getReg(); 273 GISelKnownBits Info(*MF); 274 KnownBits Res = Info.getKnownBits(SrcReg); 275 EXPECT_EQ(3u, Res.One.getZExtValue()); 276 EXPECT_EQ(252u, Res.Zero.getZExtValue()); 277 } 278 279 TEST_F(AArch64GISelMITest, TestKnownBits) { 280 281 StringRef MIR = " %3:_(s32) = G_TRUNC %0\n" 282 " %4:_(s32) = G_TRUNC %1\n" 283 " %5:_(s32) = G_CONSTANT i32 5\n" 284 " %6:_(s32) = G_CONSTANT i32 24\n" 285 " %7:_(s32) = G_CONSTANT i32 28\n" 286 " %14:_(p0) = G_INTTOPTR %7\n" 287 " %16:_(s32) = G_PTRTOINT %14\n" 288 " %8:_(s32) = G_SHL %3, %5\n" 289 " %9:_(s32) = G_SHL %4, %5\n" 290 " %10:_(s32) = G_OR %8, %6\n" 291 " %11:_(s32) = G_OR %9, %16\n" 292 " %12:_(s32) = G_MUL %10, %11\n" 293 " %13:_(s32) = COPY %12\n"; 294 setUp(MIR); 295 if (!TM) 296 return; 297 unsigned CopyReg = Copies[Copies.size() - 1]; 298 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 299 unsigned SrcReg = FinalCopy->getOperand(1).getReg(); 300 GISelKnownBits Info(*MF); 301 KnownBits Known = Info.getKnownBits(SrcReg); 302 EXPECT_FALSE(Known.hasConflict()); 303 EXPECT_EQ(32u, Known.One.getZExtValue()); 304 EXPECT_EQ(95u, Known.Zero.getZExtValue()); 305 APInt Zeroes = Info.getKnownZeroes(SrcReg); 306 EXPECT_EQ(Known.Zero, Zeroes); 307 } 308 309 TEST_F(AArch64GISelMITest, TestSignBitIsZero) { 310 setUp(); 311 if (!TM) 312 return; 313 314 const LLT S32 = LLT::scalar(32); 315 auto SignBit = B.buildConstant(S32, 0x80000000); 316 auto Zero = B.buildConstant(S32, 0); 317 318 GISelKnownBits KnownBits(*MF); 319 320 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0))); 321 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0))); 322 } 323 324 TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) { 325 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n" 326 " %4:_(s8) = COPY %3\n" 327 328 " %5:_(s8) = G_CONSTANT i8 -1\n" 329 " %6:_(s8) = COPY %5\n" 330 331 " %7:_(s8) = G_CONSTANT i8 127\n" 332 " %8:_(s8) = COPY %7\n" 333 334 " %9:_(s8) = G_CONSTANT i8 32\n" 335 " %10:_(s8) = COPY %9\n" 336 337 " %11:_(s8) = G_CONSTANT i8 -32\n" 338 " %12:_(s8) = COPY %11\n"; 339 setUp(MIRString); 340 if (!TM) 341 return; 342 Register CopyReg1 = Copies[Copies.size() - 5]; 343 Register CopyRegNeg1 = Copies[Copies.size() - 4]; 344 Register CopyReg127 = Copies[Copies.size() - 3]; 345 Register CopyReg32 = Copies[Copies.size() - 2]; 346 Register CopyRegNeg32 = Copies[Copies.size() - 1]; 347 348 GISelKnownBits Info(*MF); 349 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1)); 350 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1)); 351 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127)); 352 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32)); 353 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32)); 354 } 355 356 TEST_F(AArch64GISelMITest, TestNumSignBitsSext) { 357 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n" 358 " %4:_(s8) = G_LOAD %3 :: (load 1)\n" 359 " %5:_(s32) = G_SEXT %4\n" 360 " %6:_(s32) = COPY %5\n" 361 362 " %7:_(s8) = G_CONSTANT i8 -1\n" 363 " %8:_(s32) = G_SEXT %7\n" 364 " %9:_(s32) = COPY %8\n"; 365 setUp(MIRString); 366 if (!TM) 367 return; 368 Register CopySextLoad = Copies[Copies.size() - 2]; 369 Register CopySextNeg1 = Copies[Copies.size() - 1]; 370 371 GISelKnownBits Info(*MF); 372 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad)); 373 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1)); 374 } 375 376 TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) { 377 StringRef MIRString = R"( 378 %ptr:_(p0) = G_IMPLICIT_DEF 379 %load4:_(s32) = G_LOAD %ptr :: (load 4) 380 381 %inreg7:_(s32) = G_SEXT_INREG %load4, 7 382 %copy_inreg7:_(s32) = COPY %inreg7 383 384 %inreg8:_(s32) = G_SEXT_INREG %load4, 8 385 %copy_inreg8:_(s32) = COPY %inreg8 386 387 %inreg9:_(s32) = G_SEXT_INREG %load4, 9 388 %copy_inreg9:_(s32) = COPY %inreg9 389 390 %inreg31:_(s32) = G_SEXT_INREG %load4, 31 391 %copy_inreg31:_(s32) = COPY %inreg31 392 393 %load1:_(s8) = G_LOAD %ptr :: (load 1) 394 %sext_load1:_(s32) = G_SEXT %load1 395 396 %inreg6_sext:_(s32) = G_SEXT_INREG %sext_load1, 6 397 %copy_inreg6_sext:_(s32) = COPY %inreg6_sext 398 399 %inreg7_sext:_(s32) = G_SEXT_INREG %sext_load1, 7 400 %copy_inreg7_sext:_(s32) = COPY %inreg7_sext 401 402 %inreg8_sext:_(s32) = G_SEXT_INREG %sext_load1, 8 403 %copy_inreg8_sext:_(s32) = COPY %inreg8_sext 404 405 %inreg9_sext:_(s32) = G_SEXT_INREG %sext_load1, 9 406 %copy_inreg9_sext:_(s32) = COPY %inreg9_sext 407 408 %inreg31_sext:_(s32) = G_SEXT_INREG %sext_load1, 31 409 %copy_inreg31_sext:_(s32) = COPY %inreg31_sext 410 )"; 411 412 setUp(MIRString); 413 if (!TM) 414 return; 415 416 Register CopyInReg7 = Copies[Copies.size() - 9]; 417 Register CopyInReg8 = Copies[Copies.size() - 8]; 418 Register CopyInReg9 = Copies[Copies.size() - 7]; 419 Register CopyInReg31 = Copies[Copies.size() - 6]; 420 421 Register CopyInReg6Sext = Copies[Copies.size() - 5]; 422 Register CopyInReg7Sext = Copies[Copies.size() - 4]; 423 Register CopyInReg8Sext = Copies[Copies.size() - 3]; 424 Register CopyInReg9Sext = Copies[Copies.size() - 2]; 425 Register CopyInReg31Sext = Copies[Copies.size() - 1]; 426 427 GISelKnownBits Info(*MF); 428 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7)); 429 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8)); 430 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9)); 431 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31)); 432 433 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext)); 434 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext)); 435 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext)); 436 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext)); 437 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext)); 438 } 439 440 TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) { 441 StringRef MIRString = R"( 442 %ptr:_(p0) = G_IMPLICIT_DEF 443 %load4:_(s32) = G_LOAD %ptr :: (load 4) 444 445 %assert_sext1:_(s32) = G_ASSERT_SEXT %load4, 1 446 %copy_assert_sext1:_(s32) = COPY %assert_sext1 447 448 %assert_sext7:_(s32) = G_ASSERT_SEXT %load4, 7 449 %copy_assert_sext7:_(s32) = COPY %assert_sext7 450 451 %assert_sext8:_(s32) = G_ASSERT_SEXT %load4, 8 452 %copy_assert_sext8:_(s32) = COPY %assert_sext8 453 454 %assert_sext9:_(s32) = G_ASSERT_SEXT %load4, 9 455 %copy_assert_sext9:_(s32) = COPY %assert_sext9 456 457 %assert_sext31:_(s32) = G_ASSERT_SEXT %load4, 31 458 %copy_assert_sext31:_(s32) = COPY %assert_sext31 459 460 %load1:_(s8) = G_LOAD %ptr :: (load 1) 461 %sext_load1:_(s32) = G_SEXT %load1 462 463 %assert_sext6_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 6 464 %copy_assert_sext6_sext:_(s32) = COPY %assert_sext6_sext 465 466 %assert_sext7_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 7 467 %copy_assert_sext7_sext:_(s32) = COPY %assert_sext7_sext 468 469 %assert_sext8_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 8 470 %copy_assert_sext8_sext:_(s32) = COPY %assert_sext8_sext 471 472 %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9 473 %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext 474 475 %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31 476 %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext 477 )"; 478 479 setUp(MIRString); 480 if (!TM) 481 return; 482 483 Register CopyInReg1 = Copies[Copies.size() - 10]; 484 Register CopyInReg7 = Copies[Copies.size() - 9]; 485 Register CopyInReg8 = Copies[Copies.size() - 8]; 486 Register CopyInReg9 = Copies[Copies.size() - 7]; 487 Register CopyInReg31 = Copies[Copies.size() - 6]; 488 489 Register CopyInReg6Sext = Copies[Copies.size() - 5]; 490 Register CopyInReg7Sext = Copies[Copies.size() - 4]; 491 Register CopyInReg8Sext = Copies[Copies.size() - 3]; 492 Register CopyInReg9Sext = Copies[Copies.size() - 2]; 493 Register CopyInReg31Sext = Copies[Copies.size() - 1]; 494 495 GISelKnownBits Info(*MF); 496 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1)); 497 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7)); 498 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8)); 499 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9)); 500 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31)); 501 502 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext)); 503 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext)); 504 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext)); 505 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext)); 506 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext)); 507 } 508 509 TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) { 510 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n" 511 " %4:_(s32) = G_LOAD %3 :: (load 4)\n" 512 " %5:_(s8) = G_TRUNC %4\n" 513 " %6:_(s8) = COPY %5\n" 514 515 " %7:_(s32) = G_CONSTANT i32 -1\n" 516 " %8:_(s8) = G_TRUNC %7\n" 517 " %9:_(s8) = COPY %8\n" 518 519 " %10:_(s32) = G_CONSTANT i32 7\n" 520 " %11:_(s8) = G_TRUNC %10\n" 521 " %12:_(s8) = COPY %11\n"; 522 setUp(MIRString); 523 if (!TM) 524 return; 525 Register CopyTruncLoad = Copies[Copies.size() - 3]; 526 Register CopyTruncNeg1 = Copies[Copies.size() - 2]; 527 Register CopyTrunc7 = Copies[Copies.size() - 1]; 528 529 GISelKnownBits Info(*MF); 530 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad)); 531 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1)); 532 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7)); 533 } 534 535 TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) { 536 StringRef MIRString = 537 " %3:_(<4 x s32>) = G_IMPLICIT_DEF\n" 538 " %4:_(s32) = G_IMPLICIT_DEF\n" 539 " %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load 1)\n" 540 " %6:_(s32) = COPY %5\n" 541 542 " %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load 1)\n" 543 " %8:_(s32) = COPY %7\n" 544 545 " %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load 2)\n" 546 " %10:_(s32) = COPY %9\n" 547 548 " %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load 2)\n" 549 " %12:_(s32) = COPY %11\n"; 550 551 setUp(MIRString); 552 if (!TM) 553 return; 554 555 Register CopyLoadUByte = Copies[Copies.size() - 4]; 556 Register CopyLoadSByte = Copies[Copies.size() - 3]; 557 Register CopyLoadUShort = Copies[Copies.size() - 2]; 558 Register CopyLoadSShort = Copies[Copies.size() - 1]; 559 560 GISelKnownBits Info(*MF); 561 562 EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte)); 563 EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte)); 564 EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort)); 565 EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort)); 566 } 567 568 TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) { 569 StringRef MIRString = 570 " %5:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.dispatch.ptr)\n" 571 " %6:_(p4) = COPY %5\n" 572 " %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.queue.ptr)\n" 573 " %8:_(p4) = COPY %7\n" 574 " %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n" 575 " %10:_(p4) = COPY %9\n" 576 " %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n" 577 " %12:_(p4) = COPY %11\n" 578 " %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n" 579 " %14:_(p4) = COPY %13\n"; 580 581 setUp(MIRString); 582 if (!TM) 583 return; 584 585 Register CopyDispatchPtr = Copies[Copies.size() - 5]; 586 Register CopyQueuePtr = Copies[Copies.size() - 4]; 587 Register CopyKernargSegmentPtr = Copies[Copies.size() - 3]; 588 Register CopyImplicitArgPtr = Copies[Copies.size() - 2]; 589 Register CopyImplicitBufferPtr = Copies[Copies.size() - 1]; 590 591 GISelKnownBits Info(*MF); 592 593 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyDispatchPtr)); 594 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyQueuePtr)); 595 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyKernargSegmentPtr)); 596 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitArgPtr)); 597 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr)); 598 } 599 600 TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) { 601 602 StringRef MIRString = R"MIR( 603 %zero:_(s32) = G_CONSTANT i32 0 604 %one:_(s32) = G_CONSTANT i32 1 605 %two:_(s32) = G_CONSTANT i32 2 606 %three:_(s32) = G_CONSTANT i32 3 607 %five:_(s32) = G_CONSTANT i32 5 608 %copy_zero:_(s32) = COPY %zero 609 %copy_one:_(s32) = COPY %one 610 %copy_two:_(s32) = COPY %two 611 %copy_three:_(s32) = COPY %three 612 613 %trunc_two:_(s1) = G_TRUNC %two 614 %trunc_three:_(s1) = G_TRUNC %three 615 %trunc_five:_(s1) = G_TRUNC %five 616 617 %copy_trunc_two:_(s1) = COPY %trunc_two 618 %copy_trunc_three:_(s1) = COPY %trunc_three 619 %copy_trunc_five:_(s1) = COPY %trunc_five 620 621 %ptr:_(p1) = G_IMPLICIT_DEF 622 %shift_amt:_(s32) = G_LOAD %ptr :: (load 4, addrspace 1) 623 624 %shl_1:_(s32) = G_SHL %one, %shift_amt 625 %copy_shl_1:_(s32) = COPY %shl_1 626 627 %shl_2:_(s32) = G_SHL %two, %shift_amt 628 %copy_shl_2:_(s32) = COPY %shl_2 629 630 %not_sign_mask:_(s32) = G_LOAD %ptr :: (load 4, addrspace 1) 631 %sign_mask:_(s32) = G_CONSTANT i32 -2147483648 632 633 %lshr_not_sign_mask:_(s32) = G_LSHR %not_sign_mask, %shift_amt 634 %copy_lshr_not_sign_mask:_(s32) = COPY %lshr_not_sign_mask 635 636 %lshr_sign_mask:_(s32) = G_LSHR %sign_mask, %shift_amt 637 %copy_lshr_sign_mask:_(s32) = COPY %lshr_sign_mask 638 639 %or_pow2:_(s32) = G_OR %zero, %two 640 %copy_or_pow2:_(s32) = COPY %or_pow2 641 642 )MIR"; 643 setUp(MIRString); 644 if (!TM) 645 return; 646 647 GISelKnownBits KB(*MF); 648 649 Register CopyZero = Copies[Copies.size() - 12]; 650 Register CopyOne = Copies[Copies.size() - 11]; 651 Register CopyTwo = Copies[Copies.size() - 10]; 652 Register CopyThree = Copies[Copies.size() - 9]; 653 Register CopyTruncTwo = Copies[Copies.size() - 8]; 654 Register CopyTruncThree = Copies[Copies.size() - 7]; 655 Register CopyTruncFive = Copies[Copies.size() - 6]; 656 657 Register CopyShl1 = Copies[Copies.size() - 5]; 658 Register CopyShl2 = Copies[Copies.size() - 4]; 659 660 Register CopyLShrNotSignMask = Copies[Copies.size() - 3]; 661 Register CopyLShrSignMask = Copies[Copies.size() - 2]; 662 Register CopyOrPow2 = Copies[Copies.size() - 1]; 663 664 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &KB)); 665 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &KB)); 666 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &KB)); 667 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &KB)); 668 669 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &KB)); 670 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &KB)); 671 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &KB)); 672 673 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &KB)); 674 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &KB)); 675 676 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &KB)); 677 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &KB)); 678 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &KB)); 679 } 680 681 TEST_F(AArch64GISelMITest, TestMetadata) { 682 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n" 683 " %load:_(s8) = G_LOAD %imp(p0) :: (load 1)\n" 684 " %ext:_(s32) = G_ZEXT %load(s8)\n" 685 " %cst:_(s32) = G_CONSTANT i32 1\n" 686 " %and:_(s32) = G_AND %ext, %cst\n" 687 " %copy:_(s32) = COPY %and(s32)\n"; 688 setUp(MIRString); 689 if (!TM) 690 return; 691 692 Register CopyReg = Copies[Copies.size() - 1]; 693 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); 694 Register SrcReg = FinalCopy->getOperand(1).getReg(); 695 696 // We need a load with a metadata range for this to break. Fudge the load in 697 // the string and replace it with something we can work with. 698 MachineInstr *And = MRI->getVRegDef(SrcReg); 699 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg()); 700 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg()); 701 IntegerType *Int8Ty = Type::getInt8Ty(Context); 702 703 // Value must be in [0, 2) 704 Metadata *LowAndHigh[] = { 705 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)), 706 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))}; 707 auto NewMDNode = MDNode::get(Context, LowAndHigh); 708 const MachineMemOperand *OldMMO = *Load->memoperands_begin(); 709 MachineMemOperand NewMMO(OldMMO->getPointerInfo(), OldMMO->getFlags(), 710 OldMMO->getSizeInBits(), OldMMO->getAlign(), 711 OldMMO->getAAInfo(), NewMDNode); 712 MachineIRBuilder MIB(*Load); 713 MIB.buildLoad(Load->getOperand(0), Load->getOperand(1), NewMMO); 714 Load->eraseFromParent(); 715 716 GISelKnownBits Info(*MF); 717 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg()); 718 719 // We don't know what the result of the load is, so we don't know any ones. 720 EXPECT_TRUE(Res.One.isNullValue()); 721 722 // We know that the value is in [0, 2). So, we don't know if the first bit 723 // is 0 or not. However, we do know that every other bit must be 0. 724 APInt Mask(Res.getBitWidth(), 1); 725 Mask.flipAllBits(); 726 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue()); 727 } 728 729 TEST_F(AArch64GISelMITest, TestKnownBitsExt) { 730 StringRef MIRString = " %c1:_(s16) = G_CONSTANT i16 1\n" 731 " %x:_(s16) = G_IMPLICIT_DEF\n" 732 " %y:_(s16) = G_AND %x, %c1\n" 733 " %anyext:_(s32) = G_ANYEXT %y(s16)\n" 734 " %r1:_(s32) = COPY %anyext\n" 735 " %zext:_(s32) = G_ZEXT %y(s16)\n" 736 " %r2:_(s32) = COPY %zext\n" 737 " %sext:_(s32) = G_SEXT %y(s16)\n" 738 " %r3:_(s32) = COPY %sext\n"; 739 setUp(MIRString); 740 if (!TM) 741 return; 742 Register CopyRegAny = Copies[Copies.size() - 3]; 743 Register CopyRegZ = Copies[Copies.size() - 2]; 744 Register CopyRegS = Copies[Copies.size() - 1]; 745 746 GISelKnownBits Info(*MF); 747 MachineInstr *Copy; 748 Register SrcReg; 749 KnownBits Res; 750 751 Copy = MRI->getVRegDef(CopyRegAny); 752 SrcReg = Copy->getOperand(1).getReg(); 753 Res = Info.getKnownBits(SrcReg); 754 EXPECT_EQ((uint64_t)32, Res.getBitWidth()); 755 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 756 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue()); 757 758 Copy = MRI->getVRegDef(CopyRegZ); 759 SrcReg = Copy->getOperand(1).getReg(); 760 Res = Info.getKnownBits(SrcReg); 761 EXPECT_EQ((uint64_t)32, Res.getBitWidth()); 762 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 763 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue()); 764 765 Copy = MRI->getVRegDef(CopyRegS); 766 SrcReg = Copy->getOperand(1).getReg(); 767 Res = Info.getKnownBits(SrcReg); 768 EXPECT_EQ((uint64_t)32, Res.getBitWidth()); 769 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); 770 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue()); 771 } 772 773 TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) { 774 StringRef MIRString = R"( 775 ; 000...0001 776 %one:_(s32) = G_CONSTANT i32 1 777 778 ; 000...0010 779 %two:_(s32) = G_CONSTANT i32 2 780 781 ; 000...1010 782 %ten:_(s32) = G_CONSTANT i32 10 783 784 ; ???...???? 785 %w0:_(s32) = COPY $w0 786 787 ; ???...?1? 788 %or:_(s32) = G_OR %w0, %two 789 790 ; All bits are known. 791 %inreg1:_(s32) = G_SEXT_INREG %one, 1 792 %copy_inreg1:_(s32) = COPY %inreg1 793 794 ; All bits unknown 795 %inreg2:_(s32) = G_SEXT_INREG %or, 1 796 %copy_inreg2:_(s32) = COPY %inreg2 797 798 ; Extending from the only (known) set bit 799 ; 111...11? 800 %inreg3:_(s32) = G_SEXT_INREG %or, 2 801 %copy_inreg3:_(s32) = COPY %inreg3 802 803 ; Extending from a known set bit, overwriting all of the high set bits. 804 ; 111...1110 805 %inreg4:_(s32) = G_SEXT_INREG %ten, 2 806 %copy_inreg4:_(s32) = COPY %inreg4 807 808 )"; 809 setUp(MIRString); 810 if (!TM) 811 return; 812 GISelKnownBits Info(*MF); 813 KnownBits Res; 814 auto GetKB = [&](unsigned Idx) { 815 Register CopyReg = Copies[Idx]; 816 auto *Copy = MRI->getVRegDef(CopyReg); 817 return Info.getKnownBits(Copy->getOperand(1).getReg()); 818 }; 819 820 // Every bit is known to be a 1. 821 Res = GetKB(Copies.size() - 4); 822 EXPECT_EQ(32u, Res.getBitWidth()); 823 EXPECT_TRUE(Res.isAllOnes()); 824 825 // All bits are unknown 826 Res = GetKB(Copies.size() - 3); 827 EXPECT_EQ(32u, Res.getBitWidth()); 828 EXPECT_TRUE(Res.isUnknown()); 829 830 // Extending from the only known set bit 831 // 111...11? 832 Res = GetKB(Copies.size() - 2); 833 EXPECT_EQ(32u, Res.getBitWidth()); 834 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue()); 835 EXPECT_EQ(0u, Res.Zero.getZExtValue()); 836 837 // Extending from a known set bit, overwriting all of the high set bits. 838 // 111...1110 839 Res = GetKB(Copies.size() - 1); 840 EXPECT_EQ(32u, Res.getBitWidth()); 841 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue()); 842 EXPECT_EQ(1u, Res.Zero.getZExtValue()); 843 } 844 845 TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) { 846 StringRef MIRString = R"( 847 %val0:_(s16) = G_CONSTANT i16 35224 848 %val1:_(s16) = G_CONSTANT i16 17494 849 %val2:_(s16) = G_CONSTANT i16 4659 850 %val3:_(s16) = G_CONSTANT i16 43981 851 %merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val3 852 %mergecopy:_(s64) = COPY %merge 853 )"; 854 setUp(MIRString); 855 if (!TM) 856 return; 857 858 const uint64_t TestVal = UINT64_C(0xabcd123344568998); 859 Register CopyMerge = Copies[Copies.size() - 1]; 860 861 GISelKnownBits Info(*MF); 862 KnownBits Res = Info.getKnownBits(CopyMerge); 863 EXPECT_EQ(64u, Res.getBitWidth()); 864 EXPECT_EQ(TestVal, Res.One.getZExtValue()); 865 EXPECT_EQ(~TestVal, Res.Zero.getZExtValue()); 866 } 867 868 TEST_F(AArch64GISelMITest, TestKnownBitsUnmergeValues) { 869 StringRef MIRString = R"( 870 %val:_(s64) = G_CONSTANT i64 12379570962110515608 871 %val0:_(s16), %val1:_(s16), %val2:_(s16), %val3:_(s16) = G_UNMERGE_VALUES %val 872 %part0:_(s16) = COPY %val0 873 %part1:_(s16) = COPY %val1 874 %part2:_(s16) = COPY %val2 875 %part3:_(s16) = COPY %val3 876 877 )"; 878 setUp(MIRString); 879 if (!TM) 880 return; 881 882 const uint64_t TestVal = UINT64_C(0xabcd123344568998); 883 GISelKnownBits Info(*MF); 884 885 int Offset = -4; 886 for (unsigned BitOffset = 0; BitOffset != 64; BitOffset += 16, ++Offset) { 887 Register Part = Copies[Copies.size() + Offset]; 888 KnownBits PartKnown = Info.getKnownBits(Part); 889 EXPECT_EQ(16u, PartKnown.getBitWidth()); 890 891 uint16_t PartTestVal = static_cast<uint16_t>(TestVal >> BitOffset); 892 EXPECT_EQ(PartTestVal, PartKnown.One.getZExtValue()); 893 EXPECT_EQ(static_cast<uint16_t>(~PartTestVal), PartKnown.Zero.getZExtValue()); 894 } 895 } 896 897 TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) { 898 StringRef MIRString = R"( 899 %const:_(s32) = G_CONSTANT i32 287454020 900 %bswap:_(s32) = G_BSWAP %const 901 %bitreverse:_(s32) = G_BITREVERSE %const 902 %copy_bswap:_(s32) = COPY %bswap 903 %copy_bitreverse:_(s32) = COPY %bitreverse 904 )"; 905 setUp(MIRString); 906 if (!TM) 907 return; 908 909 const uint32_t TestVal = 0x11223344; 910 911 Register CopyBSwap = Copies[Copies.size() - 2]; 912 Register CopyBitReverse = Copies[Copies.size() - 1]; 913 914 GISelKnownBits Info(*MF); 915 916 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap); 917 EXPECT_EQ(32u, BSwapKnown.getBitWidth()); 918 EXPECT_EQ(TestVal, BSwapKnown.One.getZExtValue()); 919 EXPECT_EQ(~TestVal, BSwapKnown.Zero.getZExtValue()); 920 921 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse); 922 EXPECT_EQ(32u, BitReverseKnown.getBitWidth()); 923 EXPECT_EQ(TestVal, BitReverseKnown.One.getZExtValue()); 924 EXPECT_EQ(~TestVal, BitReverseKnown.Zero.getZExtValue()); 925 } 926 927 TEST_F(AArch64GISelMITest, TestKnownBitsUMax) { 928 StringRef MIRString = R"( 929 %val:_(s32) = COPY $w0 930 %zext:_(s64) = G_ZEXT %val 931 %const:_(s64) = G_CONSTANT i64 -256 932 %umax:_(s64) = G_UMAX %zext, %const 933 %copy_umax:_(s64) = COPY %umax 934 )"; 935 setUp(MIRString); 936 if (!TM) 937 return; 938 939 Register CopyUMax = Copies[Copies.size() - 1]; 940 GISelKnownBits Info(*MF); 941 942 KnownBits KnownUmax = Info.getKnownBits(CopyUMax); 943 EXPECT_EQ(64u, KnownUmax.getBitWidth()); 944 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue()); 945 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue()); 946 947 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue()); 948 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue()); 949 } 950 951 TEST_F(AArch64GISelMITest, TestInvalidQueries) { 952 StringRef MIRString = R"( 953 %src:_(s32) = COPY $w0 954 %thirty2:_(s32) = G_CONSTANT i32 32 955 %equalSized:_(s32) = G_SHL %src, %thirty2 956 %copy1:_(s32) = COPY %equalSized 957 %thirty3:_(s32) = G_CONSTANT i32 33 958 %biggerSized:_(s32) = G_SHL %src, %thirty3 959 %copy2:_(s32) = COPY %biggerSized 960 )"; 961 setUp(MIRString); 962 if (!TM) 963 return; 964 965 Register EqSizedCopyReg = Copies[Copies.size() - 2]; 966 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg); 967 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg(); 968 969 Register BiggerSizedCopyReg = Copies[Copies.size() - 1]; 970 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg); 971 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg(); 972 973 GISelKnownBits Info(*MF); 974 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl); 975 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl); 976 977 978 // We don't know what the result of the shift is, but we should not crash 979 EXPECT_TRUE(EqSizeRes.One.isNullValue()); 980 EXPECT_TRUE(EqSizeRes.Zero.isNullValue()); 981 982 EXPECT_TRUE(BiggerSizeRes.One.isNullValue()); 983 EXPECT_TRUE(BiggerSizeRes.Zero.isNullValue()); 984 } 985 986 TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) { 987 StringRef MIRString = R"( 988 %copy:_(s64) = COPY $x0 989 990 %assert8:_(s64) = G_ASSERT_ZEXT %copy, 8 991 %copy_assert8:_(s64) = COPY %assert8 992 993 %assert1:_(s64) = G_ASSERT_ZEXT %copy, 1 994 %copy_assert1:_(s64) = COPY %assert1 995 996 %assert63:_(s64) = G_ASSERT_ZEXT %copy, 63 997 %copy_assert63:_(s64) = COPY %assert63 998 999 %assert3:_(s64) = G_ASSERT_ZEXT %copy, 3 1000 %copy_assert3:_(s64) = COPY %assert3 1001 )"; 1002 1003 setUp(MIRString); 1004 if (!TM) 1005 return; 1006 1007 Register CopyAssert8 = Copies[Copies.size() - 4]; 1008 Register CopyAssert1 = Copies[Copies.size() - 3]; 1009 Register CopyAssert63 = Copies[Copies.size() - 2]; 1010 Register CopyAssert3 = Copies[Copies.size() - 1]; 1011 1012 GISelKnownBits Info(*MF); 1013 MachineInstr *Copy; 1014 Register SrcReg; 1015 KnownBits Res; 1016 1017 // Assert zero-extension from an 8-bit value. 1018 Copy = MRI->getVRegDef(CopyAssert8); 1019 SrcReg = Copy->getOperand(1).getReg(); 1020 Res = Info.getKnownBits(SrcReg); 1021 EXPECT_EQ(64u, Res.getBitWidth()); 1022 EXPECT_EQ(0u, Res.One.getZExtValue()); 1023 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue()); 1024 1025 // Assert zero-extension from a 1-bit value. 1026 Copy = MRI->getVRegDef(CopyAssert1); 1027 SrcReg = Copy->getOperand(1).getReg(); 1028 Res = Info.getKnownBits(SrcReg); 1029 EXPECT_EQ(64u, Res.getBitWidth()); 1030 EXPECT_EQ(0u, Res.One.getZExtValue()); 1031 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue()); 1032 1033 // Assert zero-extension from a 63-bit value. 1034 Copy = MRI->getVRegDef(CopyAssert63); 1035 SrcReg = Copy->getOperand(1).getReg(); 1036 Res = Info.getKnownBits(SrcReg); 1037 EXPECT_EQ(64u, Res.getBitWidth()); 1038 EXPECT_EQ(0u, Res.One.getZExtValue()); 1039 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue()); 1040 1041 // Assert zero-extension from a 3-bit value. 1042 Copy = MRI->getVRegDef(CopyAssert3); 1043 SrcReg = Copy->getOperand(1).getReg(); 1044 Res = Info.getKnownBits(SrcReg); 1045 EXPECT_EQ(64u, Res.getBitWidth()); 1046 EXPECT_EQ(0u, Res.One.getZExtValue()); 1047 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue()); 1048 } 1049