1 //===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/CodeGen/SelectionDAG.h"
10 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
11 #include "llvm/AsmParser/Parser.h"
12 #include "llvm/CodeGen/MachineModuleInfo.h"
13 #include "llvm/CodeGen/TargetLowering.h"
14 #include "llvm/Support/SourceMgr.h"
15 #include "llvm/Support/TargetRegistry.h"
16 #include "llvm/Support/TargetSelect.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "gtest/gtest.h"
19 
20 namespace llvm {
21 
22 class AArch64SelectionDAGTest : public testing::Test {
23 protected:
24   static void SetUpTestCase() {
25     InitializeAllTargets();
26     InitializeAllTargetMCs();
27   }
28 
29   void SetUp() override {
30     StringRef Assembly = "define void @f() { ret void }";
31 
32     Triple TargetTriple("aarch64--");
33     std::string Error;
34     const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
35     // FIXME: These tests do not depend on AArch64 specifically, but we have to
36     // initialize a target. A skeleton Target for unittests would allow us to
37     // always run these tests.
38     if (!T)
39       return;
40 
41     TargetOptions Options;
42     TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
43         T->createTargetMachine("AArch64", "", "+sve", Options, None, None,
44                                CodeGenOpt::Aggressive)));
45     if (!TM)
46       return;
47 
48     SMDiagnostic SMError;
49     M = parseAssemblyString(Assembly, SMError, Context);
50     if (!M)
51       report_fatal_error(SMError.getMessage());
52     M->setDataLayout(TM->createDataLayout());
53 
54     F = M->getFunction("f");
55     if (!F)
56       report_fatal_error("F?");
57 
58     MachineModuleInfo MMI(TM.get());
59 
60     MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F), 0,
61                                       MMI);
62 
63     DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::None);
64     if (!DAG)
65       report_fatal_error("DAG?");
66     OptimizationRemarkEmitter ORE(F);
67     DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr);
68   }
69 
70   TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) {
71     return DAG->getTargetLoweringInfo().getTypeAction(Context, VT);
72   }
73 
74   EVT getTypeToTransformTo(EVT VT) {
75     return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT);
76   }
77 
78   LLVMContext Context;
79   std::unique_ptr<LLVMTargetMachine> TM;
80   std::unique_ptr<Module> M;
81   Function *F;
82   std::unique_ptr<MachineFunction> MF;
83   std::unique_ptr<SelectionDAG> DAG;
84 };
85 
86 TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) {
87   if (!TM)
88     return;
89   SDLoc Loc;
90   auto Int8VT = EVT::getIntegerVT(Context, 8);
91   auto Int16VT = EVT::getIntegerVT(Context, 16);
92   auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4);
93   auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2);
94   auto InVec = DAG->getConstant(0, Loc, InVecVT);
95   auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
96   auto DemandedElts = APInt(2, 3);
97   KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
98   EXPECT_TRUE(Known.isZero());
99 }
100 
101 TEST_F(AArch64SelectionDAGTest, computeKnownBitsSVE_ZERO_EXTEND_VECTOR_INREG) {
102   if (!TM)
103     return;
104   SDLoc Loc;
105   auto Int8VT = EVT::getIntegerVT(Context, 8);
106   auto Int16VT = EVT::getIntegerVT(Context, 16);
107   auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4, true);
108   auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2, true);
109   auto InVec = DAG->getConstant(0, Loc, InVecVT);
110   auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
111   auto DemandedElts = APInt(2, 3);
112   KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
113 
114   // We don't know anything for SVE at the moment.
115   EXPECT_EQ(Known.Zero, APInt(16, 0u));
116   EXPECT_EQ(Known.One, APInt(16, 0u));
117   EXPECT_FALSE(Known.isZero());
118 }
119 
120 TEST_F(AArch64SelectionDAGTest, computeKnownBits_EXTRACT_SUBVECTOR) {
121   if (!TM)
122     return;
123   SDLoc Loc;
124   auto IntVT = EVT::getIntegerVT(Context, 8);
125   auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
126   auto IdxVT = EVT::getIntegerVT(Context, 64);
127   auto Vec = DAG->getConstant(0, Loc, VecVT);
128   auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
129   auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
130   auto DemandedElts = APInt(3, 7);
131   KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
132   EXPECT_TRUE(Known.isZero());
133 }
134 
135 TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) {
136   if (!TM)
137     return;
138   SDLoc Loc;
139   auto Int8VT = EVT::getIntegerVT(Context, 8);
140   auto Int16VT = EVT::getIntegerVT(Context, 16);
141   auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4);
142   auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2);
143   auto InVec = DAG->getConstant(1, Loc, InVecVT);
144   auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
145   auto DemandedElts = APInt(2, 3);
146   EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 15u);
147 }
148 
149 TEST_F(AArch64SelectionDAGTest, ComputeNumSignBitsSVE_SIGN_EXTEND_VECTOR_INREG) {
150   if (!TM)
151     return;
152   SDLoc Loc;
153   auto Int8VT = EVT::getIntegerVT(Context, 8);
154   auto Int16VT = EVT::getIntegerVT(Context, 16);
155   auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4, /*IsScalable=*/true);
156   auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2, /*IsScalable=*/true);
157   auto InVec = DAG->getConstant(1, Loc, InVecVT);
158   auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
159   auto DemandedElts = APInt(2, 3);
160   EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 1u);
161 }
162 
163 TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) {
164   if (!TM)
165     return;
166   SDLoc Loc;
167   auto IntVT = EVT::getIntegerVT(Context, 8);
168   auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
169   auto IdxVT = EVT::getIntegerVT(Context, 64);
170   auto Vec = DAG->getConstant(1, Loc, VecVT);
171   auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
172   auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
173   auto DemandedElts = APInt(3, 7);
174   EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 7u);
175 }
176 
177 TEST_F(AArch64SelectionDAGTest, SimplifyDemandedVectorElts_EXTRACT_SUBVECTOR) {
178   if (!TM)
179     return;
180 
181   TargetLowering TL(*TM);
182 
183   SDLoc Loc;
184   auto IntVT = EVT::getIntegerVT(Context, 8);
185   auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
186   auto IdxVT = EVT::getIntegerVT(Context, 64);
187   auto Vec = DAG->getConstant(1, Loc, VecVT);
188   auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
189   auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
190   auto DemandedElts = APInt(3, 7);
191   auto KnownUndef = APInt(3, 0);
192   auto KnownZero = APInt(3, 0);
193   TargetLowering::TargetLoweringOpt TLO(*DAG, false, false);
194   EXPECT_EQ(TL.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef,
195                                           KnownZero, TLO),
196             false);
197 }
198 
199 TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsNEON) {
200   if (!TM)
201     return;
202 
203   TargetLowering TL(*TM);
204 
205   SDLoc Loc;
206   auto Int8VT = EVT::getIntegerVT(Context, 8);
207   auto InVecVT = EVT::getVectorVT(Context, Int8VT, 16);
208   SDValue UnknownOp = DAG->getRegister(0, InVecVT);
209   SDValue Mask1S = DAG->getConstant(0x8A, Loc, Int8VT);
210   SDValue Mask1V = DAG->getSplatBuildVector(InVecVT, Loc, Mask1S);
211   SDValue N0 = DAG->getNode(ISD::AND, Loc, InVecVT, Mask1V, UnknownOp);
212 
213   SDValue Mask2S = DAG->getConstant(0x55, Loc, Int8VT);
214   SDValue Mask2V = DAG->getSplatBuildVector(InVecVT, Loc, Mask2S);
215 
216   SDValue Op = DAG->getNode(ISD::AND, Loc, InVecVT, N0, Mask2V);
217   // N0 = ?000?0?0
218   // Mask2V = 01010101
219   //  =>
220   // Known.Zero = 00100000 (0xAA)
221   KnownBits Known;
222   APInt DemandedBits = APInt(8, 0xFF);
223   TargetLowering::TargetLoweringOpt TLO(*DAG, false, false);
224   EXPECT_TRUE(TL.SimplifyDemandedBits(Op, DemandedBits, Known, TLO));
225   EXPECT_EQ(Known.Zero, APInt(8, 0xAA));
226 }
227 
228 TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsSVE) {
229   if (!TM)
230     return;
231 
232   TargetLowering TL(*TM);
233 
234   SDLoc Loc;
235   auto Int8VT = EVT::getIntegerVT(Context, 8);
236   auto InVecVT = EVT::getVectorVT(Context, Int8VT, 16, /*IsScalable=*/true);
237   SDValue UnknownOp = DAG->getRegister(0, InVecVT);
238   SDValue Mask1S = DAG->getConstant(0x8A, Loc, Int8VT);
239   SDValue Mask1V = DAG->getSplatVector(InVecVT, Loc, Mask1S);
240   SDValue N0 = DAG->getNode(ISD::AND, Loc, InVecVT, Mask1V, UnknownOp);
241 
242   SDValue Mask2S = DAG->getConstant(0x55, Loc, Int8VT);
243   SDValue Mask2V = DAG->getSplatVector(InVecVT, Loc, Mask2S);
244 
245   SDValue Op = DAG->getNode(ISD::AND, Loc, InVecVT, N0, Mask2V);
246 
247   KnownBits Known;
248   APInt DemandedBits = APInt(8, 0xFF);
249   TargetLowering::TargetLoweringOpt TLO(*DAG, false, false);
250   EXPECT_FALSE(TL.SimplifyDemandedBits(Op, DemandedBits, Known, TLO));
251   EXPECT_EQ(Known.Zero, APInt(8, 0));
252 }
253 
254 // Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
255 TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_ADD) {
256   if (!TM)
257     return;
258   SDLoc Loc;
259   auto IntVT = EVT::getIntegerVT(Context, 8);
260   auto UnknownOp = DAG->getRegister(0, IntVT);
261   auto Mask = DAG->getConstant(0x8A, Loc, IntVT);
262   auto N0 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp);
263   auto N1 = DAG->getConstant(0x55, Loc, IntVT);
264   auto Op = DAG->getNode(ISD::ADD, Loc, IntVT, N0, N1);
265   // N0 = ?000?0?0
266   // N1 = 01010101
267   //  =>
268   // Known.One  = 01010101 (0x55)
269   // Known.Zero = 00100000 (0x20)
270   KnownBits Known = DAG->computeKnownBits(Op);
271   EXPECT_EQ(Known.Zero, APInt(8, 0x20));
272   EXPECT_EQ(Known.One, APInt(8, 0x55));
273 }
274 
275 // Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
276 TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) {
277   if (!TM)
278     return;
279   SDLoc Loc;
280   auto IntVT = EVT::getIntegerVT(Context, 8);
281   auto N0 = DAG->getConstant(0x55, Loc, IntVT);
282   auto UnknownOp = DAG->getRegister(0, IntVT);
283   auto Mask = DAG->getConstant(0x2e, Loc, IntVT);
284   auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp);
285   auto Op = DAG->getNode(ISD::SUB, Loc, IntVT, N0, N1);
286   // N0 = 01010101
287   // N1 = 00?0???0
288   //  =>
289   // Known.One  = 00000001 (0x1)
290   // Known.Zero = 10000000 (0x80)
291   KnownBits Known = DAG->computeKnownBits(Op);
292   EXPECT_EQ(Known.Zero, APInt(8, 0x80));
293   EXPECT_EQ(Known.One, APInt(8, 0x1));
294 }
295 
296 TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
297   if (!TM)
298     return;
299 
300   TargetLowering TL(*TM);
301 
302   SDLoc Loc;
303   auto IntVT = EVT::getIntegerVT(Context, 8);
304   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
305   // Create a BUILD_VECTOR
306   SDValue Op = DAG->getConstant(1, Loc, VecVT);
307   EXPECT_EQ(Op->getOpcode(), ISD::BUILD_VECTOR);
308   EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
309 
310   APInt UndefElts;
311   APInt DemandedElts;
312   EXPECT_FALSE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
313 
314   // Width=16, Mask=3
315   DemandedElts = APInt(16, 3);
316   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
317 }
318 
319 TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_ADD_of_BUILD_VECTOR) {
320   if (!TM)
321     return;
322 
323   TargetLowering TL(*TM);
324 
325   SDLoc Loc;
326   auto IntVT = EVT::getIntegerVT(Context, 8);
327   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
328 
329   // Should create BUILD_VECTORs
330   SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
331   SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
332   EXPECT_EQ(Val1->getOpcode(), ISD::BUILD_VECTOR);
333   SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
334 
335   EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
336 
337   APInt UndefElts;
338   APInt DemandedElts;
339   EXPECT_FALSE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
340 
341   // Width=16, Mask=3
342   DemandedElts = APInt(16, 3);
343   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
344 }
345 
346 TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_SPLAT_VECTOR) {
347   if (!TM)
348     return;
349 
350   TargetLowering TL(*TM);
351 
352   SDLoc Loc;
353   auto IntVT = EVT::getIntegerVT(Context, 8);
354   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
355   // Create a SPLAT_VECTOR
356   SDValue Op = DAG->getConstant(1, Loc, VecVT);
357   EXPECT_EQ(Op->getOpcode(), ISD::SPLAT_VECTOR);
358   EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
359 
360   APInt UndefElts;
361   APInt DemandedElts;
362   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
363 
364   // Width=16, Mask=3. These bits should be ignored.
365   DemandedElts = APInt(16, 3);
366   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
367 }
368 
369 TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_ADD_of_SPLAT_VECTOR) {
370   if (!TM)
371     return;
372 
373   TargetLowering TL(*TM);
374 
375   SDLoc Loc;
376   auto IntVT = EVT::getIntegerVT(Context, 8);
377   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
378 
379   // Should create SPLAT_VECTORS
380   SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
381   SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
382   EXPECT_EQ(Val1->getOpcode(), ISD::SPLAT_VECTOR);
383   SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
384 
385   EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
386 
387   APInt UndefElts;
388   APInt DemandedElts;
389   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
390 
391   // Width=16, Mask=3. These bits should be ignored.
392   DemandedElts = APInt(16, 3);
393   EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
394 }
395 
396 TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_BUILD_VECTOR) {
397   if (!TM)
398     return;
399 
400   TargetLowering TL(*TM);
401 
402   SDLoc Loc;
403   auto IntVT = EVT::getIntegerVT(Context, 8);
404   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
405   // Create a BUILD_VECTOR
406   SDValue Op = DAG->getConstant(1, Loc, VecVT);
407   EXPECT_EQ(Op->getOpcode(), ISD::BUILD_VECTOR);
408 
409   int SplatIdx = -1;
410   EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
411   EXPECT_EQ(SplatIdx, 0);
412 }
413 
414 TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_ADD_of_BUILD_VECTOR) {
415   if (!TM)
416     return;
417 
418   TargetLowering TL(*TM);
419 
420   SDLoc Loc;
421   auto IntVT = EVT::getIntegerVT(Context, 8);
422   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
423 
424   // Should create BUILD_VECTORs
425   SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
426   SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
427   EXPECT_EQ(Val1->getOpcode(), ISD::BUILD_VECTOR);
428   SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
429 
430   int SplatIdx = -1;
431   EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
432   EXPECT_EQ(SplatIdx, 0);
433 }
434 
435 TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_SPLAT_VECTOR) {
436   if (!TM)
437     return;
438 
439   TargetLowering TL(*TM);
440 
441   SDLoc Loc;
442   auto IntVT = EVT::getIntegerVT(Context, 8);
443   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
444   // Create a SPLAT_VECTOR
445   SDValue Op = DAG->getConstant(1, Loc, VecVT);
446   EXPECT_EQ(Op->getOpcode(), ISD::SPLAT_VECTOR);
447 
448   int SplatIdx = -1;
449   EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
450   EXPECT_EQ(SplatIdx, 0);
451 }
452 
453 TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTOR) {
454   if (!TM)
455     return;
456 
457   TargetLowering TL(*TM);
458 
459   SDLoc Loc;
460   auto IntVT = EVT::getIntegerVT(Context, 8);
461   auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
462 
463   // Should create SPLAT_VECTORS
464   SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
465   SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
466   EXPECT_EQ(Val1->getOpcode(), ISD::SPLAT_VECTOR);
467   SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
468 
469   int SplatIdx = -1;
470   EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
471   EXPECT_EQ(SplatIdx, 0);
472 }
473 
474 TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableMVT) {
475   if (!TM)
476     return;
477 
478   MVT VT = MVT::nxv4i64;
479   EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
480   ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
481 }
482 
483 TEST_F(AArch64SelectionDAGTest, getTypeConversion_PromoteScalableMVT) {
484   if (!TM)
485     return;
486 
487   MVT VT = MVT::nxv2i32;
488   EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypePromoteInteger);
489   ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
490 }
491 
492 TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeMVT_nxv1f32) {
493   if (!TM)
494     return;
495 
496   MVT VT = MVT::nxv1f32;
497   EXPECT_NE(getTypeAction(VT), TargetLoweringBase::TypeScalarizeVector);
498   ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
499 }
500 
501 TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableEVT) {
502   if (!TM)
503     return;
504 
505   EVT VT = EVT::getVectorVT(Context, MVT::i64, 256, true);
506   EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
507   EXPECT_EQ(getTypeToTransformTo(VT), VT.getHalfNumVectorElementsVT(Context));
508 }
509 
510 TEST_F(AArch64SelectionDAGTest, getTypeConversion_WidenScalableEVT) {
511   if (!TM)
512     return;
513 
514   EVT FromVT = EVT::getVectorVT(Context, MVT::i64, 6, true);
515   EVT ToVT = EVT::getVectorVT(Context, MVT::i64, 8, true);
516 
517   EXPECT_EQ(getTypeAction(FromVT), TargetLoweringBase::TypeWidenVector);
518   EXPECT_EQ(getTypeToTransformTo(FromVT), ToVT);
519 }
520 
521 TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeEVT_nxv1f128) {
522   if (!TM)
523     return;
524 
525   EVT FromVT = EVT::getVectorVT(Context, MVT::f128, 1, true);
526   EXPECT_DEATH(getTypeAction(FromVT), "Cannot legalize this vector");
527 }
528 
529 } // end namespace llvm
530