1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -vector-combine -data-layout=e < %s | FileCheck %s 3; RUN: opt -S -vector-combine -data-layout=E < %s | FileCheck %s 4 5define void @insert_store(<16 x i8>* %q, i8 zeroext %s) { 6; CHECK-LABEL: @insert_store( 7; CHECK-NEXT: entry: 8; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q:%.*]], i32 0, i32 3 9; CHECK-NEXT: store i8 [[S:%.*]], i8* [[TMP0]], align 1 10; CHECK-NEXT: ret void 11; 12entry: 13 %0 = load <16 x i8>, <16 x i8>* %q 14 %vecins = insertelement <16 x i8> %0, i8 %s, i32 3 15 store <16 x i8> %vecins, <16 x i8>* %q, align 16 16 ret void 17} 18 19define void @insert_store_i16_align1(<8 x i16>* %q, i16 zeroext %s) { 20; CHECK-LABEL: @insert_store_i16_align1( 21; CHECK-NEXT: entry: 22; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[Q:%.*]], i32 0, i32 3 23; CHECK-NEXT: store i16 [[S:%.*]], i16* [[TMP0]], align 1 24; CHECK-NEXT: ret void 25; 26entry: 27 %0 = load <8 x i16>, <8 x i16>* %q 28 %vecins = insertelement <8 x i16> %0, i16 %s, i32 3 29 store <8 x i16> %vecins, <8 x i16>* %q, align 1 30 ret void 31} 32 33; To verify case when index is out of bounds 34define void @insert_store_outofbounds(<8 x i16>* %q, i16 zeroext %s) { 35; CHECK-LABEL: @insert_store_outofbounds( 36; CHECK-NEXT: entry: 37; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[Q:%.*]], align 16 38; CHECK-NEXT: [[VECINS:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 9 39; CHECK-NEXT: store <8 x i16> [[VECINS]], <8 x i16>* [[Q]], align 16 40; CHECK-NEXT: ret void 41; 42entry: 43 %0 = load <8 x i16>, <8 x i16>* %q 44 %vecins = insertelement <8 x i16> %0, i16 %s, i32 9 45 store <8 x i16> %vecins, <8 x i16>* %q 46 ret void 47} 48 49define void @insert_store_vscale(<vscale x 8 x i16>* %q, i16 zeroext %s) { 50; CHECK-LABEL: @insert_store_vscale( 51; CHECK-NEXT: entry: 52; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 8 x i16>, <vscale x 8 x i16>* [[Q:%.*]], align 16 53; CHECK-NEXT: [[VECINS:%.*]] = insertelement <vscale x 8 x i16> [[TMP0]], i16 [[S:%.*]], i32 3 54; CHECK-NEXT: store <vscale x 8 x i16> [[VECINS]], <vscale x 8 x i16>* [[Q]], align 16 55; CHECK-NEXT: ret void 56; 57entry: 58 %0 = load <vscale x 8 x i16>, <vscale x 8 x i16>* %q 59 %vecins = insertelement <vscale x 8 x i16> %0, i16 %s, i32 3 60 store <vscale x 8 x i16> %vecins, <vscale x 8 x i16>* %q 61 ret void 62} 63 64define void @insert_store_v9i4(<9 x i4>* %q, i4 zeroext %s) { 65; CHECK-LABEL: @insert_store_v9i4( 66; CHECK-NEXT: entry: 67; CHECK-NEXT: [[TMP0:%.*]] = load <9 x i4>, <9 x i4>* [[Q:%.*]], align 16 68; CHECK-NEXT: [[VECINS:%.*]] = insertelement <9 x i4> [[TMP0]], i4 [[S:%.*]], i32 3 69; CHECK-NEXT: store <9 x i4> [[VECINS]], <9 x i4>* [[Q]], align 1 70; CHECK-NEXT: ret void 71; 72entry: 73 %0 = load <9 x i4>, <9 x i4>* %q 74 %vecins = insertelement <9 x i4> %0, i4 %s, i32 3 75 store <9 x i4> %vecins, <9 x i4>* %q, align 1 76 ret void 77} 78 79define void @insert_store_v4i27(<4 x i27>* %q, i27 zeroext %s) { 80; CHECK-LABEL: @insert_store_v4i27( 81; CHECK-NEXT: entry: 82; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i27>, <4 x i27>* [[Q:%.*]], align 16 83; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x i27> [[TMP0]], i27 [[S:%.*]], i32 3 84; CHECK-NEXT: store <4 x i27> [[VECINS]], <4 x i27>* [[Q]], align 1 85; CHECK-NEXT: ret void 86; 87entry: 88 %0 = load <4 x i27>, <4 x i27>* %q 89 %vecins = insertelement <4 x i27> %0, i27 %s, i32 3 90 store <4 x i27> %vecins, <4 x i27>* %q, align 1 91 ret void 92} 93 94define void @insert_store_blk_differ(<8 x i16>* %q, i16 zeroext %s) { 95; CHECK-LABEL: @insert_store_blk_differ( 96; CHECK-NEXT: entry: 97; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[Q:%.*]], align 16 98; CHECK-NEXT: br label [[CONT:%.*]] 99; CHECK: cont: 100; CHECK-NEXT: [[VECINS:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 3 101; CHECK-NEXT: store <8 x i16> [[VECINS]], <8 x i16>* [[Q]], align 16 102; CHECK-NEXT: ret void 103; 104entry: 105 %0 = load <8 x i16>, <8 x i16>* %q 106 br label %cont 107cont: 108 %vecins = insertelement <8 x i16> %0, i16 %s, i32 3 109 store <8 x i16> %vecins, <8 x i16>* %q 110 ret void 111} 112 113define void @insert_store_nonconst(<16 x i8>* %q, i8 zeroext %s, i32 %idx) { 114; CHECK-LABEL: @insert_store_nonconst( 115; CHECK-NEXT: entry: 116; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16 117; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX:%.*]] 118; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16 119; CHECK-NEXT: ret void 120; 121entry: 122 %0 = load <16 x i8>, <16 x i8>* %q 123 %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 124 store <16 x i8> %vecins, <16 x i8>* %q 125 ret void 126} 127 128define void @insert_store_nonconst_index_known_valid_by_assume(<16 x i8>* %q, i8 zeroext %s, i32 %idx) { 129; CHECK-LABEL: @insert_store_nonconst_index_known_valid_by_assume( 130; CHECK-NEXT: entry: 131; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4 132; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 133; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16 134; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX]] 135; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16 136; CHECK-NEXT: ret void 137; 138entry: 139 %cmp = icmp ult i32 %idx, 4 140 call void @llvm.assume(i1 %cmp) 141 %0 = load <16 x i8>, <16 x i8>* %q 142 %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 143 store <16 x i8> %vecins, <16 x i8>* %q 144 ret void 145} 146 147declare void @maythrow() readnone 148 149define void @insert_store_nonconst_index_not_known_valid_by_assume_after_load(<16 x i8>* %q, i8 zeroext %s, i32 %idx) { 150; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_assume_after_load( 151; CHECK-NEXT: entry: 152; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4 153; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16 154; CHECK-NEXT: call void @maythrow() 155; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 156; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX]] 157; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16 158; CHECK-NEXT: ret void 159; 160entry: 161 %cmp = icmp ult i32 %idx, 4 162 %0 = load <16 x i8>, <16 x i8>* %q 163 call void @maythrow() 164 call void @llvm.assume(i1 %cmp) 165 %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 166 store <16 x i8> %vecins, <16 x i8>* %q 167 ret void 168} 169 170define void @insert_store_nonconst_index_not_known_valid_by_assume(<16 x i8>* %q, i8 zeroext %s, i32 %idx) { 171; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_assume( 172; CHECK-NEXT: entry: 173; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 17 174; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 175; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16 176; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX]] 177; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16 178; CHECK-NEXT: ret void 179; 180entry: 181 %cmp = icmp ult i32 %idx, 17 182 call void @llvm.assume(i1 %cmp) 183 %0 = load <16 x i8>, <16 x i8>* %q 184 %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 185 store <16 x i8> %vecins, <16 x i8>* %q 186 ret void 187} 188 189declare void @llvm.assume(i1) 190 191define void @insert_store_ptr_strip(<16 x i8>* %q, i8 zeroext %s) { 192; CHECK-LABEL: @insert_store_ptr_strip( 193; CHECK-NEXT: entry: 194; CHECK-NEXT: [[ADDR0:%.*]] = bitcast <16 x i8>* [[Q:%.*]] to <2 x i64>* 195; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q]], i32 0, i32 3 196; CHECK-NEXT: store i8 [[S:%.*]], i8* [[TMP0]], align 1 197; CHECK-NEXT: ret void 198; 199entry: 200 %0 = load <16 x i8>, <16 x i8>* %q 201 %vecins = insertelement <16 x i8> %0, i8 %s, i32 3 202 %addr0 = bitcast <16 x i8>* %q to <2 x i64>* 203 %addr1 = getelementptr <2 x i64>, <2 x i64>* %addr0, i64 0 204 %addr2 = bitcast <2 x i64>* %addr1 to <16 x i8>* 205 store <16 x i8> %vecins, <16 x i8>* %addr2 206 ret void 207} 208 209define void @volatile_update(<16 x i8>* %q, <16 x i8>* %p, i8 zeroext %s) { 210; CHECK-LABEL: @volatile_update( 211; CHECK-NEXT: entry: 212; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16 213; CHECK-NEXT: [[VECINS0:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3 214; CHECK-NEXT: store volatile <16 x i8> [[VECINS0]], <16 x i8>* [[Q]], align 16 215; CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* [[P:%.*]], align 16 216; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[S]], i32 1 217; CHECK-NEXT: store <16 x i8> [[VECINS1]], <16 x i8>* [[P]], align 16 218; CHECK-NEXT: ret void 219; 220entry: 221 %0 = load <16 x i8>, <16 x i8>* %q 222 %vecins0 = insertelement <16 x i8> %0, i8 %s, i32 3 223 store volatile <16 x i8> %vecins0, <16 x i8>* %q 224 225 %1 = load volatile <16 x i8>, <16 x i8>* %p 226 %vecins1 = insertelement <16 x i8> %1, i8 %s, i32 1 227 store <16 x i8> %vecins1, <16 x i8>* %p 228 ret void 229} 230 231define void @insert_store_addr_differ(<16 x i8>* %p, <16 x i8>* %q, i8 %s) { 232; CHECK-LABEL: @insert_store_addr_differ( 233; CHECK-NEXT: entry: 234; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16 235; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3 236; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[Q:%.*]], align 16 237; CHECK-NEXT: ret void 238; 239entry: 240 %ld = load <16 x i8>, <16 x i8>* %p 241 %ins = insertelement <16 x i8> %ld, i8 %s, i32 3 242 store <16 x i8> %ins, <16 x i8>* %q 243 ret void 244} 245 246; We can't transform if any instr could modify memory in between. 247define void @insert_store_mem_modify(<16 x i8>* %p, <16 x i8>* %q, <16 x i8>* noalias %r, i8 %s, i32 %m) { 248; CHECK-LABEL: @insert_store_mem_modify( 249; CHECK-NEXT: entry: 250; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16 251; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[Q:%.*]], align 16 252; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3 253; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16 254; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[R:%.*]], align 16 255; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q]], i32 0, i32 7 256; CHECK-NEXT: store i8 [[S]], i8* [[TMP0]], align 1 257; CHECK-NEXT: [[PTR0:%.*]] = bitcast <16 x i8>* [[P]] to <4 x i32>* 258; CHECK-NEXT: [[LD3:%.*]] = load <4 x i32>, <4 x i32>* [[PTR0]], align 16 259; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[P]], align 16 260; CHECK-NEXT: [[INS3:%.*]] = insertelement <4 x i32> [[LD3]], i32 [[M:%.*]], i32 0 261; CHECK-NEXT: store <4 x i32> [[INS3]], <4 x i32>* [[PTR0]], align 16 262; CHECK-NEXT: ret void 263; 264entry: 265 ; p may alias q 266 %ld = load <16 x i8>, <16 x i8>* %p 267 store <16 x i8> zeroinitializer, <16 x i8>* %q 268 %ins = insertelement <16 x i8> %ld, i8 %s, i32 3 269 store <16 x i8> %ins, <16 x i8>* %p 270 271 ; p never aliases r 272 %ld2 = load <16 x i8>, <16 x i8>* %q 273 store <16 x i8> zeroinitializer, <16 x i8>* %r 274 %ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7 275 store <16 x i8> %ins2, <16 x i8>* %q 276 277 ; p must alias ptr0 278 %ptr0 = bitcast <16 x i8>* %p to <4 x i32>* 279 %ld3 = load <4 x i32>, <4 x i32>* %ptr0 280 store <16 x i8> zeroinitializer, <16 x i8>* %p 281 %ins3 = insertelement <4 x i32> %ld3, i32 %m, i32 0 282 store <4 x i32> %ins3, <4 x i32>* %ptr0 283 284 ret void 285} 286 287; Check cases when calls may modify memory 288define void @insert_store_with_call(<16 x i8>* %p, <16 x i8>* %q, i8 %s) { 289; CHECK-LABEL: @insert_store_with_call( 290; CHECK-NEXT: entry: 291; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16 292; CHECK-NEXT: call void @maywrite(<16 x i8>* [[P]]) 293; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3 294; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16 295; CHECK-NEXT: call void @foo() 296; CHECK-NEXT: call void @nowrite(<16 x i8>* [[P]]) 297; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[P]], i32 0, i32 7 298; CHECK-NEXT: store i8 [[S]], i8* [[TMP0]], align 1 299; CHECK-NEXT: ret void 300; 301entry: 302 %ld = load <16 x i8>, <16 x i8>* %p 303 call void @maywrite(<16 x i8>* %p) 304 %ins = insertelement <16 x i8> %ld, i8 %s, i32 3 305 store <16 x i8> %ins, <16 x i8>* %p 306 call void @foo() ; Barrier 307 %ld2 = load <16 x i8>, <16 x i8>* %p 308 call void @nowrite(<16 x i8>* %p) 309 %ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7 310 store <16 x i8> %ins2, <16 x i8>* %p 311 ret void 312} 313 314declare void @foo() 315declare void @maywrite(<16 x i8>*) 316declare void @nowrite(<16 x i8>*) readonly 317 318; To test if number of instructions in-between exceeds the limit (default 30), 319; the combine will quit. 320define i32 @insert_store_maximum_scan_instrs(i32 %arg, i16* %arg1, <16 x i8>* %arg2, i8 zeroext %arg3) { 321; CHECK-LABEL: @insert_store_maximum_scan_instrs( 322; CHECK-NEXT: bb: 323; CHECK-NEXT: [[I:%.*]] = or i32 [[ARG:%.*]], 1 324; CHECK-NEXT: [[I4:%.*]] = load <16 x i8>, <16 x i8>* [[ARG2:%.*]], align 16 325; CHECK-NEXT: [[I5:%.*]] = tail call i32 @bar(i32 [[I]], i1 true) 326; CHECK-NEXT: [[I6:%.*]] = shl i32 [[ARG]], [[I5]] 327; CHECK-NEXT: [[I7:%.*]] = lshr i32 [[I6]], 26 328; CHECK-NEXT: [[I8:%.*]] = trunc i32 [[I7]] to i8 329; CHECK-NEXT: [[I9:%.*]] = and i8 [[I8]], 31 330; CHECK-NEXT: [[I10:%.*]] = lshr i32 [[I6]], 11 331; CHECK-NEXT: [[I11:%.*]] = and i32 [[I10]], 32767 332; CHECK-NEXT: [[I12:%.*]] = zext i8 [[I9]] to i64 333; CHECK-NEXT: [[I13:%.*]] = getelementptr inbounds i16, i16* [[ARG1:%.*]], i64 [[I12]] 334; CHECK-NEXT: [[I14:%.*]] = load i16, i16* [[I13]], align 2 335; CHECK-NEXT: [[I15:%.*]] = zext i16 [[I14]] to i32 336; CHECK-NEXT: [[I16:%.*]] = add nuw nsw i8 [[I9]], 1 337; CHECK-NEXT: [[I17:%.*]] = zext i8 [[I16]] to i64 338; CHECK-NEXT: [[I18:%.*]] = getelementptr inbounds i16, i16* [[ARG1]], i64 [[I17]] 339; CHECK-NEXT: [[I19:%.*]] = load i16, i16* [[I18]], align 2 340; CHECK-NEXT: [[I20:%.*]] = zext i16 [[I19]] to i32 341; CHECK-NEXT: [[I21:%.*]] = sub nsw i32 [[I20]], [[I15]] 342; CHECK-NEXT: [[I22:%.*]] = mul nsw i32 [[I11]], [[I21]] 343; CHECK-NEXT: [[I23:%.*]] = ashr i32 [[I22]], 15 344; CHECK-NEXT: [[I24:%.*]] = shl nuw nsw i32 [[I5]], 15 345; CHECK-NEXT: [[I25:%.*]] = xor i32 [[I24]], 1015808 346; CHECK-NEXT: [[I26:%.*]] = add nuw nsw i32 [[I25]], [[I15]] 347; CHECK-NEXT: [[I27:%.*]] = add nsw i32 [[I26]], [[I23]] 348; CHECK-NEXT: [[I28:%.*]] = sitofp i32 [[ARG]] to double 349; CHECK-NEXT: [[I29:%.*]] = tail call double @llvm.log2.f64(double [[I28]]) 350; CHECK-NEXT: [[I30:%.*]] = fptosi double [[I29]] to i32 351; CHECK-NEXT: [[I31:%.*]] = shl nsw i32 [[I30]], 15 352; CHECK-NEXT: [[I32:%.*]] = or i32 [[I31]], 4 353; CHECK-NEXT: [[I33:%.*]] = icmp eq i32 [[I27]], [[I32]] 354; CHECK-NEXT: [[I34:%.*]] = select i1 [[I33]], i32 [[ARG]], i32 [[I31]] 355; CHECK-NEXT: [[I35:%.*]] = lshr i32 [[I34]], 1 356; CHECK-NEXT: [[I36:%.*]] = insertelement <16 x i8> [[I4]], i8 [[ARG3:%.*]], i32 3 357; CHECK-NEXT: store <16 x i8> [[I36]], <16 x i8>* [[ARG2]], align 16 358; CHECK-NEXT: ret i32 [[I35]] 359; 360bb: 361 %i = or i32 %arg, 1 362 %i4 = load <16 x i8>, <16 x i8>* %arg2, align 16 363 %i5 = tail call i32 @bar(i32 %i, i1 true) 364 %i6 = shl i32 %arg, %i5 365 %i7 = lshr i32 %i6, 26 366 %i8 = trunc i32 %i7 to i8 367 %i9 = and i8 %i8, 31 368 %i10 = lshr i32 %i6, 11 369 %i11 = and i32 %i10, 32767 370 %i12 = zext i8 %i9 to i64 371 %i13 = getelementptr inbounds i16, i16* %arg1, i64 %i12 372 %i14 = load i16, i16* %i13, align 2 373 %i15 = zext i16 %i14 to i32 374 %i16 = add nuw nsw i8 %i9, 1 375 %i17 = zext i8 %i16 to i64 376 %i18 = getelementptr inbounds i16, i16* %arg1, i64 %i17 377 %i19 = load i16, i16* %i18, align 2 378 %i20 = zext i16 %i19 to i32 379 %i21 = sub nsw i32 %i20, %i15 380 %i22 = mul nsw i32 %i11, %i21 381 %i23 = ashr i32 %i22, 15 382 %i24 = shl nuw nsw i32 %i5, 15 383 %i25 = xor i32 %i24, 1015808 384 %i26 = add nuw nsw i32 %i25, %i15 385 %i27 = add nsw i32 %i26, %i23 386 %i28 = sitofp i32 %arg to double 387 %i29 = tail call double @llvm.log2.f64(double %i28) 388 %i30 = fptosi double %i29 to i32 389 %i31 = shl nsw i32 %i30, 15 390 %i32 = or i32 %i31, 4 391 %i33 = icmp eq i32 %i27, %i32 392 %i34 = select i1 %i33, i32 %arg, i32 %i31 393 %i35 = lshr i32 %i34, 1 394 %i36 = insertelement <16 x i8> %i4, i8 %arg3, i32 3 395 store <16 x i8> %i36, <16 x i8>* %arg2, align 16 396 ret i32 %i35 397} 398 399declare i32 @bar(i32, i1) readonly 400declare double @llvm.log2.f64(double) 401