1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
3; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s
4
5declare void @foo1()
6
7declare void @foo2()
8
9define void @test1(i32 %V) {
10; CHECK-LABEL: @test1(
11; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
12; CHECK-NEXT:    i32 17, label [[T:%.*]]
13; CHECK-NEXT:    i32 4, label [[T]]
14; CHECK-NEXT:    ]
15; CHECK:       T:
16; CHECK-NEXT:    call void @foo1()
17; CHECK-NEXT:    ret void
18; CHECK:       F:
19; CHECK-NEXT:    call void @foo2()
20; CHECK-NEXT:    ret void
21;
22  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
23  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
24  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
25  br i1 %CN, label %T, label %F
26T:              ; preds = %0
27  call void @foo1( )
28  ret void
29F:              ; preds = %0
30  call void @foo2( )
31  ret void
32}
33
34define void @test1_select(i32 %V) {
35; CHECK-LABEL: @test1_select(
36; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
37; CHECK-NEXT:    i32 17, label [[T:%.*]]
38; CHECK-NEXT:    i32 4, label [[T]]
39; CHECK-NEXT:    ]
40; CHECK:       T:
41; CHECK-NEXT:    call void @foo1()
42; CHECK-NEXT:    ret void
43; CHECK:       F:
44; CHECK-NEXT:    call void @foo2()
45; CHECK-NEXT:    ret void
46;
47  %C1 = icmp eq i32 %V, 4
48  %C2 = icmp eq i32 %V, 17
49  %CN = select i1 %C1, i1 true, i1 %C2
50  br i1 %CN, label %T, label %F
51T:
52  call void @foo1( )
53  ret void
54F:
55  call void @foo2( )
56  ret void
57}
58
59define void @test1_ptr(i32* %V) {
60; DL-LABEL: @test1_ptr(
61; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
62; DL-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
63; DL-NEXT:    i32 17, label [[T:%.*]]
64; DL-NEXT:    i32 4, label [[T]]
65; DL-NEXT:    ]
66; DL:       T:
67; DL-NEXT:    call void @foo1()
68; DL-NEXT:    ret void
69; DL:       F:
70; DL-NEXT:    call void @foo2()
71; DL-NEXT:    ret void
72;
73  %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
74  %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
75  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
76  br i1 %CN, label %T, label %F
77T:              ; preds = %0
78  call void @foo1( )
79  ret void
80F:              ; preds = %0
81  call void @foo2( )
82  ret void
83}
84
85define void @test1_ptr_as1(i32 addrspace(1)* %V) {
86; DL-LABEL: @test1_ptr_as1(
87; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16
88; DL-NEXT:    switch i16 [[MAGICPTR]], label [[F:%.*]] [
89; DL-NEXT:    i16 17, label [[T:%.*]]
90; DL-NEXT:    i16 4, label [[T]]
91; DL-NEXT:    ]
92; DL:       T:
93; DL-NEXT:    call void @foo1()
94; DL-NEXT:    ret void
95; DL:       F:
96; DL-NEXT:    call void @foo2()
97; DL-NEXT:    ret void
98;
99  %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
100  %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
101  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
102  br i1 %CN, label %T, label %F
103T:              ; preds = %0
104  call void @foo1( )
105  ret void
106F:              ; preds = %0
107  call void @foo2( )
108  ret void
109}
110
111define void @test2(i32 %V) {
112; CHECK-LABEL: @test2(
113; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
114; CHECK-NEXT:    i32 17, label [[F:%.*]]
115; CHECK-NEXT:    i32 4, label [[F]]
116; CHECK-NEXT:    ]
117; CHECK:       T:
118; CHECK-NEXT:    call void @foo1()
119; CHECK-NEXT:    ret void
120; CHECK:       F:
121; CHECK-NEXT:    call void @foo2()
122; CHECK-NEXT:    ret void
123;
124  %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
125  %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
126  %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
127  br i1 %CN, label %T, label %F
128T:              ; preds = %0
129  call void @foo1( )
130  ret void
131F:              ; preds = %0
132  call void @foo2( )
133  ret void
134}
135
136define void @test2_select(i32 %V) {
137; CHECK-LABEL: @test2_select(
138; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
139; CHECK-NEXT:    i32 17, label [[F:%.*]]
140; CHECK-NEXT:    i32 4, label [[F]]
141; CHECK-NEXT:    ]
142; CHECK:       T:
143; CHECK-NEXT:    call void @foo1()
144; CHECK-NEXT:    ret void
145; CHECK:       F:
146; CHECK-NEXT:    call void @foo2()
147; CHECK-NEXT:    ret void
148;
149  %C1 = icmp ne i32 %V, 4
150  %C2 = icmp ne i32 %V, 17
151  %CN = select i1 %C1, i1 %C2, i1 false
152  br i1 %CN, label %T, label %F
153T:
154  call void @foo1( )
155  ret void
156F:
157  call void @foo2( )
158  ret void
159}
160
161define void @test3(i32 %V) {
162; CHECK-LABEL: @test3(
163; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
164; CHECK-NEXT:    i32 4, label [[T:%.*]]
165; CHECK-NEXT:    i32 17, label [[T]]
166; CHECK-NEXT:    ]
167; CHECK:       T:
168; CHECK-NEXT:    call void @foo1()
169; CHECK-NEXT:    ret void
170; CHECK:       F:
171; CHECK-NEXT:    call void @foo2()
172; CHECK-NEXT:    ret void
173;
174  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
175  br i1 %C1, label %T, label %N
176N:              ; preds = %0
177  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
178  br i1 %C2, label %T, label %F
179T:              ; preds = %N, %0
180  call void @foo1( )
181  ret void
182F:              ; preds = %N
183  call void @foo2( )
184  ret void
185
186}
187
188
189
190define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
191; CHECK-LABEL: @test4(
192; CHECK-NEXT:  entry:
193; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
194; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
195; CHECK-NEXT:    i8 34, label [[LOR_END]]
196; CHECK-NEXT:    i8 92, label [[LOR_END]]
197; CHECK-NEXT:    ]
198; CHECK:       lor.rhs:
199; CHECK-NEXT:    br label [[LOR_END]]
200; CHECK:       lor.end:
201; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
202; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
203; CHECK-NEXT:    ret i32 [[LOR_EXT]]
204;
205entry:
206  %cmp = icmp eq i8 %c, 62
207  br i1 %cmp, label %lor.end, label %lor.lhs.false
208
209lor.lhs.false:                                    ; preds = %entry
210  %cmp4 = icmp eq i8 %c, 34
211  br i1 %cmp4, label %lor.end, label %lor.rhs
212
213lor.rhs:                                          ; preds = %lor.lhs.false
214  %cmp8 = icmp eq i8 %c, 92
215  br label %lor.end
216
217lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
218  %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp8, %lor.rhs ]
219  %lor.ext = zext i1 %0 to i32
220  ret i32 %lor.ext
221
222}
223
224define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
225; CHECK-LABEL: @test5(
226; CHECK-NEXT:  entry:
227; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
228; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
229; CHECK-NEXT:    i8 34, label [[LOR_END]]
230; CHECK-NEXT:    i8 92, label [[LOR_END]]
231; CHECK-NEXT:    ]
232; CHECK:       lor.rhs:
233; CHECK-NEXT:    br label [[LOR_END]]
234; CHECK:       lor.end:
235; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
236; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
237; CHECK-NEXT:    ret i32 [[LOR_EXT]]
238;
239entry:
240  switch i8 %c, label %lor.rhs [
241  i8 62, label %lor.end
242  i8 34, label %lor.end
243  i8 92, label %lor.end
244  ]
245
246lor.rhs:                                          ; preds = %entry
247  %V = icmp eq i8 %c, 92
248  br label %lor.end
249
250lor.end:                                          ; preds = %entry, %entry, %entry, %lor.rhs
251  %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
252  %lor.ext = zext i1 %0 to i32
253  ret i32 %lor.ext
254}
255
256
257define i1 @test6({ i32, i32 }* %I) {
258; CHECK-LABEL: @test6(
259; CHECK-NEXT:  entry:
260; CHECK-NEXT:    [[TMP_1_I:%.*]] = getelementptr { i32, i32 }, { i32, i32 }* [[I:%.*]], i64 0, i32 1
261; CHECK-NEXT:    [[TMP_2_I:%.*]] = load i32, i32* [[TMP_1_I]], align 4
262; CHECK-NEXT:    [[TMP_2_I_OFF:%.*]] = add i32 [[TMP_2_I]], -14
263; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[TMP_2_I_OFF]], 6
264; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
265; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
266;
267entry:
268  %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
269  %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
270  %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
271  br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
272shortcirc_next.0:               ; preds = %entry
273  %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
274  br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
275shortcirc_next.1:               ; preds = %shortcirc_next.0
276  %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
277  br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
278shortcirc_next.2:               ; preds = %shortcirc_next.1
279  %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
280  br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
281shortcirc_next.3:               ; preds = %shortcirc_next.2
282  %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
283  br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
284shortcirc_next.4:               ; preds = %shortcirc_next.3
285  %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
286  br label %UnifiedReturnBlock
287shortcirc_done.4:               ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
288  br label %UnifiedReturnBlock
289UnifiedReturnBlock:             ; preds = %shortcirc_done.4, %shortcirc_next.4
290  %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
291  ret i1 %UnifiedRetVal
292
293}
294
295define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
296; CHECK-LABEL: @test7(
297; CHECK-NEXT:  entry:
298; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
299; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
300; CHECK:       switch.early.test:
301; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
302; CHECK-NEXT:    i8 99, label [[IF_THEN]]
303; CHECK-NEXT:    i8 97, label [[IF_THEN]]
304; CHECK-NEXT:    ]
305; CHECK:       if.then:
306; CHECK-NEXT:    tail call void @foo1() [[ATTR2:#.*]]
307; CHECK-NEXT:    ret void
308; CHECK:       if.end:
309; CHECK-NEXT:    ret void
310;
311entry:
312  %cmp = icmp ult i32 %x, 32
313  %cmp4 = icmp eq i8 %c, 97
314  %or.cond = or i1 %cmp, %cmp4
315  %cmp9 = icmp eq i8 %c, 99
316  %or.cond11 = or i1 %or.cond, %cmp9
317  br i1 %or.cond11, label %if.then, label %if.end
318
319if.then:                                          ; preds = %entry
320  tail call void @foo1() nounwind noredzone
321  ret void
322
323if.end:                                           ; preds = %entry
324  ret void
325
326}
327
328define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
329; CHECK-LABEL: @test8(
330; CHECK-NEXT:  entry:
331; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
332; CHECK:       N:
333; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
334; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
335; CHECK:       switch.early.test:
336; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
337; CHECK-NEXT:    i8 99, label [[IF_THEN]]
338; CHECK-NEXT:    i8 97, label [[IF_THEN]]
339; CHECK-NEXT:    ]
340; CHECK:       if.then:
341; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
342; CHECK-NEXT:    tail call void @foo1() [[ATTR2]]
343; CHECK-NEXT:    ret i32 [[A]]
344; CHECK:       if.end:
345; CHECK-NEXT:    ret i32 0
346;
347entry:
348  br i1 %C, label %N, label %if.then
349N:
350  %cmp = icmp ult i32 %x, 32
351  %cmp4 = icmp eq i8 %c, 97
352  %or.cond = or i1 %cmp, %cmp4
353  %cmp9 = icmp eq i8 %c, 99
354  %or.cond11 = or i1 %or.cond, %cmp9
355  br i1 %or.cond11, label %if.then, label %if.end
356
357if.then:                                          ; preds = %entry
358  %A = phi i32 [0, %entry], [42, %N]
359  tail call void @foo1() nounwind noredzone
360  ret i32 %A
361
362if.end:                                           ; preds = %entry
363  ret i32 0
364
365}
366
367;; This is "Example 7" from http://blog.regehr.org/archives/320
368define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
369; CHECK-LABEL: @test9(
370; CHECK-NEXT:  entry:
371; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
372; CHECK-NEXT:    br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
373; CHECK:       switch.early.test:
374; CHECK-NEXT:    switch i8 [[C]], label [[LOR_RHS:%.*]] [
375; CHECK-NEXT:    i8 92, label [[LOR_END]]
376; CHECK-NEXT:    i8 62, label [[LOR_END]]
377; CHECK-NEXT:    i8 60, label [[LOR_END]]
378; CHECK-NEXT:    i8 59, label [[LOR_END]]
379; CHECK-NEXT:    i8 58, label [[LOR_END]]
380; CHECK-NEXT:    i8 46, label [[LOR_END]]
381; CHECK-NEXT:    i8 44, label [[LOR_END]]
382; CHECK-NEXT:    i8 34, label [[LOR_END]]
383; CHECK-NEXT:    i8 39, label [[LOR_END]]
384; CHECK-NEXT:    ]
385; CHECK:       lor.rhs:
386; CHECK-NEXT:    br label [[LOR_END]]
387; CHECK:       lor.end:
388; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[SWITCH_EARLY_TEST]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY:%.*]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ]
389; CHECK-NEXT:    [[CONV46:%.*]] = zext i1 [[TMP0]] to i32
390; CHECK-NEXT:    ret i32 [[CONV46]]
391;
392entry:
393  %cmp = icmp ult i8 %c, 33
394  br i1 %cmp, label %lor.end, label %lor.lhs.false
395
396lor.lhs.false:                                    ; preds = %entry
397  %cmp4 = icmp eq i8 %c, 46
398  br i1 %cmp4, label %lor.end, label %lor.lhs.false6
399
400lor.lhs.false6:                                   ; preds = %lor.lhs.false
401  %cmp9 = icmp eq i8 %c, 44
402  br i1 %cmp9, label %lor.end, label %lor.lhs.false11
403
404lor.lhs.false11:                                  ; preds = %lor.lhs.false6
405  %cmp14 = icmp eq i8 %c, 58
406  br i1 %cmp14, label %lor.end, label %lor.lhs.false16
407
408lor.lhs.false16:                                  ; preds = %lor.lhs.false11
409  %cmp19 = icmp eq i8 %c, 59
410  br i1 %cmp19, label %lor.end, label %lor.lhs.false21
411
412lor.lhs.false21:                                  ; preds = %lor.lhs.false16
413  %cmp24 = icmp eq i8 %c, 60
414  br i1 %cmp24, label %lor.end, label %lor.lhs.false26
415
416lor.lhs.false26:                                  ; preds = %lor.lhs.false21
417  %cmp29 = icmp eq i8 %c, 62
418  br i1 %cmp29, label %lor.end, label %lor.lhs.false31
419
420lor.lhs.false31:                                  ; preds = %lor.lhs.false26
421  %cmp34 = icmp eq i8 %c, 34
422  br i1 %cmp34, label %lor.end, label %lor.lhs.false36
423
424lor.lhs.false36:                                  ; preds = %lor.lhs.false31
425  %cmp39 = icmp eq i8 %c, 92
426  br i1 %cmp39, label %lor.end, label %lor.rhs
427
428lor.rhs:                                          ; preds = %lor.lhs.false36
429  %cmp43 = icmp eq i8 %c, 39
430  br label %lor.end
431
432lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
433  %0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
434  %conv46 = zext i1 %0 to i32
435  ret i32 %conv46
436
437
438}
439
440define i32 @test10(i32 %mode, i1 %Cond) {
441; CHECK-LABEL: @test10(
442; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
443; CHECK:       switch.early.test:
444; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
445; CHECK-NEXT:    i32 51, label [[F]]
446; CHECK-NEXT:    i32 0, label [[F]]
447; CHECK-NEXT:    ]
448; CHECK:       T:
449; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
450; CHECK-NEXT:    ret i32 [[MERGE]]
451; CHECK:       F:
452; CHECK-NEXT:    br label [[T]]
453;
454  %A = icmp ne i32 %mode, 0
455  %B = icmp ne i32 %mode, 51
456  %C = and i1 %A, %B
457  %D = and i1 %C, %Cond
458  br i1 %D, label %T, label %F
459T:
460  ret i32 123
461F:
462  ret i32 324
463
464}
465
466define i32 @test10_select(i32 %mode, i1 %Cond) {
467; CHECK-LABEL: @test10_select(
468; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
469; CHECK:       switch.early.test:
470; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
471; CHECK-NEXT:    i32 51, label [[F]]
472; CHECK-NEXT:    i32 0, label [[F]]
473; CHECK-NEXT:    ]
474; CHECK:       T:
475; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
476; CHECK-NEXT:    ret i32 [[MERGE]]
477; CHECK:       F:
478; CHECK-NEXT:    br label [[T]]
479;
480  %A = icmp ne i32 %mode, 0
481  %B = icmp ne i32 %mode, 51
482  %C = select i1 %A, i1 %B, i1 false
483  %D = select i1 %C, i1 %Cond, i1 false
484  br i1 %D, label %T, label %F
485T:
486  ret i32 123
487F:
488  ret i32 324
489
490}
491
492; TODO: %Cond doesn't need freeze
493define i32 @test10_select_and(i32 %mode, i1 %Cond) {
494; CHECK-LABEL: @test10_select_and(
495; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
496; CHECK:       switch.early.test:
497; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
498; CHECK-NEXT:    i32 51, label [[F]]
499; CHECK-NEXT:    i32 0, label [[F]]
500; CHECK-NEXT:    ]
501; CHECK:       T:
502; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
503; CHECK-NEXT:    ret i32 [[MERGE]]
504; CHECK:       F:
505; CHECK-NEXT:    br label [[T]]
506;
507  %A = icmp ne i32 %mode, 0
508  %B = icmp ne i32 %mode, 51
509  %C = select i1 %A, i1 %B, i1 false
510  %D = and i1 %C, %Cond
511  br i1 %D, label %T, label %F
512T:
513  ret i32 123
514F:
515  ret i32 324
516
517}
518
519define i32 @test10_select_nofreeze(i32 %mode, i1 noundef %Cond) {
520; CHECK-LABEL: @test10_select_nofreeze(
521; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
522; CHECK:       switch.early.test:
523; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
524; CHECK-NEXT:    i32 51, label [[F]]
525; CHECK-NEXT:    i32 0, label [[F]]
526; CHECK-NEXT:    ]
527; CHECK:       T:
528; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
529; CHECK-NEXT:    ret i32 [[MERGE]]
530; CHECK:       F:
531; CHECK-NEXT:    br label [[T]]
532;
533  %A = icmp ne i32 %mode, 0
534  %B = icmp ne i32 %mode, 51
535  %C = select i1 %A, i1 %B, i1 false
536  %D = select i1 %C, i1 %Cond, i1 false
537  br i1 %D, label %T, label %F
538T:
539  ret i32 123
540F:
541  ret i32 324
542
543}
544
545; PR8780
546define i32 @test11(i32 %bar) nounwind {
547; CHECK-LABEL: @test11(
548; CHECK-NEXT:  entry:
549; CHECK-NEXT:    switch i32 [[BAR:%.*]], label [[IF_END:%.*]] [
550; CHECK-NEXT:    i32 55, label [[RETURN:%.*]]
551; CHECK-NEXT:    i32 53, label [[RETURN]]
552; CHECK-NEXT:    i32 35, label [[RETURN]]
553; CHECK-NEXT:    i32 24, label [[RETURN]]
554; CHECK-NEXT:    i32 23, label [[RETURN]]
555; CHECK-NEXT:    i32 12, label [[RETURN]]
556; CHECK-NEXT:    i32 4, label [[RETURN]]
557; CHECK-NEXT:    ]
558; CHECK:       if.end:
559; CHECK-NEXT:    br label [[RETURN]]
560; CHECK:       return:
561; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ 1, [[ENTRY:%.*]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ]
562; CHECK-NEXT:    ret i32 [[RETVAL_0]]
563;
564entry:
565  %cmp = icmp eq i32 %bar, 4
566  %cmp2 = icmp eq i32 %bar, 35
567  %or.cond = or i1 %cmp, %cmp2
568  %cmp5 = icmp eq i32 %bar, 53
569  %or.cond1 = or i1 %or.cond, %cmp5
570  %cmp8 = icmp eq i32 %bar, 24
571  %or.cond2 = or i1 %or.cond1, %cmp8
572  %cmp11 = icmp eq i32 %bar, 23
573  %or.cond3 = or i1 %or.cond2, %cmp11
574  %cmp14 = icmp eq i32 %bar, 55
575  %or.cond4 = or i1 %or.cond3, %cmp14
576  %cmp17 = icmp eq i32 %bar, 12
577  %or.cond5 = or i1 %or.cond4, %cmp17
578  %cmp20 = icmp eq i32 %bar, 35
579  %or.cond6 = or i1 %or.cond5, %cmp20
580  br i1 %or.cond6, label %if.then, label %if.end
581
582if.then:                                          ; preds = %entry
583  br label %return
584
585if.end:                                           ; preds = %entry
586  br label %return
587
588return:                                           ; preds = %if.end, %if.then
589  %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
590  ret i32 %retval.0
591
592}
593
594define void @test12() nounwind {
595; CHECK-LABEL: @test12(
596; CHECK-NEXT:  entry:
597; CHECK-NEXT:    [[DOTOLD:%.*]] = icmp eq i32 undef, undef
598; CHECK-NEXT:    br i1 [[DOTOLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
599; CHECK:       bb55.us.us:
600; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
601; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
602; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
603; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
604; CHECK:       malformed:
605; CHECK-NEXT:    ret void
606;
607entry:
608  br label %bb49.us.us
609
610bb49.us.us:
611  %A = icmp eq i32 undef, undef
612  br i1 %A, label %bb55.us.us, label %malformed
613
614bb48.us.us:
615  %B = icmp ugt i32 undef, undef
616  br i1 %B, label %bb55.us.us, label %bb49.us.us
617
618bb55.us.us:
619  br label %bb48.us.us
620
621malformed:
622  ret void
623
624}
625
626; test13 - handle switch formation with ult.
627define void @test13(i32 %x) nounwind ssp noredzone {
628; CHECK-LABEL: @test13(
629; CHECK-NEXT:  entry:
630; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
631; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
632; CHECK-NEXT:    i32 4, label [[IF_THEN]]
633; CHECK-NEXT:    i32 3, label [[IF_THEN]]
634; CHECK-NEXT:    i32 1, label [[IF_THEN]]
635; CHECK-NEXT:    i32 0, label [[IF_THEN]]
636; CHECK-NEXT:    ]
637; CHECK:       if.then:
638; CHECK-NEXT:    call void @foo1() [[ATTR3:#.*]]
639; CHECK-NEXT:    br label [[IF_END]]
640; CHECK:       if.end:
641; CHECK-NEXT:    ret void
642;
643entry:
644  %cmp = icmp ult i32 %x, 2
645  br i1 %cmp, label %if.then, label %lor.lhs.false3
646
647lor.lhs.false3:                                   ; preds = %lor.lhs.false
648  %cmp5 = icmp eq i32 %x, 3
649  br i1 %cmp5, label %if.then, label %lor.lhs.false6
650
651lor.lhs.false6:                                   ; preds = %lor.lhs.false3
652  %cmp8 = icmp eq i32 %x, 4
653  br i1 %cmp8, label %if.then, label %lor.lhs.false9
654
655lor.lhs.false9:                                   ; preds = %lor.lhs.false6
656  %cmp11 = icmp eq i32 %x, 6
657  br i1 %cmp11, label %if.then, label %if.end
658
659if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
660  call void @foo1() noredzone
661  br label %if.end
662
663if.end:                                           ; preds = %if.then, %lor.lhs.false9
664  ret void
665}
666
667; test14 - handle switch formation with ult.
668define void @test14(i32 %x) nounwind ssp noredzone {
669; CHECK-LABEL: @test14(
670; CHECK-NEXT:  entry:
671; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
672; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
673; CHECK-NEXT:    i32 4, label [[IF_THEN]]
674; CHECK-NEXT:    i32 3, label [[IF_THEN]]
675; CHECK-NEXT:    i32 2, label [[IF_THEN]]
676; CHECK-NEXT:    i32 1, label [[IF_THEN]]
677; CHECK-NEXT:    i32 0, label [[IF_THEN]]
678; CHECK-NEXT:    ]
679; CHECK:       if.then:
680; CHECK-NEXT:    call void @foo1() [[ATTR3]]
681; CHECK-NEXT:    br label [[IF_END]]
682; CHECK:       if.end:
683; CHECK-NEXT:    ret void
684;
685entry:
686  %cmp = icmp ugt i32 %x, 2
687  br i1 %cmp, label %lor.lhs.false3, label %if.then
688
689lor.lhs.false3:                                   ; preds = %lor.lhs.false
690  %cmp5 = icmp ne i32 %x, 3
691  br i1 %cmp5, label %lor.lhs.false6, label %if.then
692
693lor.lhs.false6:                                   ; preds = %lor.lhs.false3
694  %cmp8 = icmp ne i32 %x, 4
695  br i1 %cmp8, label %lor.lhs.false9, label %if.then
696
697lor.lhs.false9:                                   ; preds = %lor.lhs.false6
698  %cmp11 = icmp ne i32 %x, 6
699  br i1 %cmp11, label %if.end, label %if.then
700
701if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
702  call void @foo1() noredzone
703  br label %if.end
704
705if.end:                                           ; preds = %if.then, %lor.lhs.false9
706  ret void
707}
708
709; Don't crash on ginormous ranges.
710define void @test15(i128 %x) nounwind {
711; CHECK-LABEL: @test15(
712; CHECK-NEXT:  if.end:
713; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i128 [[X:%.*]], 2
714; CHECK-NEXT:    ret void
715;
716  %cmp = icmp ugt i128 %x, 2
717  br i1 %cmp, label %if.end, label %lor.false
718
719lor.false:
720  %cmp2 = icmp ne i128 %x, 100000000000000000000
721  br i1 %cmp2, label %if.end, label %if.then
722
723if.then:
724  call void @foo1() noredzone
725  br label %if.end
726
727if.end:
728  ret void
729
730}
731
732; PR8675
733; rdar://5134905
734define zeroext i1 @test16(i32 %x) nounwind {
735; CHECK-LABEL: @test16(
736; CHECK-NEXT:  entry:
737; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
738; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
739; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
740; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
741;
742entry:
743  %cmp.i = icmp eq i32 %x, 1
744  br i1 %cmp.i, label %lor.end, label %lor.lhs.false
745
746lor.lhs.false:
747  %cmp.i2 = icmp eq i32 %x, 2
748  br i1 %cmp.i2, label %lor.end, label %lor.rhs
749
750lor.rhs:
751  %cmp.i1 = icmp eq i32 %x, 3
752  br label %lor.end
753
754lor.end:
755  %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp.i1, %lor.rhs ]
756  ret i1 %0
757}
758
759; Check that we don't turn an icmp into a switch where it's not useful.
760define void @test17(i32 %x, i32 %y) {
761; CHECK-LABEL: @test17(
762; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
763; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
764; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
765; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
766; CHECK:       lor.lhs.false8:
767; CHECK-NEXT:    tail call void @foo1()
768; CHECK-NEXT:    ret void
769; CHECK:       return:
770; CHECK-NEXT:    ret void
771;
772  %cmp = icmp ult i32 %x, 3
773  %switch = icmp ult i32 %y, 2
774  %or.cond775 = or i1 %cmp, %switch
775  br i1 %or.cond775, label %lor.lhs.false8, label %return
776
777lor.lhs.false8:
778  tail call void @foo1()
779  ret void
780
781return:
782  ret void
783
784}
785
786define void @test17_select(i32 %x, i32 %y) {
787; CHECK-LABEL: @test17_select(
788; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
789; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
790; CHECK-NEXT:    [[OR_COND775:%.*]] = select i1 [[CMP]], i1 true, i1 [[SWITCH]]
791; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
792; CHECK:       lor.lhs.false8:
793; CHECK-NEXT:    tail call void @foo1()
794; CHECK-NEXT:    ret void
795; CHECK:       return:
796; CHECK-NEXT:    ret void
797;
798  %cmp = icmp ult i32 %x, 3
799  %switch = icmp ult i32 %y, 2
800  %or.cond775 = select i1 %cmp, i1 true, i1 %switch
801  br i1 %or.cond775, label %lor.lhs.false8, label %return
802
803lor.lhs.false8:
804  tail call void @foo1()
805  ret void
806
807return:
808  ret void
809
810}
811
812define void @test18(i32 %arg) {
813; CHECK-LABEL: @test18(
814; CHECK-NEXT:  bb:
815; CHECK-NEXT:    [[ARG_OFF:%.*]] = add i32 [[ARG:%.*]], -8
816; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG_OFF]], 11
817; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB19:%.*]], label [[BB20:%.*]]
818; CHECK:       bb19:
819; CHECK-NEXT:    tail call void @foo1()
820; CHECK-NEXT:    br label [[BB20]]
821; CHECK:       bb20:
822; CHECK-NEXT:    ret void
823;
824bb:
825  %tmp = and i32 %arg, -2
826  %tmp1 = icmp eq i32 %tmp, 8
827  %tmp2 = icmp eq i32 %arg, 10
828  %tmp3 = or i1 %tmp1, %tmp2
829  %tmp4 = icmp eq i32 %arg, 11
830  %tmp5 = or i1 %tmp3, %tmp4
831  %tmp6 = icmp eq i32 %arg, 12
832  %tmp7 = or i1 %tmp5, %tmp6
833  br i1 %tmp7, label %bb19, label %bb8
834
835bb8:                                              ; preds = %bb
836  %tmp9 = add i32 %arg, -13
837  %tmp10 = icmp ult i32 %tmp9, 2
838  %tmp11 = icmp eq i32 %arg, 16
839  %tmp12 = or i1 %tmp10, %tmp11
840  %tmp13 = icmp eq i32 %arg, 17
841  %tmp14 = or i1 %tmp12, %tmp13
842  %tmp15 = icmp eq i32 %arg, 18
843  %tmp16 = or i1 %tmp14, %tmp15
844  %tmp17 = icmp eq i32 %arg, 15
845  %tmp18 = or i1 %tmp16, %tmp17
846  br i1 %tmp18, label %bb19, label %bb20
847
848bb19:                                             ; preds = %bb8, %bb
849  tail call void @foo1()
850  br label %bb20
851
852bb20:                                             ; preds = %bb19, %bb8
853  ret void
854
855}
856
857define void @PR26323(i1 %tobool23, i32 %tmp3) {
858; CHECK-LABEL: @PR26323(
859; CHECK-NEXT:  entry:
860; CHECK-NEXT:    [[TOBOOL5:%.*]] = icmp ne i32 [[TMP3:%.*]], 0
861; CHECK-NEXT:    [[NEG14:%.*]] = and i32 [[TMP3]], -2
862; CHECK-NEXT:    [[CMP17:%.*]] = icmp ne i32 [[NEG14]], -1
863; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[TOBOOL5]], [[TOBOOL23:%.*]]
864; CHECK-NEXT:    [[OR_COND1:%.*]] = and i1 [[CMP17]], [[OR_COND]]
865; CHECK-NEXT:    br i1 [[OR_COND1]], label [[IF_END29:%.*]], label [[IF_THEN27:%.*]]
866; CHECK:       if.then27:
867; CHECK-NEXT:    call void @foo1()
868; CHECK-NEXT:    unreachable
869; CHECK:       if.end29:
870; CHECK-NEXT:    ret void
871;
872entry:
873  %tobool5 = icmp ne i32 %tmp3, 0
874  %neg14 = and i32 %tmp3, -2
875  %cmp17 = icmp ne i32 %neg14, -1
876  %or.cond = and i1 %tobool5, %tobool23
877  %or.cond1 = and i1 %cmp17, %or.cond
878  br i1 %or.cond1, label %if.end29, label %if.then27
879
880if.then27:                                        ; preds = %entry
881  call void @foo1()
882  unreachable
883
884if.end29:                                         ; preds = %entry
885  ret void
886}
887
888; Form a switch when and'ing a negated power of two
889define void @test19(i32 %arg) {
890; CHECK-LABEL: @test19(
891; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
892; CHECK-NEXT:    i32 32, label [[IF:%.*]]
893; CHECK-NEXT:    i32 13, label [[IF]]
894; CHECK-NEXT:    i32 12, label [[IF]]
895; CHECK-NEXT:    ]
896; CHECK:       if:
897; CHECK-NEXT:    call void @foo1()
898; CHECK-NEXT:    ret void
899; CHECK:       else:
900; CHECK-NEXT:    ret void
901;
902  %and = and i32 %arg, -2
903  %cmp1 = icmp eq i32 %and, 12
904  %cmp2 = icmp eq i32 %arg, 32
905  %pred = or i1 %cmp1, %cmp2
906  br i1 %pred, label %if, label %else
907
908if:
909  call void @foo1()
910  ret void
911
912else:
913  ret void
914}
915
916define void @test19_select(i32 %arg) {
917; CHECK-LABEL: @test19_select(
918; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
919; CHECK-NEXT:    i32 32, label [[IF:%.*]]
920; CHECK-NEXT:    i32 13, label [[IF]]
921; CHECK-NEXT:    i32 12, label [[IF]]
922; CHECK-NEXT:    ]
923; CHECK:       if:
924; CHECK-NEXT:    call void @foo1()
925; CHECK-NEXT:    ret void
926; CHECK:       else:
927; CHECK-NEXT:    ret void
928;
929  %and = and i32 %arg, -2
930  %cmp1 = icmp eq i32 %and, 12
931  %cmp2 = icmp eq i32 %arg, 32
932  %pred = select i1 %cmp1, i1 true, i1 %cmp2
933  br i1 %pred, label %if, label %else
934
935if:
936  call void @foo1()
937  ret void
938
939else:
940  ret void
941}
942
943; Since %cmp1 is always false, a switch is never formed
944define void @test20(i32 %arg) {
945; CHECK-LABEL: @test20(
946; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
947; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
948; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
949; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
950; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
951; CHECK:       if:
952; CHECK-NEXT:    call void @foo1()
953; CHECK-NEXT:    ret void
954; CHECK:       else:
955; CHECK-NEXT:    ret void
956;
957  %and = and i32 %arg, -2
958  %cmp1 = icmp eq i32 %and, 13
959  %cmp2 = icmp eq i32 %arg, 32
960  %pred = or i1 %cmp1, %cmp2
961  br i1 %pred, label %if, label %else
962
963if:
964  call void @foo1()
965  ret void
966
967else:
968  ret void
969}
970
971; Form a switch when or'ing a power of two
972define void @test21(i32 %arg) {
973; CHECK-LABEL: @test21(
974; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
975; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
976; CHECK-NEXT:    i32 13, label [[ELSE]]
977; CHECK-NEXT:    i32 12, label [[ELSE]]
978; CHECK-NEXT:    ]
979; CHECK:       if:
980; CHECK-NEXT:    call void @foo1()
981; CHECK-NEXT:    ret void
982; CHECK:       else:
983; CHECK-NEXT:    ret void
984;
985  %and = or i32 %arg, 1
986  %cmp1 = icmp ne i32 %and, 13
987  %cmp2 = icmp ne i32 %arg, 32
988  %pred = and i1 %cmp1, %cmp2
989  br i1 %pred, label %if, label %else
990
991if:
992  call void @foo1()
993  ret void
994
995else:
996  ret void
997}
998
999; Since %cmp1 is always false, a switch is never formed
1000define void @test22(i32 %arg) {
1001; CHECK-LABEL: @test22(
1002; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
1003; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
1004; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
1005; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
1006; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
1007; CHECK:       if:
1008; CHECK-NEXT:    call void @foo1()
1009; CHECK-NEXT:    ret void
1010; CHECK:       else:
1011; CHECK-NEXT:    ret void
1012;
1013  %and = or i32 %arg, 1
1014  %cmp1 = icmp ne i32 %and, 12
1015  %cmp2 = icmp ne i32 %arg, 32
1016  %pred = and i1 %cmp1, %cmp2
1017  br i1 %pred, label %if, label %else
1018
1019if:
1020  call void @foo1()
1021  ret void
1022
1023else:
1024  ret void
1025}
1026