1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s 3; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s 4 5declare void @foo1() 6 7declare void @foo2() 8 9define void @test1(i32 %V) { 10; CHECK-LABEL: @test1( 11; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ 12; CHECK-NEXT: i32 17, label [[T:%.*]] 13; CHECK-NEXT: i32 4, label [[T]] 14; CHECK-NEXT: ] 15; CHECK: T: 16; CHECK-NEXT: call void @foo1() 17; CHECK-NEXT: ret void 18; CHECK: F: 19; CHECK-NEXT: call void @foo2() 20; CHECK-NEXT: ret void 21; 22 %C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1] 23 %C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1] 24 %CN = or i1 %C1, %C2 ; <i1> [#uses=1] 25 br i1 %CN, label %T, label %F 26T: ; preds = %0 27 call void @foo1( ) 28 ret void 29F: ; preds = %0 30 call void @foo2( ) 31 ret void 32} 33 34define void @test1_select(i32 %V) { 35; CHECK-LABEL: @test1_select( 36; CHECK-NEXT: [[C1:%.*]] = icmp eq i32 [[V:%.*]], 4 37; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[V]], 17 38; CHECK-NEXT: [[CN:%.*]] = select i1 [[C1]], i1 true, i1 [[C2]] 39; CHECK-NEXT: br i1 [[CN]], label [[T:%.*]], label [[F:%.*]] 40; CHECK: T: 41; CHECK-NEXT: call void @foo1() 42; CHECK-NEXT: ret void 43; CHECK: F: 44; CHECK-NEXT: call void @foo2() 45; CHECK-NEXT: ret void 46; 47 %C1 = icmp eq i32 %V, 4 48 %C2 = icmp eq i32 %V, 17 49 %CN = select i1 %C1, i1 true, i1 %C2 50 br i1 %CN, label %T, label %F 51T: 52 call void @foo1( ) 53 ret void 54F: 55 call void @foo2( ) 56 ret void 57} 58 59define void @test1_ptr(i32* %V) { 60; DL-LABEL: @test1_ptr( 61; DL-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32 62; DL-NEXT: switch i32 [[MAGICPTR]], label [[F:%.*]] [ 63; DL-NEXT: i32 17, label [[T:%.*]] 64; DL-NEXT: i32 4, label [[T]] 65; DL-NEXT: ] 66; DL: T: 67; DL-NEXT: call void @foo1() 68; DL-NEXT: ret void 69; DL: F: 70; DL-NEXT: call void @foo2() 71; DL-NEXT: ret void 72; 73 %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*) 74 %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*) 75 %CN = or i1 %C1, %C2 ; <i1> [#uses=1] 76 br i1 %CN, label %T, label %F 77T: ; preds = %0 78 call void @foo1( ) 79 ret void 80F: ; preds = %0 81 call void @foo2( ) 82 ret void 83} 84 85define void @test1_ptr_as1(i32 addrspace(1)* %V) { 86; DL-LABEL: @test1_ptr_as1( 87; DL-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16 88; DL-NEXT: switch i16 [[MAGICPTR]], label [[F:%.*]] [ 89; DL-NEXT: i16 17, label [[T:%.*]] 90; DL-NEXT: i16 4, label [[T]] 91; DL-NEXT: ] 92; DL: T: 93; DL-NEXT: call void @foo1() 94; DL-NEXT: ret void 95; DL: F: 96; DL-NEXT: call void @foo2() 97; DL-NEXT: ret void 98; 99 %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*) 100 %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*) 101 %CN = or i1 %C1, %C2 ; <i1> [#uses=1] 102 br i1 %CN, label %T, label %F 103T: ; preds = %0 104 call void @foo1( ) 105 ret void 106F: ; preds = %0 107 call void @foo2( ) 108 ret void 109} 110 111define void @test2(i32 %V) { 112; CHECK-LABEL: @test2( 113; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [ 114; CHECK-NEXT: i32 17, label [[F:%.*]] 115; CHECK-NEXT: i32 4, label [[F]] 116; CHECK-NEXT: ] 117; CHECK: T: 118; CHECK-NEXT: call void @foo1() 119; CHECK-NEXT: ret void 120; CHECK: F: 121; CHECK-NEXT: call void @foo2() 122; CHECK-NEXT: ret void 123; 124 %C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1] 125 %C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1] 126 %CN = and i1 %C1, %C2 ; <i1> [#uses=1] 127 br i1 %CN, label %T, label %F 128T: ; preds = %0 129 call void @foo1( ) 130 ret void 131F: ; preds = %0 132 call void @foo2( ) 133 ret void 134} 135 136define void @test2_select(i32 %V) { 137; CHECK-LABEL: @test2_select( 138; CHECK-NEXT: [[C1:%.*]] = icmp ne i32 [[V:%.*]], 4 139; CHECK-NEXT: [[C2:%.*]] = icmp ne i32 [[V]], 17 140; CHECK-NEXT: [[CN:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false 141; CHECK-NEXT: br i1 [[CN]], label [[T:%.*]], label [[F:%.*]] 142; CHECK: T: 143; CHECK-NEXT: call void @foo1() 144; CHECK-NEXT: ret void 145; CHECK: F: 146; CHECK-NEXT: call void @foo2() 147; CHECK-NEXT: ret void 148; 149 %C1 = icmp ne i32 %V, 4 150 %C2 = icmp ne i32 %V, 17 151 %CN = select i1 %C1, i1 %C2, i1 false 152 br i1 %CN, label %T, label %F 153T: 154 call void @foo1( ) 155 ret void 156F: 157 call void @foo2( ) 158 ret void 159} 160 161define void @test3(i32 %V) { 162; CHECK-LABEL: @test3( 163; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ 164; CHECK-NEXT: i32 4, label [[T:%.*]] 165; CHECK-NEXT: i32 17, label [[T]] 166; CHECK-NEXT: ] 167; CHECK: T: 168; CHECK-NEXT: call void @foo1() 169; CHECK-NEXT: ret void 170; CHECK: F: 171; CHECK-NEXT: call void @foo2() 172; CHECK-NEXT: ret void 173; 174 %C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1] 175 br i1 %C1, label %T, label %N 176N: ; preds = %0 177 %C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1] 178 br i1 %C2, label %T, label %F 179T: ; preds = %N, %0 180 call void @foo1( ) 181 ret void 182F: ; preds = %N 183 call void @foo2( ) 184 ret void 185 186} 187 188 189 190define i32 @test4(i8 zeroext %c) nounwind ssp noredzone { 191; CHECK-LABEL: @test4( 192; CHECK-NEXT: entry: 193; CHECK-NEXT: switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [ 194; CHECK-NEXT: i8 62, label [[LOR_END:%.*]] 195; CHECK-NEXT: i8 34, label [[LOR_END]] 196; CHECK-NEXT: i8 92, label [[LOR_END]] 197; CHECK-NEXT: ] 198; CHECK: lor.rhs: 199; CHECK-NEXT: br label [[LOR_END]] 200; CHECK: lor.end: 201; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ] 202; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32 203; CHECK-NEXT: ret i32 [[LOR_EXT]] 204; 205entry: 206 %cmp = icmp eq i8 %c, 62 207 br i1 %cmp, label %lor.end, label %lor.lhs.false 208 209lor.lhs.false: ; preds = %entry 210 %cmp4 = icmp eq i8 %c, 34 211 br i1 %cmp4, label %lor.end, label %lor.rhs 212 213lor.rhs: ; preds = %lor.lhs.false 214 %cmp8 = icmp eq i8 %c, 92 215 br label %lor.end 216 217lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry 218 %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp8, %lor.rhs ] 219 %lor.ext = zext i1 %0 to i32 220 ret i32 %lor.ext 221 222} 223 224define i32 @test5(i8 zeroext %c) nounwind ssp noredzone { 225; CHECK-LABEL: @test5( 226; CHECK-NEXT: entry: 227; CHECK-NEXT: switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [ 228; CHECK-NEXT: i8 62, label [[LOR_END:%.*]] 229; CHECK-NEXT: i8 34, label [[LOR_END]] 230; CHECK-NEXT: i8 92, label [[LOR_END]] 231; CHECK-NEXT: ] 232; CHECK: lor.rhs: 233; CHECK-NEXT: br label [[LOR_END]] 234; CHECK: lor.end: 235; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ] 236; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32 237; CHECK-NEXT: ret i32 [[LOR_EXT]] 238; 239entry: 240 switch i8 %c, label %lor.rhs [ 241 i8 62, label %lor.end 242 i8 34, label %lor.end 243 i8 92, label %lor.end 244 ] 245 246lor.rhs: ; preds = %entry 247 %V = icmp eq i8 %c, 92 248 br label %lor.end 249 250lor.end: ; preds = %entry, %entry, %entry, %lor.rhs 251 %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ] 252 %lor.ext = zext i1 %0 to i32 253 ret i32 %lor.ext 254} 255 256 257define i1 @test6({ i32, i32 }* %I) { 258; CHECK-LABEL: @test6( 259; CHECK-NEXT: entry: 260; CHECK-NEXT: [[TMP_1_I:%.*]] = getelementptr { i32, i32 }, { i32, i32 }* [[I:%.*]], i64 0, i32 1 261; CHECK-NEXT: [[TMP_2_I:%.*]] = load i32, i32* [[TMP_1_I]], align 4 262; CHECK-NEXT: [[TMP_2_I_OFF:%.*]] = add i32 [[TMP_2_I]], -14 263; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[TMP_2_I_OFF]], 6 264; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false 265; CHECK-NEXT: ret i1 [[SPEC_SELECT]] 266; 267entry: 268 %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1 ; <i32*> [#uses=1] 269 %tmp.2.i = load i32, i32* %tmp.1.i ; <i32> [#uses=6] 270 %tmp.2 = icmp eq i32 %tmp.2.i, 14 ; <i1> [#uses=1] 271 br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0 272shortcirc_next.0: ; preds = %entry 273 %tmp.6 = icmp eq i32 %tmp.2.i, 15 ; <i1> [#uses=1] 274 br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1 275shortcirc_next.1: ; preds = %shortcirc_next.0 276 %tmp.11 = icmp eq i32 %tmp.2.i, 16 ; <i1> [#uses=1] 277 br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2 278shortcirc_next.2: ; preds = %shortcirc_next.1 279 %tmp.16 = icmp eq i32 %tmp.2.i, 17 ; <i1> [#uses=1] 280 br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3 281shortcirc_next.3: ; preds = %shortcirc_next.2 282 %tmp.21 = icmp eq i32 %tmp.2.i, 18 ; <i1> [#uses=1] 283 br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4 284shortcirc_next.4: ; preds = %shortcirc_next.3 285 %tmp.26 = icmp eq i32 %tmp.2.i, 19 ; <i1> [#uses=1] 286 br label %UnifiedReturnBlock 287shortcirc_done.4: ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry 288 br label %UnifiedReturnBlock 289UnifiedReturnBlock: ; preds = %shortcirc_done.4, %shortcirc_next.4 290 %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ] ; <i1> [#uses=1] 291 ret i1 %UnifiedRetVal 292 293} 294 295define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone { 296; CHECK-LABEL: @test7( 297; CHECK-NEXT: entry: 298; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32 299; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]] 300; CHECK: switch.early.test: 301; CHECK-NEXT: switch i8 [[C:%.*]], label [[IF_END:%.*]] [ 302; CHECK-NEXT: i8 99, label [[IF_THEN]] 303; CHECK-NEXT: i8 97, label [[IF_THEN]] 304; CHECK-NEXT: ] 305; CHECK: if.then: 306; CHECK-NEXT: tail call void @foo1() [[ATTR2:#.*]] 307; CHECK-NEXT: ret void 308; CHECK: if.end: 309; CHECK-NEXT: ret void 310; 311entry: 312 %cmp = icmp ult i32 %x, 32 313 %cmp4 = icmp eq i8 %c, 97 314 %or.cond = or i1 %cmp, %cmp4 315 %cmp9 = icmp eq i8 %c, 99 316 %or.cond11 = or i1 %or.cond, %cmp9 317 br i1 %or.cond11, label %if.then, label %if.end 318 319if.then: ; preds = %entry 320 tail call void @foo1() nounwind noredzone 321 ret void 322 323if.end: ; preds = %entry 324 ret void 325 326} 327 328define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone { 329; CHECK-LABEL: @test8( 330; CHECK-NEXT: entry: 331; CHECK-NEXT: br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]] 332; CHECK: N: 333; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32 334; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]] 335; CHECK: switch.early.test: 336; CHECK-NEXT: switch i8 [[C:%.*]], label [[IF_END:%.*]] [ 337; CHECK-NEXT: i8 99, label [[IF_THEN]] 338; CHECK-NEXT: i8 97, label [[IF_THEN]] 339; CHECK-NEXT: ] 340; CHECK: if.then: 341; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ] 342; CHECK-NEXT: tail call void @foo1() [[ATTR2]] 343; CHECK-NEXT: ret i32 [[A]] 344; CHECK: if.end: 345; CHECK-NEXT: ret i32 0 346; 347entry: 348 br i1 %C, label %N, label %if.then 349N: 350 %cmp = icmp ult i32 %x, 32 351 %cmp4 = icmp eq i8 %c, 97 352 %or.cond = or i1 %cmp, %cmp4 353 %cmp9 = icmp eq i8 %c, 99 354 %or.cond11 = or i1 %or.cond, %cmp9 355 br i1 %or.cond11, label %if.then, label %if.end 356 357if.then: ; preds = %entry 358 %A = phi i32 [0, %entry], [42, %N] 359 tail call void @foo1() nounwind noredzone 360 ret i32 %A 361 362if.end: ; preds = %entry 363 ret i32 0 364 365} 366 367;; This is "Example 7" from http://blog.regehr.org/archives/320 368define i32 @test9(i8 zeroext %c) nounwind ssp noredzone { 369; CHECK-LABEL: @test9( 370; CHECK-NEXT: entry: 371; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33 372; CHECK-NEXT: br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]] 373; CHECK: switch.early.test: 374; CHECK-NEXT: switch i8 [[C]], label [[LOR_RHS:%.*]] [ 375; CHECK-NEXT: i8 92, label [[LOR_END]] 376; CHECK-NEXT: i8 62, label [[LOR_END]] 377; CHECK-NEXT: i8 60, label [[LOR_END]] 378; CHECK-NEXT: i8 59, label [[LOR_END]] 379; CHECK-NEXT: i8 58, label [[LOR_END]] 380; CHECK-NEXT: i8 46, label [[LOR_END]] 381; CHECK-NEXT: i8 44, label [[LOR_END]] 382; CHECK-NEXT: i8 34, label [[LOR_END]] 383; CHECK-NEXT: i8 39, label [[LOR_END]] 384; CHECK-NEXT: ] 385; CHECK: lor.rhs: 386; CHECK-NEXT: br label [[LOR_END]] 387; CHECK: lor.end: 388; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ true, [[SWITCH_EARLY_TEST]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY:%.*]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ] 389; CHECK-NEXT: [[CONV46:%.*]] = zext i1 [[TMP0]] to i32 390; CHECK-NEXT: ret i32 [[CONV46]] 391; 392entry: 393 %cmp = icmp ult i8 %c, 33 394 br i1 %cmp, label %lor.end, label %lor.lhs.false 395 396lor.lhs.false: ; preds = %entry 397 %cmp4 = icmp eq i8 %c, 46 398 br i1 %cmp4, label %lor.end, label %lor.lhs.false6 399 400lor.lhs.false6: ; preds = %lor.lhs.false 401 %cmp9 = icmp eq i8 %c, 44 402 br i1 %cmp9, label %lor.end, label %lor.lhs.false11 403 404lor.lhs.false11: ; preds = %lor.lhs.false6 405 %cmp14 = icmp eq i8 %c, 58 406 br i1 %cmp14, label %lor.end, label %lor.lhs.false16 407 408lor.lhs.false16: ; preds = %lor.lhs.false11 409 %cmp19 = icmp eq i8 %c, 59 410 br i1 %cmp19, label %lor.end, label %lor.lhs.false21 411 412lor.lhs.false21: ; preds = %lor.lhs.false16 413 %cmp24 = icmp eq i8 %c, 60 414 br i1 %cmp24, label %lor.end, label %lor.lhs.false26 415 416lor.lhs.false26: ; preds = %lor.lhs.false21 417 %cmp29 = icmp eq i8 %c, 62 418 br i1 %cmp29, label %lor.end, label %lor.lhs.false31 419 420lor.lhs.false31: ; preds = %lor.lhs.false26 421 %cmp34 = icmp eq i8 %c, 34 422 br i1 %cmp34, label %lor.end, label %lor.lhs.false36 423 424lor.lhs.false36: ; preds = %lor.lhs.false31 425 %cmp39 = icmp eq i8 %c, 92 426 br i1 %cmp39, label %lor.end, label %lor.rhs 427 428lor.rhs: ; preds = %lor.lhs.false36 429 %cmp43 = icmp eq i8 %c, 39 430 br label %lor.end 431 432lor.end: ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry 433 %0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ] 434 %conv46 = zext i1 %0 to i32 435 ret i32 %conv46 436 437 438} 439 440define i32 @test10(i32 %mode, i1 %Cond) { 441; CHECK-LABEL: @test10( 442; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]] 443; CHECK: switch.early.test: 444; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [ 445; CHECK-NEXT: i32 51, label [[F]] 446; CHECK-NEXT: i32 0, label [[F]] 447; CHECK-NEXT: ] 448; CHECK: T: 449; CHECK-NEXT: [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ] 450; CHECK-NEXT: ret i32 [[MERGE]] 451; CHECK: F: 452; CHECK-NEXT: br label [[T]] 453; 454 %A = icmp ne i32 %mode, 0 455 %B = icmp ne i32 %mode, 51 456 %C = and i1 %A, %B 457 %D = and i1 %C, %Cond 458 br i1 %D, label %T, label %F 459T: 460 ret i32 123 461F: 462 ret i32 324 463 464} 465 466define i32 @test10_select(i32 %mode, i1 %Cond) { 467; CHECK-LABEL: @test10_select( 468; CHECK-NEXT: T: 469; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[MODE:%.*]], 0 470; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[MODE]], 51 471; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false 472; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i1 [[COND:%.*]], i1 false 473; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[D]], i32 123, i32 324 474; CHECK-NEXT: ret i32 [[SPEC_SELECT]] 475; 476 %A = icmp ne i32 %mode, 0 477 %B = icmp ne i32 %mode, 51 478 %C = select i1 %A, i1 %B, i1 false 479 %D = select i1 %C, i1 %Cond, i1 false 480 br i1 %D, label %T, label %F 481T: 482 ret i32 123 483F: 484 ret i32 324 485 486} 487 488; TODO: %Cond doesn't need freeze 489define i32 @test10_select_and(i32 %mode, i1 %Cond) { 490; CHECK-LABEL: @test10_select_and( 491; CHECK-NEXT: T: 492; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[MODE:%.*]], 0 493; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[MODE]], 51 494; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false 495; CHECK-NEXT: [[D:%.*]] = and i1 [[C]], [[COND:%.*]] 496; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[D]], i32 123, i32 324 497; CHECK-NEXT: ret i32 [[SPEC_SELECT]] 498; 499 %A = icmp ne i32 %mode, 0 500 %B = icmp ne i32 %mode, 51 501 %C = select i1 %A, i1 %B, i1 false 502 %D = and i1 %C, %Cond 503 br i1 %D, label %T, label %F 504T: 505 ret i32 123 506F: 507 ret i32 324 508 509} 510 511define i32 @test10_select_nofreeze(i32 %mode, i1 noundef %Cond) { 512; CHECK-LABEL: @test10_select_nofreeze( 513; CHECK-NEXT: T: 514; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[MODE:%.*]], 0 515; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[MODE]], 51 516; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false 517; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i1 [[COND:%.*]], i1 false 518; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[D]], i32 123, i32 324 519; CHECK-NEXT: ret i32 [[SPEC_SELECT]] 520; 521 %A = icmp ne i32 %mode, 0 522 %B = icmp ne i32 %mode, 51 523 %C = select i1 %A, i1 %B, i1 false 524 %D = select i1 %C, i1 %Cond, i1 false 525 br i1 %D, label %T, label %F 526T: 527 ret i32 123 528F: 529 ret i32 324 530 531} 532 533; PR8780 534define i32 @test11(i32 %bar) nounwind { 535; CHECK-LABEL: @test11( 536; CHECK-NEXT: entry: 537; CHECK-NEXT: switch i32 [[BAR:%.*]], label [[IF_END:%.*]] [ 538; CHECK-NEXT: i32 55, label [[RETURN:%.*]] 539; CHECK-NEXT: i32 53, label [[RETURN]] 540; CHECK-NEXT: i32 35, label [[RETURN]] 541; CHECK-NEXT: i32 24, label [[RETURN]] 542; CHECK-NEXT: i32 23, label [[RETURN]] 543; CHECK-NEXT: i32 12, label [[RETURN]] 544; CHECK-NEXT: i32 4, label [[RETURN]] 545; CHECK-NEXT: ] 546; CHECK: if.end: 547; CHECK-NEXT: br label [[RETURN]] 548; CHECK: return: 549; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ 1, [[ENTRY:%.*]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ] 550; CHECK-NEXT: ret i32 [[RETVAL_0]] 551; 552entry: 553 %cmp = icmp eq i32 %bar, 4 554 %cmp2 = icmp eq i32 %bar, 35 555 %or.cond = or i1 %cmp, %cmp2 556 %cmp5 = icmp eq i32 %bar, 53 557 %or.cond1 = or i1 %or.cond, %cmp5 558 %cmp8 = icmp eq i32 %bar, 24 559 %or.cond2 = or i1 %or.cond1, %cmp8 560 %cmp11 = icmp eq i32 %bar, 23 561 %or.cond3 = or i1 %or.cond2, %cmp11 562 %cmp14 = icmp eq i32 %bar, 55 563 %or.cond4 = or i1 %or.cond3, %cmp14 564 %cmp17 = icmp eq i32 %bar, 12 565 %or.cond5 = or i1 %or.cond4, %cmp17 566 %cmp20 = icmp eq i32 %bar, 35 567 %or.cond6 = or i1 %or.cond5, %cmp20 568 br i1 %or.cond6, label %if.then, label %if.end 569 570if.then: ; preds = %entry 571 br label %return 572 573if.end: ; preds = %entry 574 br label %return 575 576return: ; preds = %if.end, %if.then 577 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ] 578 ret i32 %retval.0 579 580} 581 582define void @test12() nounwind { 583; CHECK-LABEL: @test12( 584; CHECK-NEXT: entry: 585; CHECK-NEXT: [[DOTOLD:%.*]] = icmp eq i32 undef, undef 586; CHECK-NEXT: br i1 [[DOTOLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]] 587; CHECK: bb55.us.us: 588; CHECK-NEXT: [[B:%.*]] = icmp ugt i32 undef, undef 589; CHECK-NEXT: [[A:%.*]] = icmp eq i32 undef, undef 590; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[B]], [[A]] 591; CHECK-NEXT: br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]] 592; CHECK: malformed: 593; CHECK-NEXT: ret void 594; 595entry: 596 br label %bb49.us.us 597 598bb49.us.us: 599 %A = icmp eq i32 undef, undef 600 br i1 %A, label %bb55.us.us, label %malformed 601 602bb48.us.us: 603 %B = icmp ugt i32 undef, undef 604 br i1 %B, label %bb55.us.us, label %bb49.us.us 605 606bb55.us.us: 607 br label %bb48.us.us 608 609malformed: 610 ret void 611 612} 613 614; test13 - handle switch formation with ult. 615define void @test13(i32 %x) nounwind ssp noredzone { 616; CHECK-LABEL: @test13( 617; CHECK-NEXT: entry: 618; CHECK-NEXT: switch i32 [[X:%.*]], label [[IF_END:%.*]] [ 619; CHECK-NEXT: i32 6, label [[IF_THEN:%.*]] 620; CHECK-NEXT: i32 4, label [[IF_THEN]] 621; CHECK-NEXT: i32 3, label [[IF_THEN]] 622; CHECK-NEXT: i32 1, label [[IF_THEN]] 623; CHECK-NEXT: i32 0, label [[IF_THEN]] 624; CHECK-NEXT: ] 625; CHECK: if.then: 626; CHECK-NEXT: call void @foo1() [[ATTR3:#.*]] 627; CHECK-NEXT: br label [[IF_END]] 628; CHECK: if.end: 629; CHECK-NEXT: ret void 630; 631entry: 632 %cmp = icmp ult i32 %x, 2 633 br i1 %cmp, label %if.then, label %lor.lhs.false3 634 635lor.lhs.false3: ; preds = %lor.lhs.false 636 %cmp5 = icmp eq i32 %x, 3 637 br i1 %cmp5, label %if.then, label %lor.lhs.false6 638 639lor.lhs.false6: ; preds = %lor.lhs.false3 640 %cmp8 = icmp eq i32 %x, 4 641 br i1 %cmp8, label %if.then, label %lor.lhs.false9 642 643lor.lhs.false9: ; preds = %lor.lhs.false6 644 %cmp11 = icmp eq i32 %x, 6 645 br i1 %cmp11, label %if.then, label %if.end 646 647if.then: ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry 648 call void @foo1() noredzone 649 br label %if.end 650 651if.end: ; preds = %if.then, %lor.lhs.false9 652 ret void 653} 654 655; test14 - handle switch formation with ult. 656define void @test14(i32 %x) nounwind ssp noredzone { 657; CHECK-LABEL: @test14( 658; CHECK-NEXT: entry: 659; CHECK-NEXT: switch i32 [[X:%.*]], label [[IF_END:%.*]] [ 660; CHECK-NEXT: i32 6, label [[IF_THEN:%.*]] 661; CHECK-NEXT: i32 4, label [[IF_THEN]] 662; CHECK-NEXT: i32 3, label [[IF_THEN]] 663; CHECK-NEXT: i32 2, label [[IF_THEN]] 664; CHECK-NEXT: i32 1, label [[IF_THEN]] 665; CHECK-NEXT: i32 0, label [[IF_THEN]] 666; CHECK-NEXT: ] 667; CHECK: if.then: 668; CHECK-NEXT: call void @foo1() [[ATTR3]] 669; CHECK-NEXT: br label [[IF_END]] 670; CHECK: if.end: 671; CHECK-NEXT: ret void 672; 673entry: 674 %cmp = icmp ugt i32 %x, 2 675 br i1 %cmp, label %lor.lhs.false3, label %if.then 676 677lor.lhs.false3: ; preds = %lor.lhs.false 678 %cmp5 = icmp ne i32 %x, 3 679 br i1 %cmp5, label %lor.lhs.false6, label %if.then 680 681lor.lhs.false6: ; preds = %lor.lhs.false3 682 %cmp8 = icmp ne i32 %x, 4 683 br i1 %cmp8, label %lor.lhs.false9, label %if.then 684 685lor.lhs.false9: ; preds = %lor.lhs.false6 686 %cmp11 = icmp ne i32 %x, 6 687 br i1 %cmp11, label %if.end, label %if.then 688 689if.then: ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry 690 call void @foo1() noredzone 691 br label %if.end 692 693if.end: ; preds = %if.then, %lor.lhs.false9 694 ret void 695} 696 697; Don't crash on ginormous ranges. 698define void @test15(i128 %x) nounwind { 699; CHECK-LABEL: @test15( 700; CHECK-NEXT: if.end: 701; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i128 [[X:%.*]], 2 702; CHECK-NEXT: ret void 703; 704 %cmp = icmp ugt i128 %x, 2 705 br i1 %cmp, label %if.end, label %lor.false 706 707lor.false: 708 %cmp2 = icmp ne i128 %x, 100000000000000000000 709 br i1 %cmp2, label %if.end, label %if.then 710 711if.then: 712 call void @foo1() noredzone 713 br label %if.end 714 715if.end: 716 ret void 717 718} 719 720; PR8675 721; rdar://5134905 722define zeroext i1 @test16(i32 %x) nounwind { 723; CHECK-LABEL: @test16( 724; CHECK-NEXT: entry: 725; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -1 726; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3 727; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false 728; CHECK-NEXT: ret i1 [[SPEC_SELECT]] 729; 730entry: 731 %cmp.i = icmp eq i32 %x, 1 732 br i1 %cmp.i, label %lor.end, label %lor.lhs.false 733 734lor.lhs.false: 735 %cmp.i2 = icmp eq i32 %x, 2 736 br i1 %cmp.i2, label %lor.end, label %lor.rhs 737 738lor.rhs: 739 %cmp.i1 = icmp eq i32 %x, 3 740 br label %lor.end 741 742lor.end: 743 %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp.i1, %lor.rhs ] 744 ret i1 %0 745} 746 747; Check that we don't turn an icmp into a switch where it's not useful. 748define void @test17(i32 %x, i32 %y) { 749; CHECK-LABEL: @test17( 750; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3 751; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2 752; CHECK-NEXT: [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]] 753; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]] 754; CHECK: lor.lhs.false8: 755; CHECK-NEXT: tail call void @foo1() 756; CHECK-NEXT: ret void 757; CHECK: return: 758; CHECK-NEXT: ret void 759; 760 %cmp = icmp ult i32 %x, 3 761 %switch = icmp ult i32 %y, 2 762 %or.cond775 = or i1 %cmp, %switch 763 br i1 %or.cond775, label %lor.lhs.false8, label %return 764 765lor.lhs.false8: 766 tail call void @foo1() 767 ret void 768 769return: 770 ret void 771 772} 773 774define void @test17_select(i32 %x, i32 %y) { 775; CHECK-LABEL: @test17_select( 776; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3 777; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2 778; CHECK-NEXT: [[OR_COND775:%.*]] = select i1 [[CMP]], i1 true, i1 [[SWITCH]] 779; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]] 780; CHECK: lor.lhs.false8: 781; CHECK-NEXT: tail call void @foo1() 782; CHECK-NEXT: ret void 783; CHECK: return: 784; CHECK-NEXT: ret void 785; 786 %cmp = icmp ult i32 %x, 3 787 %switch = icmp ult i32 %y, 2 788 %or.cond775 = select i1 %cmp, i1 true, i1 %switch 789 br i1 %or.cond775, label %lor.lhs.false8, label %return 790 791lor.lhs.false8: 792 tail call void @foo1() 793 ret void 794 795return: 796 ret void 797 798} 799 800define void @test18(i32 %arg) { 801; CHECK-LABEL: @test18( 802; CHECK-NEXT: bb: 803; CHECK-NEXT: [[ARG_OFF:%.*]] = add i32 [[ARG:%.*]], -8 804; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[ARG_OFF]], 11 805; CHECK-NEXT: br i1 [[SWITCH]], label [[BB19:%.*]], label [[BB20:%.*]] 806; CHECK: bb19: 807; CHECK-NEXT: tail call void @foo1() 808; CHECK-NEXT: br label [[BB20]] 809; CHECK: bb20: 810; CHECK-NEXT: ret void 811; 812bb: 813 %tmp = and i32 %arg, -2 814 %tmp1 = icmp eq i32 %tmp, 8 815 %tmp2 = icmp eq i32 %arg, 10 816 %tmp3 = or i1 %tmp1, %tmp2 817 %tmp4 = icmp eq i32 %arg, 11 818 %tmp5 = or i1 %tmp3, %tmp4 819 %tmp6 = icmp eq i32 %arg, 12 820 %tmp7 = or i1 %tmp5, %tmp6 821 br i1 %tmp7, label %bb19, label %bb8 822 823bb8: ; preds = %bb 824 %tmp9 = add i32 %arg, -13 825 %tmp10 = icmp ult i32 %tmp9, 2 826 %tmp11 = icmp eq i32 %arg, 16 827 %tmp12 = or i1 %tmp10, %tmp11 828 %tmp13 = icmp eq i32 %arg, 17 829 %tmp14 = or i1 %tmp12, %tmp13 830 %tmp15 = icmp eq i32 %arg, 18 831 %tmp16 = or i1 %tmp14, %tmp15 832 %tmp17 = icmp eq i32 %arg, 15 833 %tmp18 = or i1 %tmp16, %tmp17 834 br i1 %tmp18, label %bb19, label %bb20 835 836bb19: ; preds = %bb8, %bb 837 tail call void @foo1() 838 br label %bb20 839 840bb20: ; preds = %bb19, %bb8 841 ret void 842 843} 844 845define void @PR26323(i1 %tobool23, i32 %tmp3) { 846; CHECK-LABEL: @PR26323( 847; CHECK-NEXT: entry: 848; CHECK-NEXT: [[TOBOOL5:%.*]] = icmp ne i32 [[TMP3:%.*]], 0 849; CHECK-NEXT: [[NEG14:%.*]] = and i32 [[TMP3]], -2 850; CHECK-NEXT: [[CMP17:%.*]] = icmp ne i32 [[NEG14]], -1 851; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[TOBOOL5]], [[TOBOOL23:%.*]] 852; CHECK-NEXT: [[OR_COND1:%.*]] = and i1 [[CMP17]], [[OR_COND]] 853; CHECK-NEXT: br i1 [[OR_COND1]], label [[IF_END29:%.*]], label [[IF_THEN27:%.*]] 854; CHECK: if.then27: 855; CHECK-NEXT: call void @foo1() 856; CHECK-NEXT: unreachable 857; CHECK: if.end29: 858; CHECK-NEXT: ret void 859; 860entry: 861 %tobool5 = icmp ne i32 %tmp3, 0 862 %neg14 = and i32 %tmp3, -2 863 %cmp17 = icmp ne i32 %neg14, -1 864 %or.cond = and i1 %tobool5, %tobool23 865 %or.cond1 = and i1 %cmp17, %or.cond 866 br i1 %or.cond1, label %if.end29, label %if.then27 867 868if.then27: ; preds = %entry 869 call void @foo1() 870 unreachable 871 872if.end29: ; preds = %entry 873 ret void 874} 875 876; Form a switch when and'ing a negated power of two 877define void @test19(i32 %arg) { 878; CHECK-LABEL: @test19( 879; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [ 880; CHECK-NEXT: i32 32, label [[IF:%.*]] 881; CHECK-NEXT: i32 13, label [[IF]] 882; CHECK-NEXT: i32 12, label [[IF]] 883; CHECK-NEXT: ] 884; CHECK: if: 885; CHECK-NEXT: call void @foo1() 886; CHECK-NEXT: ret void 887; CHECK: else: 888; CHECK-NEXT: ret void 889; 890 %and = and i32 %arg, -2 891 %cmp1 = icmp eq i32 %and, 12 892 %cmp2 = icmp eq i32 %arg, 32 893 %pred = or i1 %cmp1, %cmp2 894 br i1 %pred, label %if, label %else 895 896if: 897 call void @foo1() 898 ret void 899 900else: 901 ret void 902} 903 904define void @test19_select(i32 %arg) { 905; CHECK-LABEL: @test19_select( 906; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARG:%.*]], -2 907; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND]], 12 908; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32 909; CHECK-NEXT: [[PRED:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]] 910; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] 911; CHECK: if: 912; CHECK-NEXT: call void @foo1() 913; CHECK-NEXT: ret void 914; CHECK: else: 915; CHECK-NEXT: ret void 916; 917 %and = and i32 %arg, -2 918 %cmp1 = icmp eq i32 %and, 12 919 %cmp2 = icmp eq i32 %arg, 32 920 %pred = select i1 %cmp1, i1 true, i1 %cmp2 921 br i1 %pred, label %if, label %else 922 923if: 924 call void @foo1() 925 ret void 926 927else: 928 ret void 929} 930 931; Since %cmp1 is always false, a switch is never formed 932define void @test20(i32 %arg) { 933; CHECK-LABEL: @test20( 934; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARG:%.*]], -2 935; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND]], 13 936; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32 937; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]] 938; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] 939; CHECK: if: 940; CHECK-NEXT: call void @foo1() 941; CHECK-NEXT: ret void 942; CHECK: else: 943; CHECK-NEXT: ret void 944; 945 %and = and i32 %arg, -2 946 %cmp1 = icmp eq i32 %and, 13 947 %cmp2 = icmp eq i32 %arg, 32 948 %pred = or i1 %cmp1, %cmp2 949 br i1 %pred, label %if, label %else 950 951if: 952 call void @foo1() 953 ret void 954 955else: 956 ret void 957} 958 959; Form a switch when or'ing a power of two 960define void @test21(i32 %arg) { 961; CHECK-LABEL: @test21( 962; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[IF:%.*]] [ 963; CHECK-NEXT: i32 32, label [[ELSE:%.*]] 964; CHECK-NEXT: i32 13, label [[ELSE]] 965; CHECK-NEXT: i32 12, label [[ELSE]] 966; CHECK-NEXT: ] 967; CHECK: if: 968; CHECK-NEXT: call void @foo1() 969; CHECK-NEXT: ret void 970; CHECK: else: 971; CHECK-NEXT: ret void 972; 973 %and = or i32 %arg, 1 974 %cmp1 = icmp ne i32 %and, 13 975 %cmp2 = icmp ne i32 %arg, 32 976 %pred = and i1 %cmp1, %cmp2 977 br i1 %pred, label %if, label %else 978 979if: 980 call void @foo1() 981 ret void 982 983else: 984 ret void 985} 986 987; Since %cmp1 is always false, a switch is never formed 988define void @test22(i32 %arg) { 989; CHECK-LABEL: @test22( 990; CHECK-NEXT: [[AND:%.*]] = or i32 [[ARG:%.*]], 1 991; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 12 992; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32 993; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]] 994; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] 995; CHECK: if: 996; CHECK-NEXT: call void @foo1() 997; CHECK-NEXT: ret void 998; CHECK: else: 999; CHECK-NEXT: ret void 1000; 1001 %and = or i32 %arg, 1 1002 %cmp1 = icmp ne i32 %and, 12 1003 %cmp2 = icmp ne i32 %arg, 32 1004 %pred = and i1 %cmp1, %cmp2 1005 br i1 %pred, label %if, label %else 1006 1007if: 1008 call void @foo1() 1009 ret void 1010 1011else: 1012 ret void 1013} 1014