1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -sroa -S | FileCheck %s
3target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-f80:128-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
4
5declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
6declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
7
8; This tests that allocas are not split into slices that are not byte width multiple
9define void @no_split_on_non_byte_width(i32) {
10; CHECK-LABEL: @no_split_on_non_byte_width(
11; CHECK-NEXT:    [[ARG_SROA_0:%.*]] = alloca i8, align 8
12; CHECK-NEXT:    [[ARG_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0:%.*]] to i8
13; CHECK-NEXT:    store i8 [[ARG_SROA_0_0_EXTRACT_TRUNC]], i8* [[ARG_SROA_0]], align 8
14; CHECK-NEXT:    [[ARG_SROA_3_0_EXTRACT_SHIFT:%.*]] = lshr i32 [[TMP0]], 8
15; CHECK-NEXT:    [[ARG_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[ARG_SROA_3_0_EXTRACT_SHIFT]] to i24
16; CHECK-NEXT:    br label [[LOAD_I32:%.*]]
17; CHECK:       load_i32:
18; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_R0:%.*]] = load i8, i8* [[ARG_SROA_0]], align 8
19; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_EXT:%.*]] = zext i24 [[ARG_SROA_3_0_EXTRACT_TRUNC]] to i32
20; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_SHIFT:%.*]] = shl i32 [[ARG_SROA_3_0_INSERT_EXT]], 8
21; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_MASK:%.*]] = and i32 undef, 255
22; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_INSERT:%.*]] = or i32 [[ARG_SROA_3_0_INSERT_MASK]], [[ARG_SROA_3_0_INSERT_SHIFT]]
23; CHECK-NEXT:    [[ARG_SROA_0_0_INSERT_EXT:%.*]] = zext i8 [[ARG_SROA_0_0_ARG_SROA_0_0_R0]] to i32
24; CHECK-NEXT:    [[ARG_SROA_0_0_INSERT_MASK:%.*]] = and i32 [[ARG_SROA_3_0_INSERT_INSERT]], -256
25; CHECK-NEXT:    [[ARG_SROA_0_0_INSERT_INSERT:%.*]] = or i32 [[ARG_SROA_0_0_INSERT_MASK]], [[ARG_SROA_0_0_INSERT_EXT]]
26; CHECK-NEXT:    br label [[LOAD_I1:%.*]]
27; CHECK:       load_i1:
28; CHECK-NEXT:    [[ARG_SROA_0_0_P1_SROA_CAST2:%.*]] = bitcast i8* [[ARG_SROA_0]] to i1*
29; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_T1:%.*]] = load i1, i1* [[ARG_SROA_0_0_P1_SROA_CAST2]], align 8
30; CHECK-NEXT:    ret void
31;
32  %arg = alloca i32 , align 8
33  store i32 %0, i32* %arg
34  br label %load_i32
35
36load_i32:
37  %r0 = load i32, i32* %arg
38  br label %load_i1
39
40load_i1:
41  %p1 = bitcast i32* %arg to i1*
42  %t1 = load i1, i1* %p1
43  ret void
44}
45
46; PR18726: Check that we use memcpy and memset to fill out padding when we have
47; a slice with a simple single type whose store size is smaller than the slice
48; size.
49
50%union.Foo = type { x86_fp80, i64, i64 }
51
52@foo_copy_source = external constant %union.Foo
53@i64_sink = global i64 0
54
55define void @memcpy_fp80_padding() {
56; CHECK-LABEL: @memcpy_fp80_padding(
57; CHECK-NEXT:    [[X_SROA_0:%.*]] = alloca x86_fp80, align 16
58; CHECK-NEXT:    [[X_SROA_0_0_X_I8_SROA_CAST:%.*]] = bitcast x86_fp80* [[X_SROA_0]] to i8*
59; CHECK-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 [[X_SROA_0_0_X_I8_SROA_CAST]], i8* align 16 bitcast (%union.Foo* @foo_copy_source to i8*), i32 16, i1 false)
60; CHECK-NEXT:    [[X_SROA_1_0_COPYLOAD:%.*]] = load i64, i64* getelementptr inbounds ([[UNION_FOO:%.*]], %union.Foo* @foo_copy_source, i64 0, i32 1), align 16
61; CHECK-NEXT:    [[X_SROA_2_0_COPYLOAD:%.*]] = load i64, i64* getelementptr inbounds ([[UNION_FOO]], %union.Foo* @foo_copy_source, i64 0, i32 2), align 8
62; CHECK-NEXT:    store i64 [[X_SROA_1_0_COPYLOAD]], i64* @i64_sink, align 4
63; CHECK-NEXT:    ret void
64;
65  %x = alloca %union.Foo
66
67  ; Copy from a global.
68  %x_i8 = bitcast %union.Foo* %x to i8*
69  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 %x_i8, i8* align 16 bitcast (%union.Foo* @foo_copy_source to i8*), i32 32, i1 false)
70
71  ; Access a slice of the alloca to trigger SROA.
72  %mid_p = getelementptr %union.Foo, %union.Foo* %x, i32 0, i32 1
73  %elt = load i64, i64* %mid_p
74  store i64 %elt, i64* @i64_sink
75  ret void
76}
77
78define void @memset_fp80_padding() {
79; CHECK-LABEL: @memset_fp80_padding(
80; CHECK-NEXT:    [[X_SROA_0:%.*]] = alloca x86_fp80, align 16
81; CHECK-NEXT:    [[X_SROA_0_0_X_I8_SROA_CAST1:%.*]] = bitcast x86_fp80* [[X_SROA_0]] to i8*
82; CHECK-NEXT:    call void @llvm.memset.p0i8.i32(i8* align 16 [[X_SROA_0_0_X_I8_SROA_CAST1]], i8 -1, i32 16, i1 false)
83; CHECK-NEXT:    store i64 -1, i64* @i64_sink, align 4
84; CHECK-NEXT:    ret void
85;
86  %x = alloca %union.Foo
87
88  ; Set to all ones.
89  %x_i8 = bitcast %union.Foo* %x to i8*
90  call void @llvm.memset.p0i8.i32(i8* align 16 %x_i8, i8 -1, i32 32, i1 false)
91
92  ; Access a slice of the alloca to trigger SROA.
93  %mid_p = getelementptr %union.Foo, %union.Foo* %x, i32 0, i32 1
94  %elt = load i64, i64* %mid_p
95  store i64 %elt, i64* @i64_sink
96  ret void
97}
98
99%S.vec3float = type { float, float, float }
100%U.vec3float = type { <4 x float> }
101
102declare i32 @memcpy_vec3float_helper(%S.vec3float*)
103
104; PR18726: Check that SROA does not rewrite a 12-byte memcpy into a 16-byte
105; vector store, hence accidentally putting gibberish onto the stack.
106define i32 @memcpy_vec3float_widening(%S.vec3float* %x) {
107; CHECK-LABEL: @memcpy_vec3float_widening(
108; CHECK-NEXT:  entry:
109; CHECK-NEXT:    [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST_SROA_CAST:%.*]] = bitcast %S.vec3float* [[X:%.*]] to <3 x float>*
110; CHECK-NEXT:    [[TMP1_SROA_0_0_COPYLOAD:%.*]] = load <3 x float>, <3 x float>* [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST_SROA_CAST]], align 4
111; CHECK-NEXT:    [[TMP1_SROA_0_0_VEC_EXPAND:%.*]] = shufflevector <3 x float> [[TMP1_SROA_0_0_COPYLOAD]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
112; CHECK-NEXT:    [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> undef
113; CHECK-NEXT:    [[TMP2:%.*]] = alloca [[S_VEC3FLOAT:%.*]], align 4
114; CHECK-NEXT:    [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST2_SROA_CAST:%.*]] = bitcast %S.vec3float* [[TMP2]] to <3 x float>*
115; CHECK-NEXT:    [[TMP1_SROA_0_0_VEC_EXTRACT:%.*]] = shufflevector <4 x float> [[TMP1_SROA_0_0_VECBLEND]], <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
116; CHECK-NEXT:    store <3 x float> [[TMP1_SROA_0_0_VEC_EXTRACT]], <3 x float>* [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST2_SROA_CAST]], align 4
117; CHECK-NEXT:    [[RESULT:%.*]] = call i32 @memcpy_vec3float_helper(%S.vec3float* [[TMP2]])
118; CHECK-NEXT:    ret i32 [[RESULT]]
119entry:
120  ; Create a temporary variable %tmp1 and copy %x[0] into it
121  %tmp1 = alloca %S.vec3float, align 4
122  %0 = bitcast %S.vec3float* %tmp1 to i8*
123  %1 = bitcast %S.vec3float* %x to i8*
124  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 12, i1 false)
125
126  ; The following block does nothing; but appears to confuse SROA
127  %unused1 = bitcast %S.vec3float* %tmp1 to %U.vec3float*
128  %unused2 = getelementptr inbounds %U.vec3float, %U.vec3float* %unused1, i32 0, i32 0
129  %unused3 = load <4 x float>, <4 x float>* %unused2, align 1
130
131  ; Create a second temporary and copy %tmp1 into it
132  %tmp2 = alloca %S.vec3float, align 4
133  %2 = bitcast %S.vec3float* %tmp2 to i8*
134  %3 = bitcast %S.vec3float* %tmp1 to i8*
135  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %2, i8* align 4 %3, i32 12, i1 false)
136
137  %result = call i32 @memcpy_vec3float_helper(%S.vec3float* %tmp2)
138  ret i32 %result
139}
140