1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -slp-vectorizer -S %s | FileCheck %s
3
4declare float @memread(float) readonly #0
5declare <4 x float> @vmemread(<4 x float>)
6
7define <4 x float> @memread_4x(<4 x float>* %a) {
8; CHECK-LABEL: @memread_4x(
9; CHECK-NEXT:  entry:
10; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
11; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vmemread(<4 x float> [[TMP0]])
12; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
13; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP2]], i32 0
14; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
15; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
16; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
17; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
18; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
19; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
20; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
21;
22entry:
23  %0 = load <4 x float>, <4 x float>* %a, align 16
24  %vecext = extractelement <4 x float> %0, i32 0
25  %1 = tail call fast float @memread(float %vecext) #0
26  %vecins = insertelement <4 x float> undef, float %1, i32 0
27  %vecext.1 = extractelement <4 x float> %0, i32 1
28  %2 = tail call fast float @memread(float %vecext.1) #0
29  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
30  %vecext.2 = extractelement <4 x float> %0, i32 2
31  %3 = tail call fast float @memread(float %vecext.2) #0
32  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
33  %vecext.3 = extractelement <4 x float> %0, i32 3
34  %4 = tail call fast float @memread(float %vecext.3) #0
35  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
36  ret <4 x float> %vecins.3
37}
38
39declare float @memwrite(float) #1
40declare <4 x float> @vmemwrite(<4 x float>)
41
42define <4 x float> @memwrite_4x(<4 x float>* %a) {
43; CHECK-LABEL: @memwrite_4x(
44; CHECK-NEXT:  entry:
45; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
46; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
47; CHECK-NEXT:    [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #1
48; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> undef, float [[TMP1]], i32 0
49; CHECK-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
50; CHECK-NEXT:    [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #1
51; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
52; CHECK-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
53; CHECK-NEXT:    [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #1
54; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
55; CHECK-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
56; CHECK-NEXT:    [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #1
57; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
58; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
59;
60entry:
61  %0 = load <4 x float>, <4 x float>* %a, align 16
62  %vecext = extractelement <4 x float> %0, i32 0
63  %1 = tail call fast float @memwrite(float %vecext) #1
64  %vecins = insertelement <4 x float> undef, float %1, i32 0
65  %vecext.1 = extractelement <4 x float> %0, i32 1
66  %2 = tail call fast float @memwrite(float %vecext.1) #1
67  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
68  %vecext.2 = extractelement <4 x float> %0, i32 2
69  %3 = tail call fast float @memwrite(float %vecext.2) #1
70  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
71  %vecext.3 = extractelement <4 x float> %0, i32 3
72  %4 = tail call fast float @memwrite(float %vecext.3) #1
73  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
74  ret <4 x float> %vecins.3
75}
76
77attributes #0 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memread(vmemread)" }
78attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memwrite(vmemwrite)" }
79