1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX 3; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,SSE 4; REQUIRES: asserts 5 6; int test_add(unsigned int *p) { 7; int result = 0; 8; for (int i = 0; i < 8; i++) 9; result += p[i]; 10; return result; 11; } 12 13; Vector cost is 5, Scalar cost is 7 14; AVX: Adding cost -2 for reduction that starts with %0 = load i32, i32* %p, align 4 (It is a splitting reduction) 15; Vector cost is 6, Scalar cost is 7 16; SSE: Adding cost -1 for reduction that starts with %0 = load i32, i32* %p, align 4 (It is a splitting reduction) 17define i32 @test_add(i32* nocapture readonly %p) { 18; CHECK-LABEL: @test_add( 19; CHECK-NEXT: entry: 20; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <8 x i32>* 21; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4 22; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP1]]) 23; CHECK-NEXT: ret i32 [[TMP2]] 24; 25entry: 26 %0 = load i32, i32* %p, align 4 27 %arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1 28 %1 = load i32, i32* %arrayidx.1, align 4 29 %mul.18 = add i32 %1, %0 30 %arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2 31 %2 = load i32, i32* %arrayidx.2, align 4 32 %mul.29 = add i32 %2, %mul.18 33 %arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3 34 %3 = load i32, i32* %arrayidx.3, align 4 35 %mul.310 = add i32 %3, %mul.29 36 %arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4 37 %4 = load i32, i32* %arrayidx.4, align 4 38 %mul.411 = add i32 %4, %mul.310 39 %arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5 40 %5 = load i32, i32* %arrayidx.5, align 4 41 %mul.512 = add i32 %5, %mul.411 42 %arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6 43 %6 = load i32, i32* %arrayidx.6, align 4 44 %mul.613 = add i32 %6, %mul.512 45 %arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7 46 %7 = load i32, i32* %arrayidx.7, align 4 47 %mul.714 = add i32 %7, %mul.613 48 ret i32 %mul.714 49} 50 51; int test_mul(unsigned int *p) { 52; int result = 0; 53; for (int i = 0; i < 8; i++) 54; result *= p[i]; 55; return result; 56; } 57 58define i32 @test_mul(i32* nocapture readonly %p) { 59; AVX-LABEL: @test_mul( 60; AVX-NEXT: entry: 61; AVX-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <8 x i32>* 62; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4 63; AVX-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> [[TMP1]]) 64; AVX-NEXT: ret i32 [[TMP2]] 65; 66; SSE-LABEL: @test_mul( 67; SSE-NEXT: entry: 68; SSE-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4 69; SSE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1 70; SSE-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4 71; SSE-NEXT: [[MUL_18:%.*]] = mul i32 [[TMP1]], [[TMP0]] 72; SSE-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2 73; SSE-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4 74; SSE-NEXT: [[MUL_29:%.*]] = mul i32 [[TMP2]], [[MUL_18]] 75; SSE-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3 76; SSE-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4 77; SSE-NEXT: [[MUL_310:%.*]] = mul i32 [[TMP3]], [[MUL_29]] 78; SSE-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4 79; SSE-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4 80; SSE-NEXT: [[MUL_411:%.*]] = mul i32 [[TMP4]], [[MUL_310]] 81; SSE-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5 82; SSE-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4 83; SSE-NEXT: [[MUL_512:%.*]] = mul i32 [[TMP5]], [[MUL_411]] 84; SSE-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6 85; SSE-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4 86; SSE-NEXT: [[MUL_613:%.*]] = mul i32 [[TMP6]], [[MUL_512]] 87; SSE-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7 88; SSE-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4 89; SSE-NEXT: [[MUL_714:%.*]] = mul i32 [[TMP7]], [[MUL_613]] 90; SSE-NEXT: ret i32 [[MUL_714]] 91; 92entry: 93 %0 = load i32, i32* %p, align 4 94 %arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1 95 %1 = load i32, i32* %arrayidx.1, align 4 96 %mul.18 = mul i32 %1, %0 97 %arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2 98 %2 = load i32, i32* %arrayidx.2, align 4 99 %mul.29 = mul i32 %2, %mul.18 100 %arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3 101 %3 = load i32, i32* %arrayidx.3, align 4 102 %mul.310 = mul i32 %3, %mul.29 103 %arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4 104 %4 = load i32, i32* %arrayidx.4, align 4 105 %mul.411 = mul i32 %4, %mul.310 106 %arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5 107 %5 = load i32, i32* %arrayidx.5, align 4 108 %mul.512 = mul i32 %5, %mul.411 109 %arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6 110 %6 = load i32, i32* %arrayidx.6, align 4 111 %mul.613 = mul i32 %6, %mul.512 112 %arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7 113 %7 = load i32, i32* %arrayidx.7, align 4 114 %mul.714 = mul i32 %7, %mul.613 115 ret i32 %mul.714 116} 117 118; int test_and(unsigned int *p) { 119; int result = 0; 120; for (int i = 0; i < 8; i++) 121; result &= p[i]; 122; return result; 123; } 124 125define i32 @test_and(i32* nocapture readonly %p) { 126; CHECK-LABEL: @test_and( 127; CHECK-NEXT: entry: 128; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <8 x i32>* 129; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4 130; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> [[TMP1]]) 131; CHECK-NEXT: ret i32 [[TMP2]] 132; 133entry: 134 %0 = load i32, i32* %p, align 4 135 %arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1 136 %1 = load i32, i32* %arrayidx.1, align 4 137 %mul.18 = and i32 %1, %0 138 %arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2 139 %2 = load i32, i32* %arrayidx.2, align 4 140 %mul.29 = and i32 %2, %mul.18 141 %arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3 142 %3 = load i32, i32* %arrayidx.3, align 4 143 %mul.310 = and i32 %3, %mul.29 144 %arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4 145 %4 = load i32, i32* %arrayidx.4, align 4 146 %mul.411 = and i32 %4, %mul.310 147 %arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5 148 %5 = load i32, i32* %arrayidx.5, align 4 149 %mul.512 = and i32 %5, %mul.411 150 %arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6 151 %6 = load i32, i32* %arrayidx.6, align 4 152 %mul.613 = and i32 %6, %mul.512 153 %arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7 154 %7 = load i32, i32* %arrayidx.7, align 4 155 %mul.714 = and i32 %7, %mul.613 156 ret i32 %mul.714 157} 158 159; int test_or(unsigned int *p) { 160; int result = 0; 161; for (int i = 0; i < 8; i++) 162; result |= p[i]; 163; return result; 164; } 165 166define i32 @test_or(i32* nocapture readonly %p) { 167; CHECK-LABEL: @test_or( 168; CHECK-NEXT: entry: 169; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <8 x i32>* 170; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4 171; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP1]]) 172; CHECK-NEXT: ret i32 [[TMP2]] 173; 174entry: 175 %0 = load i32, i32* %p, align 4 176 %arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1 177 %1 = load i32, i32* %arrayidx.1, align 4 178 %mul.18 = or i32 %1, %0 179 %arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2 180 %2 = load i32, i32* %arrayidx.2, align 4 181 %mul.29 = or i32 %2, %mul.18 182 %arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3 183 %3 = load i32, i32* %arrayidx.3, align 4 184 %mul.310 = or i32 %3, %mul.29 185 %arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4 186 %4 = load i32, i32* %arrayidx.4, align 4 187 %mul.411 = or i32 %4, %mul.310 188 %arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5 189 %5 = load i32, i32* %arrayidx.5, align 4 190 %mul.512 = or i32 %5, %mul.411 191 %arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6 192 %6 = load i32, i32* %arrayidx.6, align 4 193 %mul.613 = or i32 %6, %mul.512 194 %arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7 195 %7 = load i32, i32* %arrayidx.7, align 4 196 %mul.714 = or i32 %7, %mul.613 197 ret i32 %mul.714 198} 199 200; int test_xor(unsigned int *p) { 201; int result = 0; 202; for (int i = 0; i < 8; i++) 203; result ^= p[i]; 204; return result; 205; } 206 207define i32 @test_xor(i32* nocapture readonly %p) { 208; CHECK-LABEL: @test_xor( 209; CHECK-NEXT: entry: 210; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <8 x i32>* 211; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4 212; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> [[TMP1]]) 213; CHECK-NEXT: ret i32 [[TMP2]] 214; 215entry: 216 %0 = load i32, i32* %p, align 4 217 %arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1 218 %1 = load i32, i32* %arrayidx.1, align 4 219 %mul.18 = xor i32 %1, %0 220 %arrayidx.2 = getelementptr inbounds i32, i32* %p, i64 2 221 %2 = load i32, i32* %arrayidx.2, align 4 222 %mul.29 = xor i32 %2, %mul.18 223 %arrayidx.3 = getelementptr inbounds i32, i32* %p, i64 3 224 %3 = load i32, i32* %arrayidx.3, align 4 225 %mul.310 = xor i32 %3, %mul.29 226 %arrayidx.4 = getelementptr inbounds i32, i32* %p, i64 4 227 %4 = load i32, i32* %arrayidx.4, align 4 228 %mul.411 = xor i32 %4, %mul.310 229 %arrayidx.5 = getelementptr inbounds i32, i32* %p, i64 5 230 %5 = load i32, i32* %arrayidx.5, align 4 231 %mul.512 = xor i32 %5, %mul.411 232 %arrayidx.6 = getelementptr inbounds i32, i32* %p, i64 6 233 %6 = load i32, i32* %arrayidx.6, align 4 234 %mul.613 = xor i32 %6, %mul.512 235 %arrayidx.7 = getelementptr inbounds i32, i32* %p, i64 7 236 %7 = load i32, i32* %arrayidx.7, align 4 237 %mul.714 = xor i32 %7, %mul.613 238 ret i32 %mul.714 239} 240 241define i32 @PR37731(<4 x i32>* noalias nocapture dereferenceable(16) %self) unnamed_addr #0 { 242; CHECK-LABEL: @PR37731( 243; CHECK-NEXT: entry: 244; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[SELF:%.*]], align 16 245; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[TMP0]], <i32 6, i32 2, i32 13, i32 3> 246; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], [[TMP0]] 247; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[TMP2]], <i32 13, i32 27, i32 21, i32 12> 248; CHECK-NEXT: [[TMP4:%.*]] = and <4 x i32> [[TMP0]], <i32 -2, i32 -8, i32 -16, i32 -128> 249; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i32> [[TMP4]], <i32 18, i32 2, i32 7, i32 13> 250; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP3]], [[TMP5]] 251; CHECK-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[SELF]], align 16 252; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP6]]) 253; CHECK-NEXT: ret i32 [[TMP7]] 254; 255entry: 256 %0 = load <4 x i32>, <4 x i32>* %self, align 16 257 %1 = shl <4 x i32> %0, <i32 6, i32 2, i32 13, i32 3> 258 %2 = xor <4 x i32> %1, %0 259 %3 = lshr <4 x i32> %2, <i32 13, i32 27, i32 21, i32 12> 260 %4 = and <4 x i32> %0, <i32 -2, i32 -8, i32 -16, i32 -128> 261 %5 = shl <4 x i32> %4, <i32 18, i32 2, i32 7, i32 13> 262 %6 = xor <4 x i32> %3, %5 263 store <4 x i32> %6, <4 x i32>* %self, align 16 264 %7 = extractelement <4 x i32> %6, i32 0 265 %8 = extractelement <4 x i32> %6, i32 1 266 %9 = xor i32 %7, %8 267 %10 = extractelement <4 x i32> %6, i32 2 268 %11 = xor i32 %9, %10 269 %12 = extractelement <4 x i32> %6, i32 3 270 %13 = xor i32 %11, %12 271 ret i32 %13 272} 273