1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -slp-vectorizer < %s | FileCheck %s
3
4define i64 @test() {
5; CHECK-LABEL: @test(
6; CHECK-NEXT:  bb1:
7; CHECK-NEXT:    br label [[BB3:%.*]]
8; CHECK:       bb2:
9; CHECK-NEXT:    br label [[BB3]]
10; CHECK:       bb3:
11; CHECK-NEXT:    [[TMP0:%.*]] = phi <2 x i32> [ poison, [[BB2:%.*]] ], [ zeroinitializer, [[BB1:%.*]] ]
12; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
13; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 0
14; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[TMP1]], i32 0
15; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[TMP1]], i32 1
16; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[TMP1]], i32 2
17; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[TMP1]], i32 3
18; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[TMP1]], i32 4
19; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[TMP1]], i32 5
20; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[TMP1]], i32 6
21; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[TMP1]], i32 7
22; CHECK-NEXT:    [[TMP10:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> [[TMP9]])
23; CHECK-NEXT:    [[TMP11:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[SHUFFLE]])
24; CHECK-NEXT:    [[OP_RDX:%.*]] = mul i32 [[TMP10]], [[TMP11]]
25; CHECK-NEXT:    [[TMP65:%.*]] = sext i32 [[OP_RDX]] to i64
26; CHECK-NEXT:    ret i64 [[TMP65]]
27;
28bb1:
29  br label %bb3
30
31bb2:
32  br label %bb3
33
34bb3:
35  %tmp = phi i32 [ 0, %bb2 ], [ 0, %bb1 ]
36  %tmp4 = phi i32 [ 0, %bb2 ], [ 0, %bb1 ]
37  %tmp5 = mul i32 %tmp, %tmp4
38  %tmp6 = mul i32 %tmp5, %tmp4
39  %tmp7 = mul i32 %tmp6, %tmp4
40  %tmp8 = mul i32 %tmp7, %tmp4
41  %tmp9 = mul i32 %tmp8, %tmp4
42  %tmp10 = mul i32 %tmp9, %tmp4
43  %tmp11 = mul i32 %tmp10, %tmp4
44  %tmp12 = mul i32 %tmp11, %tmp4
45  %tmp13 = mul i32 %tmp12, %tmp4
46  %tmp14 = mul i32 %tmp13, %tmp4
47  %tmp15 = mul i32 %tmp14, %tmp4
48  %tmp65 = sext i32 %tmp15 to i64
49  ret i64 %tmp65
50}
51