1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -slp-vectorizer -instcombine -S | FileCheck %s
3
4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
5target triple = "aarch64--linux-gnu"
6
7define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
8; CHECK-LABEL: @build_vec_v2i64(
9; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i64> [[V0:%.*]], [[V1:%.*]]
10; CHECK-NEXT:    [[TMP2:%.*]] = sub <2 x i64> [[V0]], [[V1]]
11; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <2 x i32> <i32 1, i32 2>
12; CHECK-NEXT:    [[TMP4:%.*]] = add <2 x i64> [[V0]], [[V1]]
13; CHECK-NEXT:    [[TMP5:%.*]] = sub <2 x i64> [[V0]], [[V1]]
14; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i32> <i32 0, i32 3>
15; CHECK-NEXT:    [[TMP7:%.*]] = add <2 x i64> [[TMP6]], [[TMP3]]
16; CHECK-NEXT:    ret <2 x i64> [[TMP7]]
17;
18  %v0.0 = extractelement <2 x i64> %v0, i32 0
19  %v0.1 = extractelement <2 x i64> %v0, i32 1
20  %v1.0 = extractelement <2 x i64> %v1, i32 0
21  %v1.1 = extractelement <2 x i64> %v1, i32 1
22  %tmp0.0 = add i64 %v0.0, %v1.0
23  %tmp0.1 = add i64 %v0.1, %v1.1
24  %tmp1.0 = sub i64 %v0.0, %v1.0
25  %tmp1.1 = sub i64 %v0.1, %v1.1
26  %tmp2.0 = add i64 %tmp0.0, %tmp0.1
27  %tmp2.1 = add i64 %tmp1.0, %tmp1.1
28  %tmp3.0 = insertelement <2 x i64> undef, i64 %tmp2.0, i32 0
29  %tmp3.1 = insertelement <2 x i64> %tmp3.0, i64 %tmp2.1, i32 1
30  ret <2 x i64> %tmp3.1
31}
32
33define void @store_chain_v2i64(i64* %a, i64* %b, i64* %c) {
34; CHECK-LABEL: @store_chain_v2i64(
35; CHECK-NEXT:    [[A_1:%.*]] = getelementptr i64, i64* [[A:%.*]], i64 1
36; CHECK-NEXT:    [[B_1:%.*]] = getelementptr i64, i64* [[B:%.*]], i64 1
37; CHECK-NEXT:    [[C_1:%.*]] = getelementptr i64, i64* [[C:%.*]], i64 1
38; CHECK-NEXT:    [[V0_0:%.*]] = load i64, i64* [[A]], align 8
39; CHECK-NEXT:    [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8
40; CHECK-NEXT:    [[V1_0:%.*]] = load i64, i64* [[B]], align 8
41; CHECK-NEXT:    [[V1_1:%.*]] = load i64, i64* [[B_1]], align 8
42; CHECK-NEXT:    [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
43; CHECK-NEXT:    [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
44; CHECK-NEXT:    [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
45; CHECK-NEXT:    [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
46; CHECK-NEXT:    [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
47; CHECK-NEXT:    [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
48; CHECK-NEXT:    store i64 [[TMP2_0]], i64* [[C]], align 8
49; CHECK-NEXT:    store i64 [[TMP2_1]], i64* [[C_1]], align 8
50; CHECK-NEXT:    ret void
51;
52  %a.0 = getelementptr i64, i64* %a, i64 0
53  %a.1 = getelementptr i64, i64* %a, i64 1
54  %b.0 = getelementptr i64, i64* %b, i64 0
55  %b.1 = getelementptr i64, i64* %b, i64 1
56  %c.0 = getelementptr i64, i64* %c, i64 0
57  %c.1 = getelementptr i64, i64* %c, i64 1
58  %v0.0 = load i64, i64* %a.0, align 8
59  %v0.1 = load i64, i64* %a.1, align 8
60  %v1.0 = load i64, i64* %b.0, align 8
61  %v1.1 = load i64, i64* %b.1, align 8
62  %tmp0.0 = add i64 %v0.0, %v1.0
63  %tmp0.1 = add i64 %v0.1, %v1.1
64  %tmp1.0 = sub i64 %v0.0, %v1.0
65  %tmp1.1 = sub i64 %v0.1, %v1.1
66  %tmp2.0 = add i64 %tmp0.0, %tmp0.1
67  %tmp2.1 = add i64 %tmp1.0, %tmp1.1
68  store i64 %tmp2.0, i64* %c.0, align 8
69  store i64 %tmp2.1, i64* %c.1, align 8
70  ret void
71}
72
73define <4 x i32> @build_vec_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
74; CHECK-LABEL: @build_vec_v4i32(
75; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], [[V1:%.*]]
76; CHECK-NEXT:    [[TMP2:%.*]] = sub <4 x i32> [[V0]], [[V1]]
77; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
78; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i32> [[V0]], [[V1]]
79; CHECK-NEXT:    [[TMP5:%.*]] = sub <4 x i32> [[V0]], [[V1]]
80; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
81; CHECK-NEXT:    [[TMP7:%.*]] = add <4 x i32> [[TMP6]], [[TMP3]]
82; CHECK-NEXT:    ret <4 x i32> [[TMP7]]
83;
84  %v0.0 = extractelement <4 x i32> %v0, i32 0
85  %v0.1 = extractelement <4 x i32> %v0, i32 1
86  %v0.2 = extractelement <4 x i32> %v0, i32 2
87  %v0.3 = extractelement <4 x i32> %v0, i32 3
88  %v1.0 = extractelement <4 x i32> %v1, i32 0
89  %v1.1 = extractelement <4 x i32> %v1, i32 1
90  %v1.2 = extractelement <4 x i32> %v1, i32 2
91  %v1.3 = extractelement <4 x i32> %v1, i32 3
92  %tmp0.0 = add i32 %v0.0, %v1.0
93  %tmp0.1 = add i32 %v0.1, %v1.1
94  %tmp0.2 = add i32 %v0.2, %v1.2
95  %tmp0.3 = add i32 %v0.3, %v1.3
96  %tmp1.0 = sub i32 %v0.0, %v1.0
97  %tmp1.1 = sub i32 %v0.1, %v1.1
98  %tmp1.2 = sub i32 %v0.2, %v1.2
99  %tmp1.3 = sub i32 %v0.3, %v1.3
100  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
101  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
102  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
103  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
104  %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
105  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
106  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
107  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
108  ret <4 x i32> %tmp3.3
109}
110
111define <4 x i32> @build_vec_v4i32_reuse_0(<2 x i32> %v0, <2 x i32> %v1) {
112; CHECK-LABEL: @build_vec_v4i32_reuse_0(
113; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[V0:%.*]], [[V1:%.*]]
114; CHECK-NEXT:    [[TMP2:%.*]] = sub <2 x i32> [[V0]], [[V1]]
115; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 1, i32 2>
116; CHECK-NEXT:    [[TMP4:%.*]] = add <2 x i32> [[V0]], [[V1]]
117; CHECK-NEXT:    [[TMP5:%.*]] = sub <2 x i32> [[V0]], [[V1]]
118; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> <i32 0, i32 3>
119; CHECK-NEXT:    [[TMP7:%.*]] = add <2 x i32> [[TMP6]], [[TMP3]]
120; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
121; CHECK-NEXT:    ret <4 x i32> [[SHUFFLE]]
122;
123  %v0.0 = extractelement <2 x i32> %v0, i32 0
124  %v0.1 = extractelement <2 x i32> %v0, i32 1
125  %v1.0 = extractelement <2 x i32> %v1, i32 0
126  %v1.1 = extractelement <2 x i32> %v1, i32 1
127  %tmp0.0 = add i32 %v0.0, %v1.0
128  %tmp0.1 = add i32 %v0.1, %v1.1
129  %tmp1.0 = sub i32 %v0.0, %v1.0
130  %tmp1.1 = sub i32 %v0.1, %v1.1
131  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
132  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
133  %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
134  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
135  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.0, i32 2
136  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.1, i32 3
137  ret <4 x i32> %tmp3.3
138}
139
140define <4 x i32> @build_vec_v4i32_reuse_1(<2 x i32> %v0, <2 x i32> %v1) {
141; CHECK-LABEL: @build_vec_v4i32_reuse_1(
142; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 1
143; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[V1]], i32 0
144; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 1
145; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[V0]], i32 0
146; CHECK-NEXT:    [[TMP0_0:%.*]] = add i32 [[TMP4]], [[TMP2]]
147; CHECK-NEXT:    [[TMP0_1:%.*]] = add i32 [[TMP3]], [[TMP1]]
148; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i32> [[V0]], [[V1]]
149; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0_0]], i32 0
150; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0_1]], i32 0
151; CHECK-NEXT:    [[TMP8:%.*]] = sub <2 x i32> [[TMP6]], [[TMP7]]
152; CHECK-NEXT:    [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> undef, <2 x i32> <i32 1, i32 0>
153; CHECK-NEXT:    [[TMP10:%.*]] = sub <2 x i32> [[TMP5]], [[TMP9]]
154; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
155; CHECK-NEXT:    [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
156; CHECK-NEXT:    [[TMP2_31:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
157; CHECK-NEXT:    ret <4 x i32> [[TMP2_31]]
158;
159  %v0.0 = extractelement <2 x i32> %v0, i32 0
160  %v0.1 = extractelement <2 x i32> %v0, i32 1
161  %v1.0 = extractelement <2 x i32> %v1, i32 0
162  %v1.1 = extractelement <2 x i32> %v1, i32 1
163  %tmp0.0 = add i32 %v0.0, %v1.0
164  %tmp0.1 = add i32 %v0.1, %v1.1
165  %tmp0.2 = xor i32 %v0.0, %v1.0
166  %tmp0.3 = xor i32 %v0.1, %v1.1
167  %tmp1.0 = sub i32 %tmp0.0, %tmp0.1
168  %tmp1.1 = sub i32 %tmp0.0, %tmp0.1
169  %tmp1.2 = sub i32 %tmp0.2, %tmp0.3
170  %tmp1.3 = sub i32 %tmp0.3, %tmp0.2
171  %tmp2.0 = insertelement <4 x i32> undef, i32 %tmp1.0, i32 0
172  %tmp2.1 = insertelement <4 x i32> %tmp2.0, i32 %tmp1.1, i32 1
173  %tmp2.2 = insertelement <4 x i32> %tmp2.1, i32 %tmp1.2, i32 2
174  %tmp2.3 = insertelement <4 x i32> %tmp2.2, i32 %tmp1.3, i32 3
175  ret <4 x i32> %tmp2.3
176}
177
178define <4 x i32> @build_vec_v4i32_3_binops(<2 x i32> %v0, <2 x i32> %v1) {
179; CHECK-LABEL: @build_vec_v4i32_3_binops(
180; CHECK-NEXT:    [[V0_0:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 0
181; CHECK-NEXT:    [[V0_1:%.*]] = extractelement <2 x i32> [[V0]], i32 1
182; CHECK-NEXT:    [[V1_0:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 0
183; CHECK-NEXT:    [[V1_1:%.*]] = extractelement <2 x i32> [[V1]], i32 1
184; CHECK-NEXT:    [[TMP0_0:%.*]] = add i32 [[V0_0]], [[V1_0]]
185; CHECK-NEXT:    [[TMP0_1:%.*]] = add i32 [[V0_1]], [[V1_1]]
186; CHECK-NEXT:    [[TMP1_0:%.*]] = mul i32 [[V0_0]], [[V1_0]]
187; CHECK-NEXT:    [[TMP1_1:%.*]] = mul i32 [[V0_1]], [[V1_1]]
188; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[V0]], [[V1]]
189; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
190; CHECK-NEXT:    [[TMP3:%.*]] = xor <2 x i32> [[V0]], [[V1]]
191; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
192; CHECK-NEXT:    [[TMP2_0:%.*]] = add i32 [[TMP0_0]], [[TMP0_1]]
193; CHECK-NEXT:    [[TMP2_1:%.*]] = add i32 [[TMP1_0]], [[TMP1_1]]
194; CHECK-NEXT:    [[TMP5:%.*]] = add <2 x i32> [[TMP2]], [[TMP4]]
195; CHECK-NEXT:    [[TMP3_0:%.*]] = insertelement <4 x i32> undef, i32 [[TMP2_0]], i32 0
196; CHECK-NEXT:    [[TMP3_1:%.*]] = insertelement <4 x i32> [[TMP3_0]], i32 [[TMP2_1]], i32 1
197; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
198; CHECK-NEXT:    [[TMP3_31:%.*]] = shufflevector <4 x i32> [[TMP3_1]], <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
199; CHECK-NEXT:    ret <4 x i32> [[TMP3_31]]
200;
201  %v0.0 = extractelement <2 x i32> %v0, i32 0
202  %v0.1 = extractelement <2 x i32> %v0, i32 1
203  %v1.0 = extractelement <2 x i32> %v1, i32 0
204  %v1.1 = extractelement <2 x i32> %v1, i32 1
205  %tmp0.0 = add i32 %v0.0, %v1.0
206  %tmp0.1 = add i32 %v0.1, %v1.1
207  %tmp0.2 = xor i32 %v0.0, %v1.0
208  %tmp0.3 = xor i32 %v0.1, %v1.1
209  %tmp1.0 = mul i32 %v0.0, %v1.0
210  %tmp1.1 = mul i32 %v0.1, %v1.1
211  %tmp1.2 = xor i32 %v0.0, %v1.0
212  %tmp1.3 = xor i32 %v0.1, %v1.1
213  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
214  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
215  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
216  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
217  %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
218  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
219  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
220  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
221  ret <4 x i32> %tmp3.3
222}
223
224define i32 @reduction_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
225; CHECK-LABEL: @reduction_v4i32(
226; CHECK-NEXT:    [[TMP1:%.*]] = sub <4 x i32> [[V0:%.*]], [[V1:%.*]]
227; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[V0]], [[V1]]
228; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 1, i32 4, i32 7, i32 2>
229; CHECK-NEXT:    [[TMP4:%.*]] = sub <4 x i32> [[V0]], [[V1]]
230; CHECK-NEXT:    [[TMP5:%.*]] = add <4 x i32> [[V0]], [[V1]]
231; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
232; CHECK-NEXT:    [[TMP7:%.*]] = add <4 x i32> [[TMP6]], [[TMP3]]
233; CHECK-NEXT:    [[TMP8:%.*]] = lshr <4 x i32> [[TMP7]], <i32 15, i32 15, i32 15, i32 15>
234; CHECK-NEXT:    [[TMP9:%.*]] = and <4 x i32> [[TMP8]], <i32 65537, i32 65537, i32 65537, i32 65537>
235; CHECK-NEXT:    [[TMP10:%.*]] = mul nuw <4 x i32> [[TMP9]], <i32 65535, i32 65535, i32 65535, i32 65535>
236; CHECK-NEXT:    [[TMP11:%.*]] = add <4 x i32> [[TMP10]], [[TMP7]]
237; CHECK-NEXT:    [[TMP12:%.*]] = xor <4 x i32> [[TMP11]], [[TMP10]]
238; CHECK-NEXT:    [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP12]])
239; CHECK-NEXT:    ret i32 [[TMP13]]
240;
241  %v0.0 = extractelement <4 x i32> %v0, i32 0
242  %v0.1 = extractelement <4 x i32> %v0, i32 1
243  %v0.2 = extractelement <4 x i32> %v0, i32 2
244  %v0.3 = extractelement <4 x i32> %v0, i32 3
245  %v1.0 = extractelement <4 x i32> %v1, i32 0
246  %v1.1 = extractelement <4 x i32> %v1, i32 1
247  %v1.2 = extractelement <4 x i32> %v1, i32 2
248  %v1.3 = extractelement <4 x i32> %v1, i32 3
249  %tmp0.0 = add i32 %v0.0, %v1.0
250  %tmp0.1 = add i32 %v0.1, %v1.1
251  %tmp0.2 = add i32 %v0.2, %v1.2
252  %tmp0.3 = add i32 %v0.3, %v1.3
253  %tmp1.0 = sub i32 %v0.0, %v1.0
254  %tmp1.1 = sub i32 %v0.1, %v1.1
255  %tmp1.2 = sub i32 %v0.2, %v1.2
256  %tmp1.3 = sub i32 %v0.3, %v1.3
257  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
258  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
259  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
260  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
261  %tmp3.0 = lshr i32 %tmp2.0, 15
262  %tmp3.1 = lshr i32 %tmp2.1, 15
263  %tmp3.2 = lshr i32 %tmp2.2, 15
264  %tmp3.3 = lshr i32 %tmp2.3, 15
265  %tmp4.0 = and i32 %tmp3.0, 65537
266  %tmp4.1 = and i32 %tmp3.1, 65537
267  %tmp4.2 = and i32 %tmp3.2, 65537
268  %tmp4.3 = and i32 %tmp3.3, 65537
269  %tmp5.0 = mul nuw i32 %tmp4.0, 65535
270  %tmp5.1 = mul nuw i32 %tmp4.1, 65535
271  %tmp5.2 = mul nuw i32 %tmp4.2, 65535
272  %tmp5.3 = mul nuw i32 %tmp4.3, 65535
273  %tmp6.0 = add i32 %tmp5.0, %tmp2.0
274  %tmp6.1 = add i32 %tmp5.1, %tmp2.1
275  %tmp6.2 = add i32 %tmp5.2, %tmp2.2
276  %tmp6.3 = add i32 %tmp5.3, %tmp2.3
277  %tmp7.0 = xor i32 %tmp6.0, %tmp5.0
278  %tmp7.1 = xor i32 %tmp6.1, %tmp5.1
279  %tmp7.2 = xor i32 %tmp6.2, %tmp5.2
280  %tmp7.3 = xor i32 %tmp6.3, %tmp5.3
281  %reduce.0 = add i32 %tmp7.1, %tmp7.0
282  %reduce.1 = add i32 %reduce.0, %tmp7.2
283  %reduce.2 = add i32 %reduce.1, %tmp7.3
284  ret i32 %reduce.2
285}
286