1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -slp-vectorizer -instcombine -S | FileCheck %s
3
4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
5target triple = "aarch64--linux-gnu"
6
7define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
8; CHECK-LABEL: @build_vec_v2i64(
9; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[V0:%.*]], <2 x i64> undef, <2 x i32> <i32 1, i32 0>
10; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[V1:%.*]], <2 x i64> undef, <2 x i32> <i32 1, i32 0>
11; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]]
12; CHECK-NEXT:    [[TMP4:%.*]] = sub <2 x i64> [[TMP1]], [[TMP2]]
13; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i32> <i32 0, i32 3>
14; CHECK-NEXT:    [[TMP6:%.*]] = add <2 x i64> [[V0]], [[V1]]
15; CHECK-NEXT:    [[TMP7:%.*]] = sub <2 x i64> [[V0]], [[V1]]
16; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], <2 x i32> <i32 0, i32 3>
17; CHECK-NEXT:    [[TMP9:%.*]] = add <2 x i64> [[TMP8]], [[TMP5]]
18; CHECK-NEXT:    ret <2 x i64> [[TMP9]]
19;
20  %v0.0 = extractelement <2 x i64> %v0, i32 0
21  %v0.1 = extractelement <2 x i64> %v0, i32 1
22  %v1.0 = extractelement <2 x i64> %v1, i32 0
23  %v1.1 = extractelement <2 x i64> %v1, i32 1
24  %tmp0.0 = add i64 %v0.0, %v1.0
25  %tmp0.1 = add i64 %v0.1, %v1.1
26  %tmp1.0 = sub i64 %v0.0, %v1.0
27  %tmp1.1 = sub i64 %v0.1, %v1.1
28  %tmp2.0 = add i64 %tmp0.0, %tmp0.1
29  %tmp2.1 = add i64 %tmp1.0, %tmp1.1
30  %tmp3.0 = insertelement <2 x i64> undef, i64 %tmp2.0, i32 0
31  %tmp3.1 = insertelement <2 x i64> %tmp3.0, i64 %tmp2.1, i32 1
32  ret <2 x i64> %tmp3.1
33}
34
35define void @store_chain_v2i64(i64* %a, i64* %b, i64* %c) {
36; CHECK-LABEL: @store_chain_v2i64(
37; CHECK-NEXT:    [[A_1:%.*]] = getelementptr i64, i64* [[A:%.*]], i64 1
38; CHECK-NEXT:    [[B_1:%.*]] = getelementptr i64, i64* [[B:%.*]], i64 1
39; CHECK-NEXT:    [[C_1:%.*]] = getelementptr i64, i64* [[C:%.*]], i64 1
40; CHECK-NEXT:    [[V0_0:%.*]] = load i64, i64* [[A]], align 8
41; CHECK-NEXT:    [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8
42; CHECK-NEXT:    [[V1_0:%.*]] = load i64, i64* [[B]], align 8
43; CHECK-NEXT:    [[V1_1:%.*]] = load i64, i64* [[B_1]], align 8
44; CHECK-NEXT:    [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
45; CHECK-NEXT:    [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
46; CHECK-NEXT:    [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
47; CHECK-NEXT:    [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
48; CHECK-NEXT:    [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
49; CHECK-NEXT:    [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
50; CHECK-NEXT:    store i64 [[TMP2_0]], i64* [[C]], align 8
51; CHECK-NEXT:    store i64 [[TMP2_1]], i64* [[C_1]], align 8
52; CHECK-NEXT:    ret void
53;
54  %a.0 = getelementptr i64, i64* %a, i64 0
55  %a.1 = getelementptr i64, i64* %a, i64 1
56  %b.0 = getelementptr i64, i64* %b, i64 0
57  %b.1 = getelementptr i64, i64* %b, i64 1
58  %c.0 = getelementptr i64, i64* %c, i64 0
59  %c.1 = getelementptr i64, i64* %c, i64 1
60  %v0.0 = load i64, i64* %a.0, align 8
61  %v0.1 = load i64, i64* %a.1, align 8
62  %v1.0 = load i64, i64* %b.0, align 8
63  %v1.1 = load i64, i64* %b.1, align 8
64  %tmp0.0 = add i64 %v0.0, %v1.0
65  %tmp0.1 = add i64 %v0.1, %v1.1
66  %tmp1.0 = sub i64 %v0.0, %v1.0
67  %tmp1.1 = sub i64 %v0.1, %v1.1
68  %tmp2.0 = add i64 %tmp0.0, %tmp0.1
69  %tmp2.1 = add i64 %tmp1.0, %tmp1.1
70  store i64 %tmp2.0, i64* %c.0, align 8
71  store i64 %tmp2.1, i64* %c.1, align 8
72  ret void
73}
74
75define <4 x i32> @build_vec_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
76; CHECK-LABEL: @build_vec_v4i32(
77; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
78; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
79; CHECK-NEXT:    [[TMP3:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
80; CHECK-NEXT:    [[TMP4:%.*]] = sub <4 x i32> [[TMP1]], [[TMP2]]
81; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
82; CHECK-NEXT:    [[TMP6:%.*]] = add <4 x i32> [[V0]], [[V1]]
83; CHECK-NEXT:    [[TMP7:%.*]] = sub <4 x i32> [[V0]], [[V1]]
84; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
85; CHECK-NEXT:    [[TMP9:%.*]] = add <4 x i32> [[TMP8]], [[TMP5]]
86; CHECK-NEXT:    ret <4 x i32> [[TMP9]]
87;
88  %v0.0 = extractelement <4 x i32> %v0, i32 0
89  %v0.1 = extractelement <4 x i32> %v0, i32 1
90  %v0.2 = extractelement <4 x i32> %v0, i32 2
91  %v0.3 = extractelement <4 x i32> %v0, i32 3
92  %v1.0 = extractelement <4 x i32> %v1, i32 0
93  %v1.1 = extractelement <4 x i32> %v1, i32 1
94  %v1.2 = extractelement <4 x i32> %v1, i32 2
95  %v1.3 = extractelement <4 x i32> %v1, i32 3
96  %tmp0.0 = add i32 %v0.0, %v1.0
97  %tmp0.1 = add i32 %v0.1, %v1.1
98  %tmp0.2 = add i32 %v0.2, %v1.2
99  %tmp0.3 = add i32 %v0.3, %v1.3
100  %tmp1.0 = sub i32 %v0.0, %v1.0
101  %tmp1.1 = sub i32 %v0.1, %v1.1
102  %tmp1.2 = sub i32 %v0.2, %v1.2
103  %tmp1.3 = sub i32 %v0.3, %v1.3
104  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
105  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
106  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
107  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
108  %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
109  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
110  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
111  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
112  ret <4 x i32> %tmp3.3
113}
114
115define <4 x i32> @build_vec_v4i32_reuse_0(<2 x i32> %v0, <2 x i32> %v1) {
116; CHECK-LABEL: @build_vec_v4i32_reuse_0(
117; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 0>
118; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i32> [[V1:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 0>
119; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i32> [[TMP1]], [[TMP2]]
120; CHECK-NEXT:    [[TMP4:%.*]] = sub <2 x i32> [[TMP1]], [[TMP2]]
121; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> <i32 0, i32 3>
122; CHECK-NEXT:    [[TMP6:%.*]] = add <2 x i32> [[V0]], [[V1]]
123; CHECK-NEXT:    [[TMP7:%.*]] = sub <2 x i32> [[V0]], [[V1]]
124; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], <2 x i32> <i32 0, i32 3>
125; CHECK-NEXT:    [[TMP9:%.*]] = add <2 x i32> [[TMP8]], [[TMP5]]
126; CHECK-NEXT:    [[TMP3_3:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
127; CHECK-NEXT:    ret <4 x i32> [[TMP3_3]]
128;
129  %v0.0 = extractelement <2 x i32> %v0, i32 0
130  %v0.1 = extractelement <2 x i32> %v0, i32 1
131  %v1.0 = extractelement <2 x i32> %v1, i32 0
132  %v1.1 = extractelement <2 x i32> %v1, i32 1
133  %tmp0.0 = add i32 %v0.0, %v1.0
134  %tmp0.1 = add i32 %v0.1, %v1.1
135  %tmp1.0 = sub i32 %v0.0, %v1.0
136  %tmp1.1 = sub i32 %v0.1, %v1.1
137  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
138  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
139  %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
140  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
141  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.0, i32 2
142  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.1, i32 3
143  ret <4 x i32> %tmp3.3
144}
145
146define <4 x i32> @build_vec_v4i32_reuse_1(<2 x i32> %v0, <2 x i32> %v1) {
147; CHECK-LABEL: @build_vec_v4i32_reuse_1(
148; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 1
149; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[V1]], i32 0
150; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 1
151; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i32> [[V0]], i32 0
152; CHECK-NEXT:    [[TMP0_0:%.*]] = add i32 [[TMP4]], [[TMP2]]
153; CHECK-NEXT:    [[TMP0_1:%.*]] = add i32 [[TMP3]], [[TMP1]]
154; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i32> [[V0]], [[V1]]
155; CHECK-NEXT:    [[TMP1_0:%.*]] = sub i32 [[TMP0_0]], [[TMP0_1]]
156; CHECK-NEXT:    [[TMP1_1:%.*]] = sub i32 [[TMP0_0]], [[TMP0_1]]
157; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> undef, <2 x i32> <i32 1, i32 0>
158; CHECK-NEXT:    [[TMP7:%.*]] = sub <2 x i32> [[TMP5]], [[TMP6]]
159; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
160; CHECK-NEXT:    [[TMP2_0:%.*]] = insertelement <4 x i32> undef, i32 [[TMP1_0]], i32 0
161; CHECK-NEXT:    [[TMP2_1:%.*]] = insertelement <4 x i32> [[TMP2_0]], i32 [[TMP1_1]], i32 1
162; CHECK-NEXT:    [[TMP2_3:%.*]] = shufflevector <4 x i32> [[TMP2_1]], <4 x i32> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
163; CHECK-NEXT:    ret <4 x i32> [[TMP2_3]]
164;
165  %v0.0 = extractelement <2 x i32> %v0, i32 0
166  %v0.1 = extractelement <2 x i32> %v0, i32 1
167  %v1.0 = extractelement <2 x i32> %v1, i32 0
168  %v1.1 = extractelement <2 x i32> %v1, i32 1
169  %tmp0.0 = add i32 %v0.0, %v1.0
170  %tmp0.1 = add i32 %v0.1, %v1.1
171  %tmp0.2 = xor i32 %v0.0, %v1.0
172  %tmp0.3 = xor i32 %v0.1, %v1.1
173  %tmp1.0 = sub i32 %tmp0.0, %tmp0.1
174  %tmp1.1 = sub i32 %tmp0.0, %tmp0.1
175  %tmp1.2 = sub i32 %tmp0.2, %tmp0.3
176  %tmp1.3 = sub i32 %tmp0.3, %tmp0.2
177  %tmp2.0 = insertelement <4 x i32> undef, i32 %tmp1.0, i32 0
178  %tmp2.1 = insertelement <4 x i32> %tmp2.0, i32 %tmp1.1, i32 1
179  %tmp2.2 = insertelement <4 x i32> %tmp2.1, i32 %tmp1.2, i32 2
180  %tmp2.3 = insertelement <4 x i32> %tmp2.2, i32 %tmp1.3, i32 3
181  ret <4 x i32> %tmp2.3
182}
183
184define <4 x i32> @build_vec_v4i32_3_binops(<2 x i32> %v0, <2 x i32> %v1) {
185; CHECK-LABEL: @build_vec_v4i32_3_binops(
186; CHECK-NEXT:    [[V0_0:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 0
187; CHECK-NEXT:    [[V0_1:%.*]] = extractelement <2 x i32> [[V0]], i32 1
188; CHECK-NEXT:    [[V1_0:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 0
189; CHECK-NEXT:    [[V1_1:%.*]] = extractelement <2 x i32> [[V1]], i32 1
190; CHECK-NEXT:    [[TMP0_0:%.*]] = add i32 [[V0_0]], [[V1_0]]
191; CHECK-NEXT:    [[TMP0_1:%.*]] = add i32 [[V0_1]], [[V1_1]]
192; CHECK-NEXT:    [[TMP1_0:%.*]] = mul i32 [[V0_0]], [[V1_0]]
193; CHECK-NEXT:    [[TMP1_1:%.*]] = mul i32 [[V0_1]], [[V1_1]]
194; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[V0]], [[V1]]
195; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
196; CHECK-NEXT:    [[TMP3:%.*]] = xor <2 x i32> [[V0]], [[V1]]
197; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
198; CHECK-NEXT:    [[TMP2_0:%.*]] = add i32 [[TMP0_0]], [[TMP0_1]]
199; CHECK-NEXT:    [[TMP2_1:%.*]] = add i32 [[TMP1_0]], [[TMP1_1]]
200; CHECK-NEXT:    [[TMP5:%.*]] = add <2 x i32> [[TMP2]], [[TMP4]]
201; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
202; CHECK-NEXT:    [[TMP3_0:%.*]] = insertelement <4 x i32> undef, i32 [[TMP2_0]], i32 0
203; CHECK-NEXT:    [[TMP3_1:%.*]] = insertelement <4 x i32> [[TMP3_0]], i32 [[TMP2_1]], i32 1
204; CHECK-NEXT:    [[TMP3_3:%.*]] = shufflevector <4 x i32> [[TMP3_1]], <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
205; CHECK-NEXT:    ret <4 x i32> [[TMP3_3]]
206;
207  %v0.0 = extractelement <2 x i32> %v0, i32 0
208  %v0.1 = extractelement <2 x i32> %v0, i32 1
209  %v1.0 = extractelement <2 x i32> %v1, i32 0
210  %v1.1 = extractelement <2 x i32> %v1, i32 1
211  %tmp0.0 = add i32 %v0.0, %v1.0
212  %tmp0.1 = add i32 %v0.1, %v1.1
213  %tmp0.2 = xor i32 %v0.0, %v1.0
214  %tmp0.3 = xor i32 %v0.1, %v1.1
215  %tmp1.0 = mul i32 %v0.0, %v1.0
216  %tmp1.1 = mul i32 %v0.1, %v1.1
217  %tmp1.2 = xor i32 %v0.0, %v1.0
218  %tmp1.3 = xor i32 %v0.1, %v1.1
219  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
220  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
221  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
222  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
223  %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
224  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
225  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
226  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
227  ret <4 x i32> %tmp3.3
228}
229
230define i32 @reduction_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
231; CHECK-LABEL: @reduction_v4i32(
232; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
233; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
234; CHECK-NEXT:    [[TMP3:%.*]] = sub <4 x i32> [[TMP1]], [[TMP2]]
235; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
236; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
237; CHECK-NEXT:    [[TMP6:%.*]] = sub <4 x i32> [[V0]], [[V1]]
238; CHECK-NEXT:    [[TMP7:%.*]] = add <4 x i32> [[V0]], [[V1]]
239; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
240; CHECK-NEXT:    [[TMP9:%.*]] = add <4 x i32> [[TMP8]], [[TMP5]]
241; CHECK-NEXT:    [[TMP10:%.*]] = lshr <4 x i32> [[TMP9]], <i32 15, i32 15, i32 15, i32 15>
242; CHECK-NEXT:    [[TMP11:%.*]] = and <4 x i32> [[TMP10]], <i32 65537, i32 65537, i32 65537, i32 65537>
243; CHECK-NEXT:    [[TMP12:%.*]] = mul nuw <4 x i32> [[TMP11]], <i32 65535, i32 65535, i32 65535, i32 65535>
244; CHECK-NEXT:    [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP9]]
245; CHECK-NEXT:    [[TMP14:%.*]] = xor <4 x i32> [[TMP13]], [[TMP12]]
246; CHECK-NEXT:    [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP14]])
247; CHECK-NEXT:    ret i32 [[TMP15]]
248;
249  %v0.0 = extractelement <4 x i32> %v0, i32 0
250  %v0.1 = extractelement <4 x i32> %v0, i32 1
251  %v0.2 = extractelement <4 x i32> %v0, i32 2
252  %v0.3 = extractelement <4 x i32> %v0, i32 3
253  %v1.0 = extractelement <4 x i32> %v1, i32 0
254  %v1.1 = extractelement <4 x i32> %v1, i32 1
255  %v1.2 = extractelement <4 x i32> %v1, i32 2
256  %v1.3 = extractelement <4 x i32> %v1, i32 3
257  %tmp0.0 = add i32 %v0.0, %v1.0
258  %tmp0.1 = add i32 %v0.1, %v1.1
259  %tmp0.2 = add i32 %v0.2, %v1.2
260  %tmp0.3 = add i32 %v0.3, %v1.3
261  %tmp1.0 = sub i32 %v0.0, %v1.0
262  %tmp1.1 = sub i32 %v0.1, %v1.1
263  %tmp1.2 = sub i32 %v0.2, %v1.2
264  %tmp1.3 = sub i32 %v0.3, %v1.3
265  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
266  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
267  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
268  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
269  %tmp3.0 = lshr i32 %tmp2.0, 15
270  %tmp3.1 = lshr i32 %tmp2.1, 15
271  %tmp3.2 = lshr i32 %tmp2.2, 15
272  %tmp3.3 = lshr i32 %tmp2.3, 15
273  %tmp4.0 = and i32 %tmp3.0, 65537
274  %tmp4.1 = and i32 %tmp3.1, 65537
275  %tmp4.2 = and i32 %tmp3.2, 65537
276  %tmp4.3 = and i32 %tmp3.3, 65537
277  %tmp5.0 = mul nuw i32 %tmp4.0, 65535
278  %tmp5.1 = mul nuw i32 %tmp4.1, 65535
279  %tmp5.2 = mul nuw i32 %tmp4.2, 65535
280  %tmp5.3 = mul nuw i32 %tmp4.3, 65535
281  %tmp6.0 = add i32 %tmp5.0, %tmp2.0
282  %tmp6.1 = add i32 %tmp5.1, %tmp2.1
283  %tmp6.2 = add i32 %tmp5.2, %tmp2.2
284  %tmp6.3 = add i32 %tmp5.3, %tmp2.3
285  %tmp7.0 = xor i32 %tmp6.0, %tmp5.0
286  %tmp7.1 = xor i32 %tmp6.1, %tmp5.1
287  %tmp7.2 = xor i32 %tmp6.2, %tmp5.2
288  %tmp7.3 = xor i32 %tmp6.3, %tmp5.3
289  %reduce.0 = add i32 %tmp7.1, %tmp7.0
290  %reduce.1 = add i32 %reduce.0, %tmp7.2
291  %reduce.2 = add i32 %reduce.1, %tmp7.3
292  ret i32 %reduce.2
293}
294