1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -O2 -S < %s -enable-new-pm=0 | FileCheck %s
3; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
4
5define i64 @PR36760(i64 %a) {
6; CHECK-LABEL: @PR36760(
7; CHECK-NEXT:  entry:
8; CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.smax.i64(i64 [[A:%.*]], i64 0)
9; CHECK-NEXT:    ret i64 [[TMP0]]
10;
11entry:
12  %retval = alloca i64, align 8
13  %a.addr = alloca i64, align 8
14  store i64 %a, i64* %a.addr, align 8
15  %0 = load i64, i64* %a.addr, align 8
16  %cmp = icmp slt i64 %0, 0
17  br i1 %cmp, label %if.then, label %if.end
18
19if.then:
20  store i64 0, i64* %retval, align 8
21  br label %return
22
23if.end:
24  %1 = load i64, i64* %a.addr, align 8
25  %shr = ashr i64 %1, 63
26  %2 = load i64, i64* %a.addr, align 8
27  %xor = xor i64 %shr, %2
28  store i64 %xor, i64* %retval, align 8
29  br label %return
30
31return:
32  %3 = load i64, i64* %retval, align 8
33  ret i64 %3
34}
35
36define i64 @PR36760_2(i64 %a) #0 {
37; CHECK-LABEL: @PR36760_2(
38; CHECK-NEXT:  entry:
39; CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.smin.i64(i64 [[A:%.*]], i64 -1)
40; CHECK-NEXT:    [[TMP1:%.*]] = xor i64 [[TMP0]], -1
41; CHECK-NEXT:    ret i64 [[TMP1]]
42;
43entry:
44  %retval = alloca i64, align 8
45  %a.addr = alloca i64, align 8
46  store i64 %a, i64* %a.addr, align 8
47  %0 = load i64, i64* %a.addr, align 8
48  %cmp = icmp sge i64 %0, 0
49  br i1 %cmp, label %if.then, label %if.end
50
51if.then:                                          ; preds = %entry
52  store i64 0, i64* %retval, align 8
53  br label %return
54
55if.end:                                           ; preds = %entry
56  %1 = load i64, i64* %a.addr, align 8
57  %shr = ashr i64 %1, 63
58  %2 = load i64, i64* %a.addr, align 8
59  %xor = xor i64 %shr, %2
60  store i64 %xor, i64* %retval, align 8
61  br label %return
62
63return:                                           ; preds = %if.end, %if.then
64  %3 = load i64, i64* %retval, align 8
65  ret i64 %3
66}
67