1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -O2 -S < %s | FileCheck %s 3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64--" 6 7define float @test_merge_allof_v4sf(<4 x float> %t) { 8; CHECK-LABEL: @test_merge_allof_v4sf( 9; CHECK-NEXT: entry: 10; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 11; CHECK-NEXT: [[TMP0:%.*]] = fcmp uge <4 x float> [[T_FR]], zeroinitializer 12; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 13; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 14; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]] 15; CHECK: lor.lhs.false: 16; CHECK-NEXT: [[TMP3:%.*]] = fcmp ule <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 17; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 18; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 19; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 20; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[T_FR]], [[SHIFT]] 21; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i64 0 22; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]] 23; CHECK-NEXT: br label [[RETURN]] 24; CHECK: return: 25; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[LOR_LHS_FALSE]] ] 26; CHECK-NEXT: ret float [[RETVAL_0]] 27; 28entry: 29 %vecext = extractelement <4 x float> %t, i32 0 30 %conv = fpext float %vecext to double 31 %cmp = fcmp olt double %conv, 0.000000e+00 32 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false 33 34land.lhs.true: 35 %vecext2 = extractelement <4 x float> %t, i32 1 36 %conv3 = fpext float %vecext2 to double 37 %cmp4 = fcmp olt double %conv3, 0.000000e+00 38 br i1 %cmp4, label %land.lhs.true6, label %lor.lhs.false 39 40land.lhs.true6: 41 %vecext7 = extractelement <4 x float> %t, i32 2 42 %conv8 = fpext float %vecext7 to double 43 %cmp9 = fcmp olt double %conv8, 0.000000e+00 44 br i1 %cmp9, label %land.lhs.true11, label %lor.lhs.false 45 46land.lhs.true11: 47 %vecext12 = extractelement <4 x float> %t, i32 3 48 %conv13 = fpext float %vecext12 to double 49 %cmp14 = fcmp olt double %conv13, 0.000000e+00 50 br i1 %cmp14, label %if.then, label %lor.lhs.false 51 52lor.lhs.false: 53 %vecext16 = extractelement <4 x float> %t, i32 0 54 %conv17 = fpext float %vecext16 to double 55 %cmp18 = fcmp ogt double %conv17, 1.000000e+00 56 br i1 %cmp18, label %land.lhs.true20, label %if.end 57 58land.lhs.true20: 59 %vecext21 = extractelement <4 x float> %t, i32 1 60 %conv22 = fpext float %vecext21 to double 61 %cmp23 = fcmp ogt double %conv22, 1.000000e+00 62 br i1 %cmp23, label %land.lhs.true25, label %if.end 63 64land.lhs.true25: 65 %vecext26 = extractelement <4 x float> %t, i32 2 66 %conv27 = fpext float %vecext26 to double 67 %cmp28 = fcmp ogt double %conv27, 1.000000e+00 68 br i1 %cmp28, label %land.lhs.true30, label %if.end 69 70land.lhs.true30: 71 %vecext31 = extractelement <4 x float> %t, i32 3 72 %conv32 = fpext float %vecext31 to double 73 %cmp33 = fcmp ogt double %conv32, 1.000000e+00 74 br i1 %cmp33, label %if.then, label %if.end 75 76if.then: 77 br label %return 78 79if.end: 80 %vecext35 = extractelement <4 x float> %t, i32 0 81 %vecext36 = extractelement <4 x float> %t, i32 1 82 %add = fadd float %vecext35, %vecext36 83 br label %return 84 85return: 86 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %add, %if.end ] 87 ret float %retval.0 88} 89 90define float @test_merge_anyof_v4sf(<4 x float> %t) { 91; CHECK-LABEL: @test_merge_anyof_v4sf( 92; CHECK-NEXT: entry: 93; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 94; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer 95; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 96; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i1> [[TMP1]], [[TMP0]] 97; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 98; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP3]], 0 99; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 100; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[T_FR]], [[SHIFT]] 101; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP4]], i64 0 102; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[DOTNOT]], float [[ADD]], float 0.000000e+00 103; CHECK-NEXT: ret float [[RETVAL_0]] 104; 105entry: 106 %vecext = extractelement <4 x float> %t, i32 0 107 %conv = fpext float %vecext to double 108 %cmp = fcmp olt double %conv, 0.000000e+00 109 br i1 %cmp, label %if.then, label %lor.lhs.false 110 111lor.lhs.false: 112 %vecext2 = extractelement <4 x float> %t, i32 1 113 %conv3 = fpext float %vecext2 to double 114 %cmp4 = fcmp olt double %conv3, 0.000000e+00 115 br i1 %cmp4, label %if.then, label %lor.lhs.false6 116 117lor.lhs.false6: 118 %vecext7 = extractelement <4 x float> %t, i32 2 119 %conv8 = fpext float %vecext7 to double 120 %cmp9 = fcmp olt double %conv8, 0.000000e+00 121 br i1 %cmp9, label %if.then, label %lor.lhs.false11 122 123lor.lhs.false11: 124 %vecext12 = extractelement <4 x float> %t, i32 3 125 %conv13 = fpext float %vecext12 to double 126 %cmp14 = fcmp olt double %conv13, 0.000000e+00 127 br i1 %cmp14, label %if.then, label %lor.lhs.false16 128 129lor.lhs.false16: 130 %vecext17 = extractelement <4 x float> %t, i32 0 131 %conv18 = fpext float %vecext17 to double 132 %cmp19 = fcmp ogt double %conv18, 1.000000e+00 133 br i1 %cmp19, label %if.then, label %lor.lhs.false21 134 135lor.lhs.false21: 136 %vecext22 = extractelement <4 x float> %t, i32 1 137 %conv23 = fpext float %vecext22 to double 138 %cmp24 = fcmp ogt double %conv23, 1.000000e+00 139 br i1 %cmp24, label %if.then, label %lor.lhs.false26 140 141lor.lhs.false26: 142 %vecext27 = extractelement <4 x float> %t, i32 2 143 %conv28 = fpext float %vecext27 to double 144 %cmp29 = fcmp ogt double %conv28, 1.000000e+00 145 br i1 %cmp29, label %if.then, label %lor.lhs.false31 146 147lor.lhs.false31: 148 %vecext32 = extractelement <4 x float> %t, i32 3 149 %conv33 = fpext float %vecext32 to double 150 %cmp34 = fcmp ogt double %conv33, 1.000000e+00 151 br i1 %cmp34, label %if.then, label %if.end 152 153if.then: 154 br label %return 155 156if.end: 157 %vecext36 = extractelement <4 x float> %t, i32 0 158 %vecext37 = extractelement <4 x float> %t, i32 1 159 %add = fadd float %vecext36, %vecext37 160 br label %return 161 162return: 163 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %add, %if.end ] 164 ret float %retval.0 165} 166 167define float @test_separate_allof_v4sf(<4 x float> %t) { 168; CHECK-LABEL: @test_separate_allof_v4sf( 169; CHECK-NEXT: entry: 170; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 171; CHECK-NEXT: [[TMP0:%.*]] = fcmp uge <4 x float> [[T_FR]], zeroinitializer 172; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 173; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 174; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]] 175; CHECK: if.end: 176; CHECK-NEXT: [[TMP3:%.*]] = fcmp ule <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 177; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 178; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 179; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 180; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[T_FR]], [[SHIFT]] 181; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i64 0 182; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]] 183; CHECK-NEXT: br label [[RETURN]] 184; CHECK: return: 185; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 186; CHECK-NEXT: ret float [[RETVAL_0]] 187; 188entry: 189 %vecext = extractelement <4 x float> %t, i32 0 190 %conv = fpext float %vecext to double 191 %cmp = fcmp olt double %conv, 0.000000e+00 192 br i1 %cmp, label %land.lhs.true, label %if.end 193 194land.lhs.true: 195 %vecext2 = extractelement <4 x float> %t, i32 1 196 %conv3 = fpext float %vecext2 to double 197 %cmp4 = fcmp olt double %conv3, 0.000000e+00 198 br i1 %cmp4, label %land.lhs.true6, label %if.end 199 200land.lhs.true6: 201 %vecext7 = extractelement <4 x float> %t, i32 2 202 %conv8 = fpext float %vecext7 to double 203 %cmp9 = fcmp olt double %conv8, 0.000000e+00 204 br i1 %cmp9, label %land.lhs.true11, label %if.end 205 206land.lhs.true11: 207 %vecext12 = extractelement <4 x float> %t, i32 3 208 %conv13 = fpext float %vecext12 to double 209 %cmp14 = fcmp olt double %conv13, 0.000000e+00 210 br i1 %cmp14, label %if.then, label %if.end 211 212if.then: 213 br label %return 214 215if.end: 216 %vecext16 = extractelement <4 x float> %t, i32 0 217 %conv17 = fpext float %vecext16 to double 218 %cmp18 = fcmp ogt double %conv17, 1.000000e+00 219 br i1 %cmp18, label %land.lhs.true20, label %if.end36 220 221land.lhs.true20: 222 %vecext21 = extractelement <4 x float> %t, i32 1 223 %conv22 = fpext float %vecext21 to double 224 %cmp23 = fcmp ogt double %conv22, 1.000000e+00 225 br i1 %cmp23, label %land.lhs.true25, label %if.end36 226 227land.lhs.true25: 228 %vecext26 = extractelement <4 x float> %t, i32 2 229 %conv27 = fpext float %vecext26 to double 230 %cmp28 = fcmp ogt double %conv27, 1.000000e+00 231 br i1 %cmp28, label %land.lhs.true30, label %if.end36 232 233land.lhs.true30: 234 %vecext31 = extractelement <4 x float> %t, i32 3 235 %conv32 = fpext float %vecext31 to double 236 %cmp33 = fcmp ogt double %conv32, 1.000000e+00 237 br i1 %cmp33, label %if.then35, label %if.end36 238 239if.then35: 240 br label %return 241 242if.end36: 243 %vecext37 = extractelement <4 x float> %t, i32 0 244 %vecext38 = extractelement <4 x float> %t, i32 1 245 %add = fadd float %vecext37, %vecext38 246 br label %return 247 248return: 249 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ 0.000000e+00, %if.then35 ], [ %add, %if.end36 ] 250 ret float %retval.0 251} 252 253define float @test_separate_anyof_v4sf(<4 x float> %t) { 254; CHECK-LABEL: @test_separate_anyof_v4sf( 255; CHECK-NEXT: entry: 256; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 257; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer 258; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 259; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0 260; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[RETURN:%.*]] 261; CHECK: if.end: 262; CHECK-NEXT: [[TMP2:%.*]] = fcmp ogt <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 263; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 264; CHECK-NEXT: [[DOTNOT6:%.*]] = icmp eq i4 [[TMP3]], 0 265; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 266; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[T_FR]], [[SHIFT]] 267; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP4]], i64 0 268; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[DOTNOT6]], float [[ADD]], float 0.000000e+00 269; CHECK-NEXT: br label [[RETURN]] 270; CHECK: return: 271; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 272; CHECK-NEXT: ret float [[RETVAL_0]] 273; 274entry: 275 %vecext = extractelement <4 x float> %t, i32 0 276 %conv = fpext float %vecext to double 277 %cmp = fcmp olt double %conv, 0.000000e+00 278 br i1 %cmp, label %if.then, label %lor.lhs.false 279 280lor.lhs.false: 281 %vecext2 = extractelement <4 x float> %t, i32 1 282 %conv3 = fpext float %vecext2 to double 283 %cmp4 = fcmp olt double %conv3, 0.000000e+00 284 br i1 %cmp4, label %if.then, label %lor.lhs.false6 285 286lor.lhs.false6: 287 %vecext7 = extractelement <4 x float> %t, i32 2 288 %conv8 = fpext float %vecext7 to double 289 %cmp9 = fcmp olt double %conv8, 0.000000e+00 290 br i1 %cmp9, label %if.then, label %lor.lhs.false11 291 292lor.lhs.false11: 293 %vecext12 = extractelement <4 x float> %t, i32 3 294 %conv13 = fpext float %vecext12 to double 295 %cmp14 = fcmp olt double %conv13, 0.000000e+00 296 br i1 %cmp14, label %if.then, label %if.end 297 298if.then: 299 br label %return 300 301if.end: 302 %vecext16 = extractelement <4 x float> %t, i32 0 303 %conv17 = fpext float %vecext16 to double 304 %cmp18 = fcmp ogt double %conv17, 1.000000e+00 305 br i1 %cmp18, label %if.then35, label %lor.lhs.false20 306 307lor.lhs.false20: 308 %vecext21 = extractelement <4 x float> %t, i32 1 309 %conv22 = fpext float %vecext21 to double 310 %cmp23 = fcmp ogt double %conv22, 1.000000e+00 311 br i1 %cmp23, label %if.then35, label %lor.lhs.false25 312 313lor.lhs.false25: 314 %vecext26 = extractelement <4 x float> %t, i32 2 315 %conv27 = fpext float %vecext26 to double 316 %cmp28 = fcmp ogt double %conv27, 1.000000e+00 317 br i1 %cmp28, label %if.then35, label %lor.lhs.false30 318 319lor.lhs.false30: 320 %vecext31 = extractelement <4 x float> %t, i32 3 321 %conv32 = fpext float %vecext31 to double 322 %cmp33 = fcmp ogt double %conv32, 1.000000e+00 323 br i1 %cmp33, label %if.then35, label %if.end36 324 325if.then35: 326 br label %return 327 328if.end36: 329 %vecext37 = extractelement <4 x float> %t, i32 0 330 %vecext38 = extractelement <4 x float> %t, i32 1 331 %add = fadd float %vecext37, %vecext38 332 br label %return 333 334return: 335 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ 0.000000e+00, %if.then35 ], [ %add, %if.end36 ] 336 ret float %retval.0 337} 338 339define float @test_merge_allof_v4si(<4 x i32> %t) { 340; CHECK-LABEL: @test_merge_allof_v4si( 341; CHECK-NEXT: entry: 342; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 343; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <4 x i32> [[T_FR]], zeroinitializer 344; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 345; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 346; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 256, i32 256, i32 256, i32 256> 347; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 348; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 349; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[TMP2]], [[TMP5]] 350; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 351; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[T_FR]], [[SHIFT]] 352; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i64 0 353; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float 354; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], float 0.000000e+00, float [[CONV]] 355; CHECK-NEXT: ret float [[RETVAL_0]] 356; 357entry: 358 %vecext = extractelement <4 x i32> %t, i32 0 359 %cmp = icmp slt i32 %vecext, 1 360 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false 361 362land.lhs.true: 363 %vecext1 = extractelement <4 x i32> %t, i32 1 364 %cmp2 = icmp slt i32 %vecext1, 1 365 br i1 %cmp2, label %land.lhs.true3, label %lor.lhs.false 366 367land.lhs.true3: 368 %vecext4 = extractelement <4 x i32> %t, i32 2 369 %cmp5 = icmp slt i32 %vecext4, 1 370 br i1 %cmp5, label %land.lhs.true6, label %lor.lhs.false 371 372land.lhs.true6: 373 %vecext7 = extractelement <4 x i32> %t, i32 3 374 %cmp8 = icmp slt i32 %vecext7, 1 375 br i1 %cmp8, label %if.then, label %lor.lhs.false 376 377lor.lhs.false: 378 %vecext9 = extractelement <4 x i32> %t, i32 0 379 %cmp10 = icmp sgt i32 %vecext9, 255 380 br i1 %cmp10, label %land.lhs.true11, label %if.end 381 382land.lhs.true11: 383 %vecext12 = extractelement <4 x i32> %t, i32 1 384 %cmp13 = icmp sgt i32 %vecext12, 255 385 br i1 %cmp13, label %land.lhs.true14, label %if.end 386 387land.lhs.true14: 388 %vecext15 = extractelement <4 x i32> %t, i32 2 389 %cmp16 = icmp sgt i32 %vecext15, 255 390 br i1 %cmp16, label %land.lhs.true17, label %if.end 391 392land.lhs.true17: 393 %vecext18 = extractelement <4 x i32> %t, i32 3 394 %cmp19 = icmp sgt i32 %vecext18, 255 395 br i1 %cmp19, label %if.then, label %if.end 396 397if.then: 398 br label %return 399 400if.end: 401 %vecext20 = extractelement <4 x i32> %t, i32 0 402 %vecext21 = extractelement <4 x i32> %t, i32 1 403 %add = add nsw i32 %vecext20, %vecext21 404 %conv = sitofp i32 %add to float 405 br label %return 406 407return: 408 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %conv, %if.end ] 409 ret float %retval.0 410} 411 412define float @test_merge_anyof_v4si(<4 x i32> %t) { 413; CHECK-LABEL: @test_merge_anyof_v4si( 414; CHECK-NEXT: entry: 415; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 416; CHECK-NEXT: [[TMP0:%.*]] = add <4 x i32> [[T_FR]], <i32 -256, i32 -256, i32 -256, i32 -256> 417; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <4 x i32> [[TMP0]], <i32 -255, i32 -255, i32 -255, i32 -255> 418; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i1> [[TMP1]] to i4 419; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP2]], 0 420; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 421; CHECK-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[T_FR]], [[SHIFT]] 422; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 423; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float 424; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[DOTNOT]], float [[CONV]], float 0.000000e+00 425; CHECK-NEXT: ret float [[RETVAL_0]] 426; 427entry: 428 %vecext = extractelement <4 x i32> %t, i32 0 429 %cmp = icmp slt i32 %vecext, 1 430 br i1 %cmp, label %if.then, label %lor.lhs.false 431 432lor.lhs.false: 433 %vecext1 = extractelement <4 x i32> %t, i32 1 434 %cmp2 = icmp slt i32 %vecext1, 1 435 br i1 %cmp2, label %if.then, label %lor.lhs.false3 436 437lor.lhs.false3: 438 %vecext4 = extractelement <4 x i32> %t, i32 2 439 %cmp5 = icmp slt i32 %vecext4, 1 440 br i1 %cmp5, label %if.then, label %lor.lhs.false6 441 442lor.lhs.false6: 443 %vecext7 = extractelement <4 x i32> %t, i32 3 444 %cmp8 = icmp slt i32 %vecext7, 1 445 br i1 %cmp8, label %if.then, label %lor.lhs.false9 446 447lor.lhs.false9: 448 %vecext10 = extractelement <4 x i32> %t, i32 0 449 %cmp11 = icmp sgt i32 %vecext10, 255 450 br i1 %cmp11, label %if.then, label %lor.lhs.false12 451 452lor.lhs.false12: 453 %vecext13 = extractelement <4 x i32> %t, i32 1 454 %cmp14 = icmp sgt i32 %vecext13, 255 455 br i1 %cmp14, label %if.then, label %lor.lhs.false15 456 457lor.lhs.false15: 458 %vecext16 = extractelement <4 x i32> %t, i32 2 459 %cmp17 = icmp sgt i32 %vecext16, 255 460 br i1 %cmp17, label %if.then, label %lor.lhs.false18 461 462lor.lhs.false18: 463 %vecext19 = extractelement <4 x i32> %t, i32 3 464 %cmp20 = icmp sgt i32 %vecext19, 255 465 br i1 %cmp20, label %if.then, label %if.end 466 467if.then: 468 br label %return 469 470if.end: 471 %vecext21 = extractelement <4 x i32> %t, i32 0 472 %vecext22 = extractelement <4 x i32> %t, i32 1 473 %add = add nsw i32 %vecext21, %vecext22 474 %conv = sitofp i32 %add to float 475 br label %return 476 477return: 478 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %conv, %if.end ] 479 ret float %retval.0 480} 481 482define i32 @test_separate_allof_v4si(<4 x i32> %t) { 483; CHECK-LABEL: @test_separate_allof_v4si( 484; CHECK-NEXT: entry: 485; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 486; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <4 x i32> [[T_FR]], zeroinitializer 487; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 488; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 489; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]] 490; CHECK: if.end: 491; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 256, i32 256, i32 256, i32 256> 492; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 493; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 494; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 495; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[T_FR]], [[SHIFT]] 496; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i64 0 497; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], i32 0, i32 [[ADD]] 498; CHECK-NEXT: br label [[RETURN]] 499; CHECK: return: 500; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 501; CHECK-NEXT: ret i32 [[RETVAL_0]] 502; 503entry: 504 %vecext = extractelement <4 x i32> %t, i32 0 505 %cmp = icmp slt i32 %vecext, 1 506 br i1 %cmp, label %land.lhs.true, label %if.end 507 508land.lhs.true: 509 %vecext1 = extractelement <4 x i32> %t, i32 1 510 %cmp2 = icmp slt i32 %vecext1, 1 511 br i1 %cmp2, label %land.lhs.true3, label %if.end 512 513land.lhs.true3: 514 %vecext4 = extractelement <4 x i32> %t, i32 2 515 %cmp5 = icmp slt i32 %vecext4, 1 516 br i1 %cmp5, label %land.lhs.true6, label %if.end 517 518land.lhs.true6: 519 %vecext7 = extractelement <4 x i32> %t, i32 3 520 %cmp8 = icmp slt i32 %vecext7, 1 521 br i1 %cmp8, label %if.then, label %if.end 522 523if.then: 524 br label %return 525 526if.end: 527 %vecext9 = extractelement <4 x i32> %t, i32 0 528 %cmp10 = icmp sgt i32 %vecext9, 255 529 br i1 %cmp10, label %land.lhs.true11, label %if.end21 530 531land.lhs.true11: 532 %vecext12 = extractelement <4 x i32> %t, i32 1 533 %cmp13 = icmp sgt i32 %vecext12, 255 534 br i1 %cmp13, label %land.lhs.true14, label %if.end21 535 536land.lhs.true14: 537 %vecext15 = extractelement <4 x i32> %t, i32 2 538 %cmp16 = icmp sgt i32 %vecext15, 255 539 br i1 %cmp16, label %land.lhs.true17, label %if.end21 540 541land.lhs.true17: 542 %vecext18 = extractelement <4 x i32> %t, i32 3 543 %cmp19 = icmp sgt i32 %vecext18, 255 544 br i1 %cmp19, label %if.then20, label %if.end21 545 546if.then20: 547 br label %return 548 549if.end21: 550 %vecext22 = extractelement <4 x i32> %t, i32 0 551 %vecext23 = extractelement <4 x i32> %t, i32 1 552 %add = add nsw i32 %vecext22, %vecext23 553 br label %return 554 555return: 556 %retval.0 = phi i32 [ 0, %if.then ], [ 0, %if.then20 ], [ %add, %if.end21 ] 557 ret i32 %retval.0 558} 559 560define i32 @test_separate_anyof_v4si(<4 x i32> %t) { 561; CHECK-LABEL: @test_separate_anyof_v4si( 562; CHECK-NEXT: entry: 563; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 564; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 1, i32 1, i32 1, i32 1> 565; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 566; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0 567; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[RETURN:%.*]] 568; CHECK: if.end: 569; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt <4 x i32> [[T_FR]], <i32 255, i32 255, i32 255, i32 255> 570; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 571; CHECK-NEXT: [[DOTNOT6:%.*]] = icmp eq i4 [[TMP3]], 0 572; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 573; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[T_FR]], [[SHIFT]] 574; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0 575; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[DOTNOT6]], i32 [[ADD]], i32 0 576; CHECK-NEXT: br label [[RETURN]] 577; CHECK: return: 578; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 579; CHECK-NEXT: ret i32 [[RETVAL_0]] 580; 581entry: 582 %vecext = extractelement <4 x i32> %t, i32 0 583 %cmp = icmp slt i32 %vecext, 1 584 br i1 %cmp, label %if.then, label %lor.lhs.false 585 586lor.lhs.false: 587 %vecext1 = extractelement <4 x i32> %t, i32 1 588 %cmp2 = icmp slt i32 %vecext1, 1 589 br i1 %cmp2, label %if.then, label %lor.lhs.false3 590 591lor.lhs.false3: 592 %vecext4 = extractelement <4 x i32> %t, i32 2 593 %cmp5 = icmp slt i32 %vecext4, 1 594 br i1 %cmp5, label %if.then, label %lor.lhs.false6 595 596lor.lhs.false6: 597 %vecext7 = extractelement <4 x i32> %t, i32 3 598 %cmp8 = icmp slt i32 %vecext7, 1 599 br i1 %cmp8, label %if.then, label %if.end 600 601if.then: 602 br label %return 603 604if.end: 605 %vecext9 = extractelement <4 x i32> %t, i32 0 606 %cmp10 = icmp sgt i32 %vecext9, 255 607 br i1 %cmp10, label %if.then20, label %lor.lhs.false11 608 609lor.lhs.false11: 610 %vecext12 = extractelement <4 x i32> %t, i32 1 611 %cmp13 = icmp sgt i32 %vecext12, 255 612 br i1 %cmp13, label %if.then20, label %lor.lhs.false14 613 614lor.lhs.false14: 615 %vecext15 = extractelement <4 x i32> %t, i32 2 616 %cmp16 = icmp sgt i32 %vecext15, 255 617 br i1 %cmp16, label %if.then20, label %lor.lhs.false17 618 619lor.lhs.false17: 620 %vecext18 = extractelement <4 x i32> %t, i32 3 621 %cmp19 = icmp sgt i32 %vecext18, 255 622 br i1 %cmp19, label %if.then20, label %if.end21 623 624if.then20: 625 br label %return 626 627if.end21: 628 %vecext22 = extractelement <4 x i32> %t, i32 0 629 %vecext23 = extractelement <4 x i32> %t, i32 1 630 %add = add nsw i32 %vecext22, %vecext23 631 br label %return 632 633return: 634 %retval.0 = phi i32 [ 0, %if.then ], [ 0, %if.then20 ], [ %add, %if.end21 ] 635 ret i32 %retval.0 636} 637