1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -O2 -S < %s | FileCheck %s 3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64--" 6 7define float @test_merge_allof_v4sf(<4 x float> %t) { 8; CHECK-LABEL: @test_merge_allof_v4sf( 9; CHECK-NEXT: entry: 10; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 11; CHECK-NEXT: [[TMP0:%.*]] = fcmp uge <4 x float> [[T_FR]], zeroinitializer 12; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 13; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 14; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]] 15; CHECK: lor.lhs.false: 16; CHECK-NEXT: [[TMP3:%.*]] = fcmp ule <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 17; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 18; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 19; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 20; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR]] 21; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0 22; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]] 23; CHECK-NEXT: br label [[RETURN]] 24; CHECK: return: 25; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[LOR_LHS_FALSE]] ] 26; CHECK-NEXT: ret float [[RETVAL_0]] 27; 28entry: 29 %vecext = extractelement <4 x float> %t, i32 0 30 %conv = fpext float %vecext to double 31 %cmp = fcmp olt double %conv, 0.000000e+00 32 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false 33 34land.lhs.true: 35 %vecext2 = extractelement <4 x float> %t, i32 1 36 %conv3 = fpext float %vecext2 to double 37 %cmp4 = fcmp olt double %conv3, 0.000000e+00 38 br i1 %cmp4, label %land.lhs.true6, label %lor.lhs.false 39 40land.lhs.true6: 41 %vecext7 = extractelement <4 x float> %t, i32 2 42 %conv8 = fpext float %vecext7 to double 43 %cmp9 = fcmp olt double %conv8, 0.000000e+00 44 br i1 %cmp9, label %land.lhs.true11, label %lor.lhs.false 45 46land.lhs.true11: 47 %vecext12 = extractelement <4 x float> %t, i32 3 48 %conv13 = fpext float %vecext12 to double 49 %cmp14 = fcmp olt double %conv13, 0.000000e+00 50 br i1 %cmp14, label %if.then, label %lor.lhs.false 51 52lor.lhs.false: 53 %vecext16 = extractelement <4 x float> %t, i32 0 54 %conv17 = fpext float %vecext16 to double 55 %cmp18 = fcmp ogt double %conv17, 1.000000e+00 56 br i1 %cmp18, label %land.lhs.true20, label %if.end 57 58land.lhs.true20: 59 %vecext21 = extractelement <4 x float> %t, i32 1 60 %conv22 = fpext float %vecext21 to double 61 %cmp23 = fcmp ogt double %conv22, 1.000000e+00 62 br i1 %cmp23, label %land.lhs.true25, label %if.end 63 64land.lhs.true25: 65 %vecext26 = extractelement <4 x float> %t, i32 2 66 %conv27 = fpext float %vecext26 to double 67 %cmp28 = fcmp ogt double %conv27, 1.000000e+00 68 br i1 %cmp28, label %land.lhs.true30, label %if.end 69 70land.lhs.true30: 71 %vecext31 = extractelement <4 x float> %t, i32 3 72 %conv32 = fpext float %vecext31 to double 73 %cmp33 = fcmp ogt double %conv32, 1.000000e+00 74 br i1 %cmp33, label %if.then, label %if.end 75 76if.then: 77 br label %return 78 79if.end: 80 %vecext35 = extractelement <4 x float> %t, i32 0 81 %vecext36 = extractelement <4 x float> %t, i32 1 82 %add = fadd float %vecext35, %vecext36 83 br label %return 84 85return: 86 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %add, %if.end ] 87 ret float %retval.0 88} 89 90define float @test_merge_anyof_v4sf(<4 x float> %t) { 91; CHECK-LABEL: @test_merge_anyof_v4sf( 92; CHECK-NEXT: entry: 93; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[T:%.*]], i32 3 94; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[T]], i32 2 95; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[T]], i32 1 96; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[T]], i32 0 97; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T]] 98; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer 99; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 100; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i4 [[TMP5]], 0 101; CHECK-NEXT: [[CMP19:%.*]] = fcmp ogt float [[TMP3]], 1.000000e+00 102; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP19]] 103; CHECK-NEXT: [[CMP24:%.*]] = fcmp ogt float [[TMP2]], 1.000000e+00 104; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP24]] 105; CHECK-NEXT: [[CMP29:%.*]] = fcmp ogt float [[TMP1]], 1.000000e+00 106; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP29]] 107; CHECK-NEXT: [[CMP34:%.*]] = fcmp ogt float [[TMP0]], 1.000000e+00 108; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP34]] 109; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]] 110; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[ADD]] 111; CHECK-NEXT: ret float [[RETVAL_0]] 112; 113entry: 114 %vecext = extractelement <4 x float> %t, i32 0 115 %conv = fpext float %vecext to double 116 %cmp = fcmp olt double %conv, 0.000000e+00 117 br i1 %cmp, label %if.then, label %lor.lhs.false 118 119lor.lhs.false: 120 %vecext2 = extractelement <4 x float> %t, i32 1 121 %conv3 = fpext float %vecext2 to double 122 %cmp4 = fcmp olt double %conv3, 0.000000e+00 123 br i1 %cmp4, label %if.then, label %lor.lhs.false6 124 125lor.lhs.false6: 126 %vecext7 = extractelement <4 x float> %t, i32 2 127 %conv8 = fpext float %vecext7 to double 128 %cmp9 = fcmp olt double %conv8, 0.000000e+00 129 br i1 %cmp9, label %if.then, label %lor.lhs.false11 130 131lor.lhs.false11: 132 %vecext12 = extractelement <4 x float> %t, i32 3 133 %conv13 = fpext float %vecext12 to double 134 %cmp14 = fcmp olt double %conv13, 0.000000e+00 135 br i1 %cmp14, label %if.then, label %lor.lhs.false16 136 137lor.lhs.false16: 138 %vecext17 = extractelement <4 x float> %t, i32 0 139 %conv18 = fpext float %vecext17 to double 140 %cmp19 = fcmp ogt double %conv18, 1.000000e+00 141 br i1 %cmp19, label %if.then, label %lor.lhs.false21 142 143lor.lhs.false21: 144 %vecext22 = extractelement <4 x float> %t, i32 1 145 %conv23 = fpext float %vecext22 to double 146 %cmp24 = fcmp ogt double %conv23, 1.000000e+00 147 br i1 %cmp24, label %if.then, label %lor.lhs.false26 148 149lor.lhs.false26: 150 %vecext27 = extractelement <4 x float> %t, i32 2 151 %conv28 = fpext float %vecext27 to double 152 %cmp29 = fcmp ogt double %conv28, 1.000000e+00 153 br i1 %cmp29, label %if.then, label %lor.lhs.false31 154 155lor.lhs.false31: 156 %vecext32 = extractelement <4 x float> %t, i32 3 157 %conv33 = fpext float %vecext32 to double 158 %cmp34 = fcmp ogt double %conv33, 1.000000e+00 159 br i1 %cmp34, label %if.then, label %if.end 160 161if.then: 162 br label %return 163 164if.end: 165 %vecext36 = extractelement <4 x float> %t, i32 0 166 %vecext37 = extractelement <4 x float> %t, i32 1 167 %add = fadd float %vecext36, %vecext37 168 br label %return 169 170return: 171 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %add, %if.end ] 172 ret float %retval.0 173} 174 175define float @test_separate_allof_v4sf(<4 x float> %t) { 176; CHECK-LABEL: @test_separate_allof_v4sf( 177; CHECK-NEXT: entry: 178; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 179; CHECK-NEXT: [[TMP0:%.*]] = fcmp uge <4 x float> [[T_FR]], zeroinitializer 180; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 181; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 182; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]] 183; CHECK: if.end: 184; CHECK-NEXT: [[TMP3:%.*]] = fcmp ule <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 185; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 186; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 187; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 188; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR]] 189; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0 190; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]] 191; CHECK-NEXT: br label [[RETURN]] 192; CHECK: return: 193; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 194; CHECK-NEXT: ret float [[RETVAL_0]] 195; 196entry: 197 %vecext = extractelement <4 x float> %t, i32 0 198 %conv = fpext float %vecext to double 199 %cmp = fcmp olt double %conv, 0.000000e+00 200 br i1 %cmp, label %land.lhs.true, label %if.end 201 202land.lhs.true: 203 %vecext2 = extractelement <4 x float> %t, i32 1 204 %conv3 = fpext float %vecext2 to double 205 %cmp4 = fcmp olt double %conv3, 0.000000e+00 206 br i1 %cmp4, label %land.lhs.true6, label %if.end 207 208land.lhs.true6: 209 %vecext7 = extractelement <4 x float> %t, i32 2 210 %conv8 = fpext float %vecext7 to double 211 %cmp9 = fcmp olt double %conv8, 0.000000e+00 212 br i1 %cmp9, label %land.lhs.true11, label %if.end 213 214land.lhs.true11: 215 %vecext12 = extractelement <4 x float> %t, i32 3 216 %conv13 = fpext float %vecext12 to double 217 %cmp14 = fcmp olt double %conv13, 0.000000e+00 218 br i1 %cmp14, label %if.then, label %if.end 219 220if.then: 221 br label %return 222 223if.end: 224 %vecext16 = extractelement <4 x float> %t, i32 0 225 %conv17 = fpext float %vecext16 to double 226 %cmp18 = fcmp ogt double %conv17, 1.000000e+00 227 br i1 %cmp18, label %land.lhs.true20, label %if.end36 228 229land.lhs.true20: 230 %vecext21 = extractelement <4 x float> %t, i32 1 231 %conv22 = fpext float %vecext21 to double 232 %cmp23 = fcmp ogt double %conv22, 1.000000e+00 233 br i1 %cmp23, label %land.lhs.true25, label %if.end36 234 235land.lhs.true25: 236 %vecext26 = extractelement <4 x float> %t, i32 2 237 %conv27 = fpext float %vecext26 to double 238 %cmp28 = fcmp ogt double %conv27, 1.000000e+00 239 br i1 %cmp28, label %land.lhs.true30, label %if.end36 240 241land.lhs.true30: 242 %vecext31 = extractelement <4 x float> %t, i32 3 243 %conv32 = fpext float %vecext31 to double 244 %cmp33 = fcmp ogt double %conv32, 1.000000e+00 245 br i1 %cmp33, label %if.then35, label %if.end36 246 247if.then35: 248 br label %return 249 250if.end36: 251 %vecext37 = extractelement <4 x float> %t, i32 0 252 %vecext38 = extractelement <4 x float> %t, i32 1 253 %add = fadd float %vecext37, %vecext38 254 br label %return 255 256return: 257 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ 0.000000e+00, %if.then35 ], [ %add, %if.end36 ] 258 ret float %retval.0 259} 260 261define float @test_separate_anyof_v4sf(<4 x float> %t) { 262; CHECK-LABEL: @test_separate_anyof_v4sf( 263; CHECK-NEXT: entry: 264; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] 265; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer 266; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 267; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0 268; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[RETURN:%.*]] 269; CHECK: if.end: 270; CHECK-NEXT: [[TMP2:%.*]] = fcmp ogt <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> 271; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 272; CHECK-NEXT: [[DOTNOT7:%.*]] = icmp eq i4 [[TMP3]], 0 273; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 274; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR]] 275; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP4]], i32 0 276; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[DOTNOT7]], float [[ADD]], float 0.000000e+00 277; CHECK-NEXT: br label [[RETURN]] 278; CHECK: return: 279; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 280; CHECK-NEXT: ret float [[RETVAL_0]] 281; 282entry: 283 %vecext = extractelement <4 x float> %t, i32 0 284 %conv = fpext float %vecext to double 285 %cmp = fcmp olt double %conv, 0.000000e+00 286 br i1 %cmp, label %if.then, label %lor.lhs.false 287 288lor.lhs.false: 289 %vecext2 = extractelement <4 x float> %t, i32 1 290 %conv3 = fpext float %vecext2 to double 291 %cmp4 = fcmp olt double %conv3, 0.000000e+00 292 br i1 %cmp4, label %if.then, label %lor.lhs.false6 293 294lor.lhs.false6: 295 %vecext7 = extractelement <4 x float> %t, i32 2 296 %conv8 = fpext float %vecext7 to double 297 %cmp9 = fcmp olt double %conv8, 0.000000e+00 298 br i1 %cmp9, label %if.then, label %lor.lhs.false11 299 300lor.lhs.false11: 301 %vecext12 = extractelement <4 x float> %t, i32 3 302 %conv13 = fpext float %vecext12 to double 303 %cmp14 = fcmp olt double %conv13, 0.000000e+00 304 br i1 %cmp14, label %if.then, label %if.end 305 306if.then: 307 br label %return 308 309if.end: 310 %vecext16 = extractelement <4 x float> %t, i32 0 311 %conv17 = fpext float %vecext16 to double 312 %cmp18 = fcmp ogt double %conv17, 1.000000e+00 313 br i1 %cmp18, label %if.then35, label %lor.lhs.false20 314 315lor.lhs.false20: 316 %vecext21 = extractelement <4 x float> %t, i32 1 317 %conv22 = fpext float %vecext21 to double 318 %cmp23 = fcmp ogt double %conv22, 1.000000e+00 319 br i1 %cmp23, label %if.then35, label %lor.lhs.false25 320 321lor.lhs.false25: 322 %vecext26 = extractelement <4 x float> %t, i32 2 323 %conv27 = fpext float %vecext26 to double 324 %cmp28 = fcmp ogt double %conv27, 1.000000e+00 325 br i1 %cmp28, label %if.then35, label %lor.lhs.false30 326 327lor.lhs.false30: 328 %vecext31 = extractelement <4 x float> %t, i32 3 329 %conv32 = fpext float %vecext31 to double 330 %cmp33 = fcmp ogt double %conv32, 1.000000e+00 331 br i1 %cmp33, label %if.then35, label %if.end36 332 333if.then35: 334 br label %return 335 336if.end36: 337 %vecext37 = extractelement <4 x float> %t, i32 0 338 %vecext38 = extractelement <4 x float> %t, i32 1 339 %add = fadd float %vecext37, %vecext38 340 br label %return 341 342return: 343 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ 0.000000e+00, %if.then35 ], [ %add, %if.end36 ] 344 ret float %retval.0 345} 346 347define float @test_merge_allof_v4si(<4 x i32> %t) { 348; CHECK-LABEL: @test_merge_allof_v4si( 349; CHECK-NEXT: entry: 350; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 351; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <4 x i32> [[T_FR]], zeroinitializer 352; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 353; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 354; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 256, i32 256, i32 256, i32 256> 355; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 356; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 357; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[TMP2]], [[TMP5]] 358; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 359; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[T_FR]], [[SHIFT]] 360; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0 361; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float 362; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], float 0.000000e+00, float [[CONV]] 363; CHECK-NEXT: ret float [[RETVAL_0]] 364; 365entry: 366 %vecext = extractelement <4 x i32> %t, i32 0 367 %cmp = icmp slt i32 %vecext, 1 368 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false 369 370land.lhs.true: 371 %vecext1 = extractelement <4 x i32> %t, i32 1 372 %cmp2 = icmp slt i32 %vecext1, 1 373 br i1 %cmp2, label %land.lhs.true3, label %lor.lhs.false 374 375land.lhs.true3: 376 %vecext4 = extractelement <4 x i32> %t, i32 2 377 %cmp5 = icmp slt i32 %vecext4, 1 378 br i1 %cmp5, label %land.lhs.true6, label %lor.lhs.false 379 380land.lhs.true6: 381 %vecext7 = extractelement <4 x i32> %t, i32 3 382 %cmp8 = icmp slt i32 %vecext7, 1 383 br i1 %cmp8, label %if.then, label %lor.lhs.false 384 385lor.lhs.false: 386 %vecext9 = extractelement <4 x i32> %t, i32 0 387 %cmp10 = icmp sgt i32 %vecext9, 255 388 br i1 %cmp10, label %land.lhs.true11, label %if.end 389 390land.lhs.true11: 391 %vecext12 = extractelement <4 x i32> %t, i32 1 392 %cmp13 = icmp sgt i32 %vecext12, 255 393 br i1 %cmp13, label %land.lhs.true14, label %if.end 394 395land.lhs.true14: 396 %vecext15 = extractelement <4 x i32> %t, i32 2 397 %cmp16 = icmp sgt i32 %vecext15, 255 398 br i1 %cmp16, label %land.lhs.true17, label %if.end 399 400land.lhs.true17: 401 %vecext18 = extractelement <4 x i32> %t, i32 3 402 %cmp19 = icmp sgt i32 %vecext18, 255 403 br i1 %cmp19, label %if.then, label %if.end 404 405if.then: 406 br label %return 407 408if.end: 409 %vecext20 = extractelement <4 x i32> %t, i32 0 410 %vecext21 = extractelement <4 x i32> %t, i32 1 411 %add = add nsw i32 %vecext20, %vecext21 412 %conv = sitofp i32 %add to float 413 br label %return 414 415return: 416 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %conv, %if.end ] 417 ret float %retval.0 418} 419 420define float @test_merge_anyof_v4si(<4 x i32> %t) { 421; CHECK-LABEL: @test_merge_anyof_v4si( 422; CHECK-NEXT: entry: 423; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> [[T:%.*]], i32 3 424; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[T]], i32 2 425; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[T]], i32 1 426; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[T]], i32 0 427; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T]] 428; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 1, i32 1, i32 1, i32 1> 429; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 430; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i4 [[TMP5]], 0 431; CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP3]], 255 432; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP11]] 433; CHECK-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP2]], 255 434; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP14]] 435; CHECK-NEXT: [[CMP17:%.*]] = icmp sgt i32 [[TMP1]], 255 436; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP17]] 437; CHECK-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP0]], 255 438; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP20]] 439; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] 440; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float 441; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[CONV]] 442; CHECK-NEXT: ret float [[RETVAL_0]] 443; 444entry: 445 %vecext = extractelement <4 x i32> %t, i32 0 446 %cmp = icmp slt i32 %vecext, 1 447 br i1 %cmp, label %if.then, label %lor.lhs.false 448 449lor.lhs.false: 450 %vecext1 = extractelement <4 x i32> %t, i32 1 451 %cmp2 = icmp slt i32 %vecext1, 1 452 br i1 %cmp2, label %if.then, label %lor.lhs.false3 453 454lor.lhs.false3: 455 %vecext4 = extractelement <4 x i32> %t, i32 2 456 %cmp5 = icmp slt i32 %vecext4, 1 457 br i1 %cmp5, label %if.then, label %lor.lhs.false6 458 459lor.lhs.false6: 460 %vecext7 = extractelement <4 x i32> %t, i32 3 461 %cmp8 = icmp slt i32 %vecext7, 1 462 br i1 %cmp8, label %if.then, label %lor.lhs.false9 463 464lor.lhs.false9: 465 %vecext10 = extractelement <4 x i32> %t, i32 0 466 %cmp11 = icmp sgt i32 %vecext10, 255 467 br i1 %cmp11, label %if.then, label %lor.lhs.false12 468 469lor.lhs.false12: 470 %vecext13 = extractelement <4 x i32> %t, i32 1 471 %cmp14 = icmp sgt i32 %vecext13, 255 472 br i1 %cmp14, label %if.then, label %lor.lhs.false15 473 474lor.lhs.false15: 475 %vecext16 = extractelement <4 x i32> %t, i32 2 476 %cmp17 = icmp sgt i32 %vecext16, 255 477 br i1 %cmp17, label %if.then, label %lor.lhs.false18 478 479lor.lhs.false18: 480 %vecext19 = extractelement <4 x i32> %t, i32 3 481 %cmp20 = icmp sgt i32 %vecext19, 255 482 br i1 %cmp20, label %if.then, label %if.end 483 484if.then: 485 br label %return 486 487if.end: 488 %vecext21 = extractelement <4 x i32> %t, i32 0 489 %vecext22 = extractelement <4 x i32> %t, i32 1 490 %add = add nsw i32 %vecext21, %vecext22 491 %conv = sitofp i32 %add to float 492 br label %return 493 494return: 495 %retval.0 = phi float [ 0.000000e+00, %if.then ], [ %conv, %if.end ] 496 ret float %retval.0 497} 498 499define i32 @test_separate_allof_v4si(<4 x i32> %t) { 500; CHECK-LABEL: @test_separate_allof_v4si( 501; CHECK-NEXT: entry: 502; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 503; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <4 x i32> [[T_FR]], zeroinitializer 504; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 505; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], 0 506; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]] 507; CHECK: if.end: 508; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 256, i32 256, i32 256, i32 256> 509; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 510; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], 0 511; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 512; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[T_FR]], [[SHIFT]] 513; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0 514; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], i32 0, i32 [[ADD]] 515; CHECK-NEXT: br label [[RETURN]] 516; CHECK: return: 517; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 518; CHECK-NEXT: ret i32 [[RETVAL_0]] 519; 520entry: 521 %vecext = extractelement <4 x i32> %t, i32 0 522 %cmp = icmp slt i32 %vecext, 1 523 br i1 %cmp, label %land.lhs.true, label %if.end 524 525land.lhs.true: 526 %vecext1 = extractelement <4 x i32> %t, i32 1 527 %cmp2 = icmp slt i32 %vecext1, 1 528 br i1 %cmp2, label %land.lhs.true3, label %if.end 529 530land.lhs.true3: 531 %vecext4 = extractelement <4 x i32> %t, i32 2 532 %cmp5 = icmp slt i32 %vecext4, 1 533 br i1 %cmp5, label %land.lhs.true6, label %if.end 534 535land.lhs.true6: 536 %vecext7 = extractelement <4 x i32> %t, i32 3 537 %cmp8 = icmp slt i32 %vecext7, 1 538 br i1 %cmp8, label %if.then, label %if.end 539 540if.then: 541 br label %return 542 543if.end: 544 %vecext9 = extractelement <4 x i32> %t, i32 0 545 %cmp10 = icmp sgt i32 %vecext9, 255 546 br i1 %cmp10, label %land.lhs.true11, label %if.end21 547 548land.lhs.true11: 549 %vecext12 = extractelement <4 x i32> %t, i32 1 550 %cmp13 = icmp sgt i32 %vecext12, 255 551 br i1 %cmp13, label %land.lhs.true14, label %if.end21 552 553land.lhs.true14: 554 %vecext15 = extractelement <4 x i32> %t, i32 2 555 %cmp16 = icmp sgt i32 %vecext15, 255 556 br i1 %cmp16, label %land.lhs.true17, label %if.end21 557 558land.lhs.true17: 559 %vecext18 = extractelement <4 x i32> %t, i32 3 560 %cmp19 = icmp sgt i32 %vecext18, 255 561 br i1 %cmp19, label %if.then20, label %if.end21 562 563if.then20: 564 br label %return 565 566if.end21: 567 %vecext22 = extractelement <4 x i32> %t, i32 0 568 %vecext23 = extractelement <4 x i32> %t, i32 1 569 %add = add nsw i32 %vecext22, %vecext23 570 br label %return 571 572return: 573 %retval.0 = phi i32 [ 0, %if.then ], [ 0, %if.then20 ], [ %add, %if.end21 ] 574 ret i32 %retval.0 575} 576 577define i32 @test_separate_anyof_v4si(<4 x i32> %t) { 578; CHECK-LABEL: @test_separate_anyof_v4si( 579; CHECK-NEXT: entry: 580; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] 581; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 1, i32 1, i32 1, i32 1> 582; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 583; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0 584; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[RETURN:%.*]] 585; CHECK: if.end: 586; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[T_FR]], <i32 255, i32 255, i32 255, i32 255> 587; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 588; CHECK-NEXT: [[DOTNOT7:%.*]] = icmp eq i4 [[TMP3]], 0 589; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 590; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T_FR]] 591; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0 592; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[DOTNOT7]], i32 [[ADD]], i32 0 593; CHECK-NEXT: br label [[RETURN]] 594; CHECK: return: 595; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ] 596; CHECK-NEXT: ret i32 [[RETVAL_0]] 597; 598entry: 599 %vecext = extractelement <4 x i32> %t, i32 0 600 %cmp = icmp slt i32 %vecext, 1 601 br i1 %cmp, label %if.then, label %lor.lhs.false 602 603lor.lhs.false: 604 %vecext1 = extractelement <4 x i32> %t, i32 1 605 %cmp2 = icmp slt i32 %vecext1, 1 606 br i1 %cmp2, label %if.then, label %lor.lhs.false3 607 608lor.lhs.false3: 609 %vecext4 = extractelement <4 x i32> %t, i32 2 610 %cmp5 = icmp slt i32 %vecext4, 1 611 br i1 %cmp5, label %if.then, label %lor.lhs.false6 612 613lor.lhs.false6: 614 %vecext7 = extractelement <4 x i32> %t, i32 3 615 %cmp8 = icmp slt i32 %vecext7, 1 616 br i1 %cmp8, label %if.then, label %if.end 617 618if.then: 619 br label %return 620 621if.end: 622 %vecext9 = extractelement <4 x i32> %t, i32 0 623 %cmp10 = icmp sgt i32 %vecext9, 255 624 br i1 %cmp10, label %if.then20, label %lor.lhs.false11 625 626lor.lhs.false11: 627 %vecext12 = extractelement <4 x i32> %t, i32 1 628 %cmp13 = icmp sgt i32 %vecext12, 255 629 br i1 %cmp13, label %if.then20, label %lor.lhs.false14 630 631lor.lhs.false14: 632 %vecext15 = extractelement <4 x i32> %t, i32 2 633 %cmp16 = icmp sgt i32 %vecext15, 255 634 br i1 %cmp16, label %if.then20, label %lor.lhs.false17 635 636lor.lhs.false17: 637 %vecext18 = extractelement <4 x i32> %t, i32 3 638 %cmp19 = icmp sgt i32 %vecext18, 255 639 br i1 %cmp19, label %if.then20, label %if.end21 640 641if.then20: 642 br label %return 643 644if.end21: 645 %vecext22 = extractelement <4 x i32> %t, i32 0 646 %vecext23 = extractelement <4 x i32> %t, i32 1 647 %add = add nsw i32 %vecext22, %vecext23 648 br label %return 649 650return: 651 %retval.0 = phi i32 [ 0, %if.then ], [ 0, %if.then20 ], [ %add, %if.end21 ] 652 ret i32 %retval.0 653} 654