1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s 3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 5target triple = "thumbv8.1m.main-arm-none-eabi" 6 7; This should, after inlining and simplification, be a single tail predicated 8; 16x vector loop handling llvm.sadd.sat. __SSAT is inlined and so is DCE'd. 9 10; Function Attrs: nounwind 11define dso_local void @arm_add_q7(i8* %pSrcA, i8* %pSrcB, i8* noalias %pDst, i32 %blockSize) #0 { 12; CHECK-LABEL: @arm_add_q7( 13; CHECK-NEXT: entry: 14; CHECK-NEXT: [[CMP_NOT3:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0 15; CHECK-NEXT: br i1 [[CMP_NOT3]], label [[WHILE_END:%.*]], label [[VECTOR_PH:%.*]] 16; CHECK: vector.ph: 17; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[BLOCKSIZE]], 15 18; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 19; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 20; CHECK: vector.body: 21; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 22; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PSRCA:%.*]], i32 [[INDEX]] 23; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, i8* [[PDST:%.*]], i32 [[INDEX]] 24; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, i8* [[PSRCB:%.*]], i32 [[INDEX]] 25; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = tail call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 [[INDEX]], i32 [[BLOCKSIZE]]) 26; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[NEXT_GEP]] to <16 x i8>* 27; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP0]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison) 28; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[NEXT_GEP15]] to <16 x i8>* 29; CHECK-NEXT: [[WIDE_MASKED_LOAD16:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP1]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison) 30; CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> [[WIDE_MASKED_LOAD]], <16 x i8> [[WIDE_MASKED_LOAD16]]) 31; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[NEXT_GEP14]] to <16 x i8>* 32; CHECK-NEXT: tail call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> [[TMP2]], <16 x i8>* [[TMP3]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]]) 33; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 16 34; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] 35; CHECK-NEXT: br i1 [[TMP4]], label [[WHILE_END]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 36; CHECK: while.end: 37; CHECK-NEXT: ret void 38; 39entry: 40 %pSrcA.addr = alloca i8*, align 4 41 %pSrcB.addr = alloca i8*, align 4 42 %pDst.addr = alloca i8*, align 4 43 %blockSize.addr = alloca i32, align 4 44 %blkCnt = alloca i32, align 4 45 store i8* %pSrcA, i8** %pSrcA.addr, align 4 46 store i8* %pSrcB, i8** %pSrcB.addr, align 4 47 store i8* %pDst, i8** %pDst.addr, align 4 48 store i32 %blockSize, i32* %blockSize.addr, align 4 49 %0 = bitcast i32* %blkCnt to i8* 50 call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) 51 %1 = load i32, i32* %blockSize.addr, align 4 52 store i32 %1, i32* %blkCnt, align 4 53 br label %while.cond 54 55while.cond: ; preds = %while.body, %entry 56 %2 = load i32, i32* %blkCnt, align 4 57 %cmp = icmp ugt i32 %2, 0 58 br i1 %cmp, label %while.body, label %while.end 59 60while.body: ; preds = %while.cond 61 %3 = load i8*, i8** %pSrcA.addr, align 4 62 %incdec.ptr = getelementptr inbounds i8, i8* %3, i32 1 63 store i8* %incdec.ptr, i8** %pSrcA.addr, align 4 64 %4 = load i8, i8* %3, align 1 65 %conv = sext i8 %4 to i16 66 %conv1 = sext i16 %conv to i32 67 %5 = load i8*, i8** %pSrcB.addr, align 4 68 %incdec.ptr2 = getelementptr inbounds i8, i8* %5, i32 1 69 store i8* %incdec.ptr2, i8** %pSrcB.addr, align 4 70 %6 = load i8, i8* %5, align 1 71 %conv3 = sext i8 %6 to i32 72 %add = add nsw i32 %conv1, %conv3 73 %call = call i32 @__SSAT(i32 %add, i32 8) 74 %conv4 = trunc i32 %call to i8 75 %7 = load i8*, i8** %pDst.addr, align 4 76 %incdec.ptr5 = getelementptr inbounds i8, i8* %7, i32 1 77 store i8* %incdec.ptr5, i8** %pDst.addr, align 4 78 store i8 %conv4, i8* %7, align 1 79 %8 = load i32, i32* %blkCnt, align 4 80 %dec = add i32 %8, -1 81 store i32 %dec, i32* %blkCnt, align 4 82 br label %while.cond 83 84while.end: ; preds = %while.cond 85 %9 = bitcast i32* %blkCnt to i8* 86 call void @llvm.lifetime.end.p0i8(i64 4, i8* %9) 87 ret void 88} 89 90define internal i32 @__SSAT(i32 %val, i32 %sat) #1 { 91entry: 92 %retval = alloca i32, align 4 93 %val.addr = alloca i32, align 4 94 %sat.addr = alloca i32, align 4 95 %max = alloca i32, align 4 96 %min = alloca i32, align 4 97 %cleanup.dest.slot = alloca i32, align 4 98 store i32 %val, i32* %val.addr, align 4 99 store i32 %sat, i32* %sat.addr, align 4 100 %0 = load i32, i32* %sat.addr, align 4 101 %cmp = icmp uge i32 %0, 1 102 br i1 %cmp, label %land.lhs.true, label %if.end10 103 104land.lhs.true: ; preds = %entry 105 %1 = load i32, i32* %sat.addr, align 4 106 %cmp1 = icmp ule i32 %1, 32 107 br i1 %cmp1, label %if.then, label %if.end10 108 109if.then: ; preds = %land.lhs.true 110 %2 = bitcast i32* %max to i8* 111 call void @llvm.lifetime.start.p0i8(i64 4, i8* %2) 112 %3 = load i32, i32* %sat.addr, align 4 113 %sub = sub i32 %3, 1 114 %shl = shl i32 1, %sub 115 %sub2 = sub i32 %shl, 1 116 store i32 %sub2, i32* %max, align 4 117 %4 = bitcast i32* %min to i8* 118 call void @llvm.lifetime.start.p0i8(i64 4, i8* %4) 119 %5 = load i32, i32* %max, align 4 120 %sub3 = sub nsw i32 -1, %5 121 store i32 %sub3, i32* %min, align 4 122 %6 = load i32, i32* %val.addr, align 4 123 %7 = load i32, i32* %max, align 4 124 %cmp4 = icmp sgt i32 %6, %7 125 br i1 %cmp4, label %if.then5, label %if.else 126 127if.then5: ; preds = %if.then 128 %8 = load i32, i32* %max, align 4 129 store i32 %8, i32* %retval, align 4 130 store i32 1, i32* %cleanup.dest.slot, align 4 131 br label %cleanup 132 133if.else: ; preds = %if.then 134 %9 = load i32, i32* %val.addr, align 4 135 %10 = load i32, i32* %min, align 4 136 %cmp6 = icmp slt i32 %9, %10 137 br i1 %cmp6, label %if.then7, label %if.end 138 139if.then7: ; preds = %if.else 140 %11 = load i32, i32* %min, align 4 141 store i32 %11, i32* %retval, align 4 142 store i32 1, i32* %cleanup.dest.slot, align 4 143 br label %cleanup 144 145if.end: ; preds = %if.else 146 br label %if.end8 147 148if.end8: ; preds = %if.end 149 store i32 0, i32* %cleanup.dest.slot, align 4 150 br label %cleanup 151 152cleanup: ; preds = %if.end8, %if.then7, %if.then5 153 %12 = bitcast i32* %min to i8* 154 call void @llvm.lifetime.end.p0i8(i64 4, i8* %12) 155 %13 = bitcast i32* %max to i8* 156 call void @llvm.lifetime.end.p0i8(i64 4, i8* %13) 157 %cleanup.dest = load i32, i32* %cleanup.dest.slot, align 4 158 switch i32 %cleanup.dest, label %unreachable [ 159 i32 0, label %cleanup.cont 160 i32 1, label %return 161 ] 162 163cleanup.cont: ; preds = %cleanup 164 br label %if.end10 165 166if.end10: ; preds = %cleanup.cont, %land.lhs.true, %entry 167 %14 = load i32, i32* %val.addr, align 4 168 store i32 %14, i32* %retval, align 4 169 br label %return 170 171return: ; preds = %if.end10, %cleanup 172 %15 = load i32, i32* %retval, align 4 173 ret i32 %15 174 175unreachable: ; preds = %cleanup 176 unreachable 177} 178 179declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) 180declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) 181 182attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" } 183attributes #1 = { alwaysinline nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" } 184