1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -loop-versioning -S < %s | FileCheck %s -check-prefix=LV
3
4target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
5
6; For this loop:
7;   unsigned index = 0;
8;   for (int i = 0; i < n; i++) {
9;    A[2 * index] = A[2 * index] + B[i];
10;    index++;
11;   }
12;
13; SCEV is unable to prove that A[2 * i] does not overflow.
14;
15; Analyzing the IR does not help us because the GEPs are not
16; affine AddRecExprs. However, we can turn them into AddRecExprs
17; using SCEV Predicates.
18;
19; Once we have an affine expression we need to add an additional NUSW
20; to check that the pointers don't wrap since the GEPs are not
21; inbound.
22
23; The expression for %mul_ext as analyzed by SCEV is
24;    (zext i32 {0,+,2}<%for.body> to i64)
25; We have added the nusw flag to turn this expression into the SCEV expression:
26;    i64 {0,+,2}<%for.body>
27
28define void @f1(i16* noalias %a,
29; LV-LABEL: @f1(
30; LV-NEXT:  for.body.lver.check:
31; LV-NEXT:    [[A5:%.*]] = bitcast i16* [[A:%.*]] to i8*
32; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N:%.*]], -1
33; LV-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
34; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
35; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
36; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
37; LV-NEXT:    [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
38; LV-NEXT:    [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
39; LV-NEXT:    [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], 0
40; LV-NEXT:    [[TMP5:%.*]] = icmp ult i32 [[TMP2]], 0
41; LV-NEXT:    [[TMP6:%.*]] = select i1 false, i1 [[TMP4]], i1 [[TMP5]]
42; LV-NEXT:    [[TMP7:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
43; LV-NEXT:    [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
44; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
45; LV-NEXT:    [[TMP10:%.*]] = or i1 false, [[TMP9]]
46; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
47; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
48; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
49; LV-NEXT:    [[TMP11:%.*]] = sub i64 0, [[MUL_RESULT3]]
50; LV-NEXT:    [[TMP12:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]
51; LV-NEXT:    [[TMP13:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP11]]
52; LV-NEXT:    [[TMP14:%.*]] = icmp ugt i8* [[TMP13]], [[A5]]
53; LV-NEXT:    [[TMP15:%.*]] = icmp ult i8* [[TMP12]], [[A5]]
54; LV-NEXT:    [[TMP16:%.*]] = select i1 false, i1 [[TMP14]], i1 [[TMP15]]
55; LV-NEXT:    [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW4]]
56; LV-NEXT:    [[TMP18:%.*]] = or i1 [[TMP10]], [[TMP17]]
57; LV-NEXT:    br i1 [[TMP18]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
58; LV:       for.body.ph.lver.orig:
59; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
60; LV:       for.body.lver.orig:
61; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
62; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC1_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
63; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
64; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = zext i32 [[MUL_LVER_ORIG]] to i64
65; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
66; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
67; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
68; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
69; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
70; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
71; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
72; LV-NEXT:    [[INC1_LVER_ORIG]] = add i32 [[IND1_LVER_ORIG]], 1
73; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
74; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
75; LV:       for.body.ph:
76; LV-NEXT:    br label [[FOR_BODY:%.*]]
77; LV:       for.body:
78; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
79; LV-NEXT:    [[IND1:%.*]] = phi i32 [ 0, [[FOR_BODY_PH]] ], [ [[INC1:%.*]], [[FOR_BODY]] ]
80; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
81; LV-NEXT:    [[MUL_EXT:%.*]] = zext i32 [[MUL]] to i64
82; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
83; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
84; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
85; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
86; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
87; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
88; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
89; LV-NEXT:    [[INC1]] = add i32 [[IND1]], 1
90; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
91; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
92; LV:       for.end.loopexit:
93; LV-NEXT:    br label [[FOR_END:%.*]]
94; LV:       for.end.loopexit6:
95; LV-NEXT:    br label [[FOR_END]]
96; LV:       for.end:
97; LV-NEXT:    ret void
98;
99  i16* noalias %b, i64 %N) {
100entry:
101  br label %for.body
102
103for.body:                                         ; preds = %for.body, %entry
104  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
105  %ind1 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
106
107  %mul = mul i32 %ind1, 2
108  %mul_ext = zext i32 %mul to i64
109
110  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
111  %loadA = load i16, i16* %arrayidxA, align 2
112
113  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
114  %loadB = load i16, i16* %arrayidxB, align 2
115
116  %add = mul i16 %loadA, %loadB
117
118  store i16 %add, i16* %arrayidxA, align 2
119
120  %inc = add nuw nsw i64 %ind, 1
121  %inc1 = add i32 %ind1, 1
122
123  %exitcond = icmp eq i64 %inc, %N
124  br i1 %exitcond, label %for.end, label %for.body
125
126for.end:                                          ; preds = %for.body
127  ret void
128}
129
130; For this loop:
131;   unsigned index = n;
132;   for (int i = 0; i < n; i++) {
133;    A[2 * index] = A[2 * index] + B[i];
134;    index--;
135;   }
136;
137; the SCEV expression for 2 * index is not an AddRecExpr
138; (and implictly not affine). However, we are able to make assumptions
139; that will turn the expression into an affine one and continue the
140; analysis.
141;
142; Once we have an affine expression we need to add an additional NUSW
143; to check that the pointers don't wrap since the GEPs are not
144; inbounds.
145;
146; This loop has a negative stride for A, and the nusw flag is required in
147; order to properly extend the increment from i32 -4 to i64 -4.
148
149; The expression for %mul_ext as analyzed by SCEV is
150;     (zext i32 {(2 * (trunc i64 %N to i32)),+,-2}<%for.body> to i64)
151; We have added the nusw flag to turn this expression into the following SCEV:
152;     i64 {zext i32 (2 * (trunc i64 %N to i32)) to i64,+,-2}<%for.body>
153
154define void @f2(i16* noalias %a,
155; LV-LABEL: @f2(
156; LV-NEXT:  for.body.lver.check:
157; LV-NEXT:    [[TRUNCN:%.*]] = trunc i64 [[N:%.*]] to i32
158; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
159; LV-NEXT:    [[TMP1:%.*]] = shl i32 [[TRUNCN]], 1
160; LV-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
161; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP2]])
162; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
163; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
164; LV-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[MUL_RESULT]]
165; LV-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
166; LV-NEXT:    [[TMP5:%.*]] = icmp ugt i32 [[TMP4]], [[TMP1]]
167; LV-NEXT:    [[TMP6:%.*]] = icmp ult i32 [[TMP3]], [[TMP1]]
168; LV-NEXT:    [[TMP7:%.*]] = select i1 true, i1 [[TMP5]], i1 [[TMP6]]
169; LV-NEXT:    [[TMP8:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
170; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
171; LV-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW]]
172; LV-NEXT:    [[TMP11:%.*]] = or i1 false, [[TMP10]]
173; LV-NEXT:    [[TMP12:%.*]] = trunc i64 [[N]] to i31
174; LV-NEXT:    [[TMP13:%.*]] = zext i31 [[TMP12]] to i64
175; LV-NEXT:    [[TMP14:%.*]] = shl nuw nsw i64 [[TMP13]], 1
176; LV-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[A:%.*]], i64 [[TMP14]]
177; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
178; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
179; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
180; LV-NEXT:    [[SCEVGEP5:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
181; LV-NEXT:    [[TMP15:%.*]] = sub i64 0, [[MUL_RESULT3]]
182; LV-NEXT:    [[TMP16:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[MUL_RESULT3]]
183; LV-NEXT:    [[TMP17:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[TMP15]]
184; LV-NEXT:    [[TMP18:%.*]] = icmp ugt i8* [[TMP17]], [[SCEVGEP5]]
185; LV-NEXT:    [[TMP19:%.*]] = icmp ult i8* [[TMP16]], [[SCEVGEP5]]
186; LV-NEXT:    [[TMP20:%.*]] = select i1 true, i1 [[TMP18]], i1 [[TMP19]]
187; LV-NEXT:    [[TMP21:%.*]] = or i1 [[TMP20]], [[MUL_OVERFLOW4]]
188; LV-NEXT:    [[TMP22:%.*]] = or i1 [[TMP11]], [[TMP21]]
189; LV-NEXT:    br i1 [[TMP22]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
190; LV:       for.body.ph.lver.orig:
191; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
192; LV:       for.body.lver.orig:
193; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
194; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH_LVER_ORIG]] ], [ [[DEC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
195; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
196; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = zext i32 [[MUL_LVER_ORIG]] to i64
197; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
198; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
199; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
200; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
201; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
202; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
203; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
204; LV-NEXT:    [[DEC_LVER_ORIG]] = sub i32 [[IND1_LVER_ORIG]], 1
205; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
206; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
207; LV:       for.body.ph:
208; LV-NEXT:    br label [[FOR_BODY:%.*]]
209; LV:       for.body:
210; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
211; LV-NEXT:    [[IND1:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH]] ], [ [[DEC:%.*]], [[FOR_BODY]] ]
212; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
213; LV-NEXT:    [[MUL_EXT:%.*]] = zext i32 [[MUL]] to i64
214; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
215; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
216; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
217; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
218; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
219; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
220; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
221; LV-NEXT:    [[DEC]] = sub i32 [[IND1]], 1
222; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
223; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
224; LV:       for.end.loopexit:
225; LV-NEXT:    br label [[FOR_END:%.*]]
226; LV:       for.end.loopexit6:
227; LV-NEXT:    br label [[FOR_END]]
228; LV:       for.end:
229; LV-NEXT:    ret void
230;
231  i16* noalias %b, i64 %N) {
232entry:
233  %TruncN = trunc i64 %N to i32
234  br label %for.body
235
236for.body:                                         ; preds = %for.body, %entry
237  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
238  %ind1 = phi i32 [ %TruncN, %entry ], [ %dec, %for.body ]
239
240  %mul = mul i32 %ind1, 2
241  %mul_ext = zext i32 %mul to i64
242
243  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
244  %loadA = load i16, i16* %arrayidxA, align 2
245
246  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
247  %loadB = load i16, i16* %arrayidxB, align 2
248
249  %add = mul i16 %loadA, %loadB
250
251  store i16 %add, i16* %arrayidxA, align 2
252
253  %inc = add nuw nsw i64 %ind, 1
254  %dec = sub i32 %ind1, 1
255
256  %exitcond = icmp eq i64 %inc, %N
257  br i1 %exitcond, label %for.end, label %for.body
258
259for.end:                                          ; preds = %for.body
260  ret void
261}
262
263; We replicate the tests above, but this time sign extend 2 * index instead
264; of zero extending it.
265
266; The expression for %mul_ext as analyzed by SCEV is
267;     i64 (sext i32 {0,+,2}<%for.body> to i64)
268; We have added the nssw flag to turn this expression into the following SCEV:
269;     i64 {0,+,2}<%for.body>
270
271define void @f3(i16* noalias %a,
272; LV-LABEL: @f3(
273; LV-NEXT:  for.body.lver.check:
274; LV-NEXT:    [[A5:%.*]] = bitcast i16* [[A:%.*]] to i8*
275; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N:%.*]], -1
276; LV-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
277; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
278; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
279; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
280; LV-NEXT:    [[TMP2:%.*]] = add i32 0, [[MUL_RESULT]]
281; LV-NEXT:    [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
282; LV-NEXT:    [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], 0
283; LV-NEXT:    [[TMP5:%.*]] = icmp slt i32 [[TMP2]], 0
284; LV-NEXT:    [[TMP6:%.*]] = select i1 false, i1 [[TMP4]], i1 [[TMP5]]
285; LV-NEXT:    [[TMP7:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
286; LV-NEXT:    [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
287; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
288; LV-NEXT:    [[TMP10:%.*]] = or i1 false, [[TMP9]]
289; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
290; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
291; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
292; LV-NEXT:    [[TMP11:%.*]] = sub i64 0, [[MUL_RESULT3]]
293; LV-NEXT:    [[TMP12:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]
294; LV-NEXT:    [[TMP13:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP11]]
295; LV-NEXT:    [[TMP14:%.*]] = icmp ugt i8* [[TMP13]], [[A5]]
296; LV-NEXT:    [[TMP15:%.*]] = icmp ult i8* [[TMP12]], [[A5]]
297; LV-NEXT:    [[TMP16:%.*]] = select i1 false, i1 [[TMP14]], i1 [[TMP15]]
298; LV-NEXT:    [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW4]]
299; LV-NEXT:    [[TMP18:%.*]] = or i1 [[TMP10]], [[TMP17]]
300; LV-NEXT:    br i1 [[TMP18]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
301; LV:       for.body.ph.lver.orig:
302; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
303; LV:       for.body.lver.orig:
304; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
305; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC1_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
306; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
307; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = sext i32 [[MUL_LVER_ORIG]] to i64
308; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
309; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
310; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
311; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
312; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
313; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
314; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
315; LV-NEXT:    [[INC1_LVER_ORIG]] = add i32 [[IND1_LVER_ORIG]], 1
316; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
317; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
318; LV:       for.body.ph:
319; LV-NEXT:    br label [[FOR_BODY:%.*]]
320; LV:       for.body:
321; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
322; LV-NEXT:    [[IND1:%.*]] = phi i32 [ 0, [[FOR_BODY_PH]] ], [ [[INC1:%.*]], [[FOR_BODY]] ]
323; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
324; LV-NEXT:    [[MUL_EXT:%.*]] = sext i32 [[MUL]] to i64
325; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
326; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
327; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
328; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
329; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
330; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
331; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
332; LV-NEXT:    [[INC1]] = add i32 [[IND1]], 1
333; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
334; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
335; LV:       for.end.loopexit:
336; LV-NEXT:    br label [[FOR_END:%.*]]
337; LV:       for.end.loopexit6:
338; LV-NEXT:    br label [[FOR_END]]
339; LV:       for.end:
340; LV-NEXT:    ret void
341;
342  i16* noalias %b, i64 %N) {
343entry:
344  br label %for.body
345
346for.body:                                         ; preds = %for.body, %entry
347  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
348  %ind1 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
349
350  %mul = mul i32 %ind1, 2
351  %mul_ext = sext i32 %mul to i64
352
353  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
354  %loadA = load i16, i16* %arrayidxA, align 2
355
356  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
357  %loadB = load i16, i16* %arrayidxB, align 2
358
359  %add = mul i16 %loadA, %loadB
360
361  store i16 %add, i16* %arrayidxA, align 2
362
363  %inc = add nuw nsw i64 %ind, 1
364  %inc1 = add i32 %ind1, 1
365
366  %exitcond = icmp eq i64 %inc, %N
367  br i1 %exitcond, label %for.end, label %for.body
368
369for.end:                                          ; preds = %for.body
370  ret void
371}
372
373define void @f4(i16* noalias %a,
374; LV-LABEL: @f4(
375; LV-NEXT:  for.body.lver.check:
376; LV-NEXT:    [[TRUNCN:%.*]] = trunc i64 [[N:%.*]] to i32
377; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
378; LV-NEXT:    [[TMP1:%.*]] = shl i32 [[TRUNCN]], 1
379; LV-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
380; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP2]])
381; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
382; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
383; LV-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[MUL_RESULT]]
384; LV-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
385; LV-NEXT:    [[TMP5:%.*]] = icmp sgt i32 [[TMP4]], [[TMP1]]
386; LV-NEXT:    [[TMP6:%.*]] = icmp slt i32 [[TMP3]], [[TMP1]]
387; LV-NEXT:    [[TMP7:%.*]] = select i1 true, i1 [[TMP5]], i1 [[TMP6]]
388; LV-NEXT:    [[TMP8:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
389; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
390; LV-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW]]
391; LV-NEXT:    [[TMP11:%.*]] = or i1 false, [[TMP10]]
392; LV-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP1]] to i64
393; LV-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[A:%.*]], i64 [[TMP12]]
394; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
395; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
396; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
397; LV-NEXT:    [[SCEVGEP5:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
398; LV-NEXT:    [[TMP13:%.*]] = sub i64 0, [[MUL_RESULT3]]
399; LV-NEXT:    [[TMP14:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[MUL_RESULT3]]
400; LV-NEXT:    [[TMP15:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[TMP13]]
401; LV-NEXT:    [[TMP16:%.*]] = icmp ugt i8* [[TMP15]], [[SCEVGEP5]]
402; LV-NEXT:    [[TMP17:%.*]] = icmp ult i8* [[TMP14]], [[SCEVGEP5]]
403; LV-NEXT:    [[TMP18:%.*]] = select i1 true, i1 [[TMP16]], i1 [[TMP17]]
404; LV-NEXT:    [[TMP19:%.*]] = or i1 [[TMP18]], [[MUL_OVERFLOW4]]
405; LV-NEXT:    [[TMP20:%.*]] = or i1 [[TMP11]], [[TMP19]]
406; LV-NEXT:    br i1 [[TMP20]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
407; LV:       for.body.ph.lver.orig:
408; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
409; LV:       for.body.lver.orig:
410; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
411; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH_LVER_ORIG]] ], [ [[DEC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
412; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
413; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = sext i32 [[MUL_LVER_ORIG]] to i64
414; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
415; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
416; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
417; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
418; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
419; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
420; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
421; LV-NEXT:    [[DEC_LVER_ORIG]] = sub i32 [[IND1_LVER_ORIG]], 1
422; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
423; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
424; LV:       for.body.ph:
425; LV-NEXT:    br label [[FOR_BODY:%.*]]
426; LV:       for.body:
427; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
428; LV-NEXT:    [[IND1:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH]] ], [ [[DEC:%.*]], [[FOR_BODY]] ]
429; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
430; LV-NEXT:    [[MUL_EXT:%.*]] = sext i32 [[MUL]] to i64
431; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
432; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
433; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
434; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
435; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
436; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
437; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
438; LV-NEXT:    [[DEC]] = sub i32 [[IND1]], 1
439; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
440; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
441; LV:       for.end.loopexit:
442; LV-NEXT:    br label [[FOR_END:%.*]]
443; LV:       for.end.loopexit6:
444; LV-NEXT:    br label [[FOR_END]]
445; LV:       for.end:
446; LV-NEXT:    ret void
447;
448  i16* noalias %b, i64 %N) {
449entry:
450  %TruncN = trunc i64 %N to i32
451  br label %for.body
452
453for.body:                                         ; preds = %for.body, %entry
454  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
455  %ind1 = phi i32 [ %TruncN, %entry ], [ %dec, %for.body ]
456
457  %mul = mul i32 %ind1, 2
458  %mul_ext = sext i32 %mul to i64
459
460  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
461  %loadA = load i16, i16* %arrayidxA, align 2
462
463  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
464  %loadB = load i16, i16* %arrayidxB, align 2
465
466  %add = mul i16 %loadA, %loadB
467
468  store i16 %add, i16* %arrayidxA, align 2
469
470  %inc = add nuw nsw i64 %ind, 1
471  %dec = sub i32 %ind1, 1
472
473  %exitcond = icmp eq i64 %inc, %N
474  br i1 %exitcond, label %for.end, label %for.body
475
476for.end:                                          ; preds = %for.body
477  ret void
478}
479
480; The following function is similar to the one above, but has the GEP
481; to pointer %A inbounds. The index %mul doesn't have the nsw flag.
482; This means that the SCEV expression for %mul can wrap and we need
483; a SCEV predicate to continue analysis.
484;
485; We can still analyze this by adding the required no wrap SCEV predicates.
486
487define void @f5(i16* noalias %a,
488; LV-LABEL: @f5(
489; LV-NEXT:  for.body.lver.check:
490; LV-NEXT:    [[TRUNCN:%.*]] = trunc i64 [[N:%.*]] to i32
491; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
492; LV-NEXT:    [[TMP1:%.*]] = shl i32 [[TRUNCN]], 1
493; LV-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
494; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP2]])
495; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
496; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
497; LV-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[MUL_RESULT]]
498; LV-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
499; LV-NEXT:    [[TMP5:%.*]] = icmp sgt i32 [[TMP4]], [[TMP1]]
500; LV-NEXT:    [[TMP6:%.*]] = icmp slt i32 [[TMP3]], [[TMP1]]
501; LV-NEXT:    [[TMP7:%.*]] = select i1 true, i1 [[TMP5]], i1 [[TMP6]]
502; LV-NEXT:    [[TMP8:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
503; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
504; LV-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW]]
505; LV-NEXT:    [[TMP11:%.*]] = or i1 false, [[TMP10]]
506; LV-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP1]] to i64
507; LV-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[A:%.*]], i64 [[TMP12]]
508; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
509; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
510; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
511; LV-NEXT:    [[SCEVGEP5:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
512; LV-NEXT:    [[TMP13:%.*]] = sub i64 0, [[MUL_RESULT3]]
513; LV-NEXT:    [[TMP14:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[MUL_RESULT3]]
514; LV-NEXT:    [[TMP15:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[TMP13]]
515; LV-NEXT:    [[TMP16:%.*]] = icmp ugt i8* [[TMP15]], [[SCEVGEP5]]
516; LV-NEXT:    [[TMP17:%.*]] = icmp ult i8* [[TMP14]], [[SCEVGEP5]]
517; LV-NEXT:    [[TMP18:%.*]] = select i1 true, i1 [[TMP16]], i1 [[TMP17]]
518; LV-NEXT:    [[TMP19:%.*]] = or i1 [[TMP18]], [[MUL_OVERFLOW4]]
519; LV-NEXT:    [[TMP20:%.*]] = or i1 [[TMP11]], [[TMP19]]
520; LV-NEXT:    br i1 [[TMP20]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
521; LV:       for.body.ph.lver.orig:
522; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
523; LV:       for.body.lver.orig:
524; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
525; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH_LVER_ORIG]] ], [ [[DEC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
526; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
527; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr inbounds i16, i16* [[A]], i32 [[MUL_LVER_ORIG]]
528; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
529; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr inbounds i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
530; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
531; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
532; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
533; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
534; LV-NEXT:    [[DEC_LVER_ORIG]] = sub i32 [[IND1_LVER_ORIG]], 1
535; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
536; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
537; LV:       for.body.ph:
538; LV-NEXT:    br label [[FOR_BODY:%.*]]
539; LV:       for.body:
540; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
541; LV-NEXT:    [[IND1:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH]] ], [ [[DEC:%.*]], [[FOR_BODY]] ]
542; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
543; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr inbounds i16, i16* [[A]], i32 [[MUL]]
544; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
545; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr inbounds i16, i16* [[B]], i64 [[IND]]
546; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
547; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
548; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
549; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
550; LV-NEXT:    [[DEC]] = sub i32 [[IND1]], 1
551; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
552; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
553; LV:       for.end.loopexit:
554; LV-NEXT:    br label [[FOR_END:%.*]]
555; LV:       for.end.loopexit6:
556; LV-NEXT:    br label [[FOR_END]]
557; LV:       for.end:
558; LV-NEXT:    ret void
559;
560  i16* noalias %b, i64 %N) {
561entry:
562  %TruncN = trunc i64 %N to i32
563  br label %for.body
564
565for.body:                                         ; preds = %for.body, %entry
566  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
567  %ind1 = phi i32 [ %TruncN, %entry ], [ %dec, %for.body ]
568
569  %mul = mul i32 %ind1, 2
570
571  %arrayidxA = getelementptr inbounds i16, i16* %a, i32 %mul
572  %loadA = load i16, i16* %arrayidxA, align 2
573
574  %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %ind
575  %loadB = load i16, i16* %arrayidxB, align 2
576
577  %add = mul i16 %loadA, %loadB
578
579  store i16 %add, i16* %arrayidxA, align 2
580
581  %inc = add nuw nsw i64 %ind, 1
582  %dec = sub i32 %ind1, 1
583
584  %exitcond = icmp eq i64 %inc, %N
585  br i1 %exitcond, label %for.end, label %for.body
586
587for.end:                                          ; preds = %for.body
588  ret void
589}
590