1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -loop-versioning -S < %s | FileCheck %s -check-prefix=LV
3
4target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
5
6; For this loop:
7;   unsigned index = 0;
8;   for (int i = 0; i < n; i++) {
9;    A[2 * index] = A[2 * index] + B[i];
10;    index++;
11;   }
12;
13; SCEV is unable to prove that A[2 * i] does not overflow.
14;
15; Analyzing the IR does not help us because the GEPs are not
16; affine AddRecExprs. However, we can turn them into AddRecExprs
17; using SCEV Predicates.
18;
19; Once we have an affine expression we need to add an additional NUSW
20; to check that the pointers don't wrap since the GEPs are not
21; inbound.
22
23; The expression for %mul_ext as analyzed by SCEV is
24;    (zext i32 {0,+,2}<%for.body> to i64)
25; We have added the nusw flag to turn this expression into the SCEV expression:
26;    i64 {0,+,2}<%for.body>
27
28define void @f1(i16* noalias %a,
29; LV-LABEL: @f1(
30; LV-NEXT:  for.body.lver.check:
31; LV-NEXT:    [[A5:%.*]] = bitcast i16* [[A:%.*]] to i8*
32; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N:%.*]], -1
33; LV-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
34; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
35; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
36; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
37; LV-NEXT:    [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]
38; LV-NEXT:    [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 0
39; LV-NEXT:    [[TMP4:%.*]] = icmp ult i32 [[MUL_RESULT]], 0
40; LV-NEXT:    [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
41; LV-NEXT:    [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]
42; LV-NEXT:    [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]
43; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
44; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
45; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
46; LV-NEXT:    [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT3]]
47; LV-NEXT:    [[TMP9:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]
48; LV-NEXT:    [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP8]]
49; LV-NEXT:    [[TMP11:%.*]] = icmp ugt i8* [[TMP10]], [[A5]]
50; LV-NEXT:    [[TMP12:%.*]] = icmp ult i8* [[TMP9]], [[A5]]
51; LV-NEXT:    [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]
52; LV-NEXT:    [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]
53; LV-NEXT:    br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
54; LV:       for.body.ph.lver.orig:
55; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
56; LV:       for.body.lver.orig:
57; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
58; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC1_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
59; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
60; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = zext i32 [[MUL_LVER_ORIG]] to i64
61; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
62; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
63; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
64; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
65; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
66; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
67; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
68; LV-NEXT:    [[INC1_LVER_ORIG]] = add i32 [[IND1_LVER_ORIG]], 1
69; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
70; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
71; LV:       for.body.ph:
72; LV-NEXT:    br label [[FOR_BODY:%.*]]
73; LV:       for.body:
74; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
75; LV-NEXT:    [[IND1:%.*]] = phi i32 [ 0, [[FOR_BODY_PH]] ], [ [[INC1:%.*]], [[FOR_BODY]] ]
76; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
77; LV-NEXT:    [[MUL_EXT:%.*]] = zext i32 [[MUL]] to i64
78; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
79; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
80; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
81; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
82; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
83; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
84; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
85; LV-NEXT:    [[INC1]] = add i32 [[IND1]], 1
86; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
87; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
88; LV:       for.end.loopexit:
89; LV-NEXT:    br label [[FOR_END:%.*]]
90; LV:       for.end.loopexit6:
91; LV-NEXT:    br label [[FOR_END]]
92; LV:       for.end:
93; LV-NEXT:    ret void
94;
95  i16* noalias %b, i64 %N) {
96entry:
97  br label %for.body
98
99for.body:                                         ; preds = %for.body, %entry
100  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
101  %ind1 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
102
103  %mul = mul i32 %ind1, 2
104  %mul_ext = zext i32 %mul to i64
105
106  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
107  %loadA = load i16, i16* %arrayidxA, align 2
108
109  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
110  %loadB = load i16, i16* %arrayidxB, align 2
111
112  %add = mul i16 %loadA, %loadB
113
114  store i16 %add, i16* %arrayidxA, align 2
115
116  %inc = add nuw nsw i64 %ind, 1
117  %inc1 = add i32 %ind1, 1
118
119  %exitcond = icmp eq i64 %inc, %N
120  br i1 %exitcond, label %for.end, label %for.body
121
122for.end:                                          ; preds = %for.body
123  ret void
124}
125
126; For this loop:
127;   unsigned index = n;
128;   for (int i = 0; i < n; i++) {
129;    A[2 * index] = A[2 * index] + B[i];
130;    index--;
131;   }
132;
133; the SCEV expression for 2 * index is not an AddRecExpr
134; (and implictly not affine). However, we are able to make assumptions
135; that will turn the expression into an affine one and continue the
136; analysis.
137;
138; Once we have an affine expression we need to add an additional NUSW
139; to check that the pointers don't wrap since the GEPs are not
140; inbounds.
141;
142; This loop has a negative stride for A, and the nusw flag is required in
143; order to properly extend the increment from i32 -4 to i64 -4.
144
145; The expression for %mul_ext as analyzed by SCEV is
146;     (zext i32 {(2 * (trunc i64 %N to i32)),+,-2}<%for.body> to i64)
147; We have added the nusw flag to turn this expression into the following SCEV:
148;     i64 {zext i32 (2 * (trunc i64 %N to i32)) to i64,+,-2}<%for.body>
149
150define void @f2(i16* noalias %a,
151; LV-LABEL: @f2(
152; LV-NEXT:  for.body.lver.check:
153; LV-NEXT:    [[TRUNCN:%.*]] = trunc i64 [[N:%.*]] to i32
154; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
155; LV-NEXT:    [[TMP1:%.*]] = shl i32 [[TRUNCN]], 1
156; LV-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
157; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP2]])
158; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
159; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
160; LV-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[MUL_RESULT]]
161; LV-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
162; LV-NEXT:    [[TMP5:%.*]] = icmp ugt i32 [[TMP4]], [[TMP1]]
163; LV-NEXT:    [[TMP6:%.*]] = icmp ult i32 [[TMP3]], [[TMP1]]
164; LV-NEXT:    [[TMP7:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
165; LV-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]]
166; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
167; LV-NEXT:    [[TMP10:%.*]] = trunc i64 [[N]] to i31
168; LV-NEXT:    [[TMP11:%.*]] = zext i31 [[TMP10]] to i64
169; LV-NEXT:    [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 1
170; LV-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[A:%.*]], i64 [[TMP12]]
171; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
172; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
173; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
174; LV-NEXT:    [[SCEVGEP5:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
175; LV-NEXT:    [[TMP13:%.*]] = sub i64 0, [[MUL_RESULT3]]
176; LV-NEXT:    [[TMP14:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[MUL_RESULT3]]
177; LV-NEXT:    [[TMP15:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[TMP13]]
178; LV-NEXT:    [[TMP16:%.*]] = icmp ugt i8* [[TMP15]], [[SCEVGEP5]]
179; LV-NEXT:    [[TMP17:%.*]] = icmp ult i8* [[TMP14]], [[SCEVGEP5]]
180; LV-NEXT:    [[TMP18:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW4]]
181; LV-NEXT:    [[TMP19:%.*]] = or i1 [[TMP9]], [[TMP18]]
182; LV-NEXT:    br i1 [[TMP19]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
183; LV:       for.body.ph.lver.orig:
184; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
185; LV:       for.body.lver.orig:
186; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
187; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH_LVER_ORIG]] ], [ [[DEC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
188; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
189; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = zext i32 [[MUL_LVER_ORIG]] to i64
190; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
191; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
192; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
193; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
194; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
195; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
196; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
197; LV-NEXT:    [[DEC_LVER_ORIG]] = sub i32 [[IND1_LVER_ORIG]], 1
198; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
199; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
200; LV:       for.body.ph:
201; LV-NEXT:    br label [[FOR_BODY:%.*]]
202; LV:       for.body:
203; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
204; LV-NEXT:    [[IND1:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH]] ], [ [[DEC:%.*]], [[FOR_BODY]] ]
205; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
206; LV-NEXT:    [[MUL_EXT:%.*]] = zext i32 [[MUL]] to i64
207; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
208; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
209; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
210; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
211; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
212; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
213; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
214; LV-NEXT:    [[DEC]] = sub i32 [[IND1]], 1
215; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
216; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
217; LV:       for.end.loopexit:
218; LV-NEXT:    br label [[FOR_END:%.*]]
219; LV:       for.end.loopexit6:
220; LV-NEXT:    br label [[FOR_END]]
221; LV:       for.end:
222; LV-NEXT:    ret void
223;
224  i16* noalias %b, i64 %N) {
225entry:
226  %TruncN = trunc i64 %N to i32
227  br label %for.body
228
229for.body:                                         ; preds = %for.body, %entry
230  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
231  %ind1 = phi i32 [ %TruncN, %entry ], [ %dec, %for.body ]
232
233  %mul = mul i32 %ind1, 2
234  %mul_ext = zext i32 %mul to i64
235
236  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
237  %loadA = load i16, i16* %arrayidxA, align 2
238
239  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
240  %loadB = load i16, i16* %arrayidxB, align 2
241
242  %add = mul i16 %loadA, %loadB
243
244  store i16 %add, i16* %arrayidxA, align 2
245
246  %inc = add nuw nsw i64 %ind, 1
247  %dec = sub i32 %ind1, 1
248
249  %exitcond = icmp eq i64 %inc, %N
250  br i1 %exitcond, label %for.end, label %for.body
251
252for.end:                                          ; preds = %for.body
253  ret void
254}
255
256; We replicate the tests above, but this time sign extend 2 * index instead
257; of zero extending it.
258
259; The expression for %mul_ext as analyzed by SCEV is
260;     i64 (sext i32 {0,+,2}<%for.body> to i64)
261; We have added the nssw flag to turn this expression into the following SCEV:
262;     i64 {0,+,2}<%for.body>
263
264define void @f3(i16* noalias %a,
265; LV-LABEL: @f3(
266; LV-NEXT:  for.body.lver.check:
267; LV-NEXT:    [[A5:%.*]] = bitcast i16* [[A:%.*]] to i8*
268; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N:%.*]], -1
269; LV-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
270; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP1]])
271; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
272; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
273; LV-NEXT:    [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]
274; LV-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 0
275; LV-NEXT:    [[TMP4:%.*]] = icmp slt i32 [[MUL_RESULT]], 0
276; LV-NEXT:    [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
277; LV-NEXT:    [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]]
278; LV-NEXT:    [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]
279; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
280; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
281; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
282; LV-NEXT:    [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT3]]
283; LV-NEXT:    [[TMP9:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]
284; LV-NEXT:    [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP8]]
285; LV-NEXT:    [[TMP11:%.*]] = icmp ugt i8* [[TMP10]], [[A5]]
286; LV-NEXT:    [[TMP12:%.*]] = icmp ult i8* [[TMP9]], [[A5]]
287; LV-NEXT:    [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]
288; LV-NEXT:    [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]
289; LV-NEXT:    br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
290; LV:       for.body.ph.lver.orig:
291; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
292; LV:       for.body.lver.orig:
293; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
294; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC1_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
295; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
296; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = sext i32 [[MUL_LVER_ORIG]] to i64
297; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
298; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
299; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
300; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
301; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
302; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
303; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
304; LV-NEXT:    [[INC1_LVER_ORIG]] = add i32 [[IND1_LVER_ORIG]], 1
305; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
306; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
307; LV:       for.body.ph:
308; LV-NEXT:    br label [[FOR_BODY:%.*]]
309; LV:       for.body:
310; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
311; LV-NEXT:    [[IND1:%.*]] = phi i32 [ 0, [[FOR_BODY_PH]] ], [ [[INC1:%.*]], [[FOR_BODY]] ]
312; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
313; LV-NEXT:    [[MUL_EXT:%.*]] = sext i32 [[MUL]] to i64
314; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
315; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
316; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
317; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
318; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
319; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
320; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
321; LV-NEXT:    [[INC1]] = add i32 [[IND1]], 1
322; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
323; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
324; LV:       for.end.loopexit:
325; LV-NEXT:    br label [[FOR_END:%.*]]
326; LV:       for.end.loopexit6:
327; LV-NEXT:    br label [[FOR_END]]
328; LV:       for.end:
329; LV-NEXT:    ret void
330;
331  i16* noalias %b, i64 %N) {
332entry:
333  br label %for.body
334
335for.body:                                         ; preds = %for.body, %entry
336  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
337  %ind1 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
338
339  %mul = mul i32 %ind1, 2
340  %mul_ext = sext i32 %mul to i64
341
342  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
343  %loadA = load i16, i16* %arrayidxA, align 2
344
345  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
346  %loadB = load i16, i16* %arrayidxB, align 2
347
348  %add = mul i16 %loadA, %loadB
349
350  store i16 %add, i16* %arrayidxA, align 2
351
352  %inc = add nuw nsw i64 %ind, 1
353  %inc1 = add i32 %ind1, 1
354
355  %exitcond = icmp eq i64 %inc, %N
356  br i1 %exitcond, label %for.end, label %for.body
357
358for.end:                                          ; preds = %for.body
359  ret void
360}
361
362define void @f4(i16* noalias %a,
363; LV-LABEL: @f4(
364; LV-NEXT:  for.body.lver.check:
365; LV-NEXT:    [[TRUNCN:%.*]] = trunc i64 [[N:%.*]] to i32
366; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
367; LV-NEXT:    [[TMP1:%.*]] = shl i32 [[TRUNCN]], 1
368; LV-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
369; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP2]])
370; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
371; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
372; LV-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[MUL_RESULT]]
373; LV-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
374; LV-NEXT:    [[TMP5:%.*]] = icmp sgt i32 [[TMP4]], [[TMP1]]
375; LV-NEXT:    [[TMP6:%.*]] = icmp slt i32 [[TMP3]], [[TMP1]]
376; LV-NEXT:    [[TMP7:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
377; LV-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]]
378; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
379; LV-NEXT:    [[TMP10:%.*]] = sext i32 [[TMP1]] to i64
380; LV-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[A:%.*]], i64 [[TMP10]]
381; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
382; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
383; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
384; LV-NEXT:    [[SCEVGEP5:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
385; LV-NEXT:    [[TMP11:%.*]] = sub i64 0, [[MUL_RESULT3]]
386; LV-NEXT:    [[TMP12:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[MUL_RESULT3]]
387; LV-NEXT:    [[TMP13:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[TMP11]]
388; LV-NEXT:    [[TMP14:%.*]] = icmp ugt i8* [[TMP13]], [[SCEVGEP5]]
389; LV-NEXT:    [[TMP15:%.*]] = icmp ult i8* [[TMP12]], [[SCEVGEP5]]
390; LV-NEXT:    [[TMP16:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW4]]
391; LV-NEXT:    [[TMP17:%.*]] = or i1 [[TMP9]], [[TMP16]]
392; LV-NEXT:    br i1 [[TMP17]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
393; LV:       for.body.ph.lver.orig:
394; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
395; LV:       for.body.lver.orig:
396; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
397; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH_LVER_ORIG]] ], [ [[DEC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
398; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
399; LV-NEXT:    [[MUL_EXT_LVER_ORIG:%.*]] = sext i32 [[MUL_LVER_ORIG]] to i64
400; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT_LVER_ORIG]]
401; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
402; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
403; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
404; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
405; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
406; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
407; LV-NEXT:    [[DEC_LVER_ORIG]] = sub i32 [[IND1_LVER_ORIG]], 1
408; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
409; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
410; LV:       for.body.ph:
411; LV-NEXT:    br label [[FOR_BODY:%.*]]
412; LV:       for.body:
413; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
414; LV-NEXT:    [[IND1:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH]] ], [ [[DEC:%.*]], [[FOR_BODY]] ]
415; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
416; LV-NEXT:    [[MUL_EXT:%.*]] = sext i32 [[MUL]] to i64
417; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr i16, i16* [[A]], i64 [[MUL_EXT]]
418; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
419; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr i16, i16* [[B]], i64 [[IND]]
420; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
421; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
422; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
423; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
424; LV-NEXT:    [[DEC]] = sub i32 [[IND1]], 1
425; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
426; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
427; LV:       for.end.loopexit:
428; LV-NEXT:    br label [[FOR_END:%.*]]
429; LV:       for.end.loopexit6:
430; LV-NEXT:    br label [[FOR_END]]
431; LV:       for.end:
432; LV-NEXT:    ret void
433;
434  i16* noalias %b, i64 %N) {
435entry:
436  %TruncN = trunc i64 %N to i32
437  br label %for.body
438
439for.body:                                         ; preds = %for.body, %entry
440  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
441  %ind1 = phi i32 [ %TruncN, %entry ], [ %dec, %for.body ]
442
443  %mul = mul i32 %ind1, 2
444  %mul_ext = sext i32 %mul to i64
445
446  %arrayidxA = getelementptr i16, i16* %a, i64 %mul_ext
447  %loadA = load i16, i16* %arrayidxA, align 2
448
449  %arrayidxB = getelementptr i16, i16* %b, i64 %ind
450  %loadB = load i16, i16* %arrayidxB, align 2
451
452  %add = mul i16 %loadA, %loadB
453
454  store i16 %add, i16* %arrayidxA, align 2
455
456  %inc = add nuw nsw i64 %ind, 1
457  %dec = sub i32 %ind1, 1
458
459  %exitcond = icmp eq i64 %inc, %N
460  br i1 %exitcond, label %for.end, label %for.body
461
462for.end:                                          ; preds = %for.body
463  ret void
464}
465
466; The following function is similar to the one above, but has the GEP
467; to pointer %A inbounds. The index %mul doesn't have the nsw flag.
468; This means that the SCEV expression for %mul can wrap and we need
469; a SCEV predicate to continue analysis.
470;
471; We can still analyze this by adding the required no wrap SCEV predicates.
472
473define void @f5(i16* noalias %a,
474; LV-LABEL: @f5(
475; LV-NEXT:  for.body.lver.check:
476; LV-NEXT:    [[TRUNCN:%.*]] = trunc i64 [[N:%.*]] to i32
477; LV-NEXT:    [[TMP0:%.*]] = add i64 [[N]], -1
478; LV-NEXT:    [[TMP1:%.*]] = shl i32 [[TRUNCN]], 1
479; LV-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
480; LV-NEXT:    [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP2]])
481; LV-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
482; LV-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
483; LV-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], [[MUL_RESULT]]
484; LV-NEXT:    [[TMP4:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
485; LV-NEXT:    [[TMP5:%.*]] = icmp sgt i32 [[TMP4]], [[TMP1]]
486; LV-NEXT:    [[TMP6:%.*]] = icmp slt i32 [[TMP3]], [[TMP1]]
487; LV-NEXT:    [[TMP7:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
488; LV-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]]
489; LV-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
490; LV-NEXT:    [[TMP10:%.*]] = sext i32 [[TMP1]] to i64
491; LV-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[A:%.*]], i64 [[TMP10]]
492; LV-NEXT:    [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP0]])
493; LV-NEXT:    [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
494; LV-NEXT:    [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
495; LV-NEXT:    [[SCEVGEP5:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
496; LV-NEXT:    [[TMP11:%.*]] = sub i64 0, [[MUL_RESULT3]]
497; LV-NEXT:    [[TMP12:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[MUL_RESULT3]]
498; LV-NEXT:    [[TMP13:%.*]] = getelementptr i8, i8* [[SCEVGEP5]], i64 [[TMP11]]
499; LV-NEXT:    [[TMP14:%.*]] = icmp ugt i8* [[TMP13]], [[SCEVGEP5]]
500; LV-NEXT:    [[TMP15:%.*]] = icmp ult i8* [[TMP12]], [[SCEVGEP5]]
501; LV-NEXT:    [[TMP16:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW4]]
502; LV-NEXT:    [[TMP17:%.*]] = or i1 [[TMP9]], [[TMP16]]
503; LV-NEXT:    br i1 [[TMP17]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
504; LV:       for.body.ph.lver.orig:
505; LV-NEXT:    br label [[FOR_BODY_LVER_ORIG:%.*]]
506; LV:       for.body.lver.orig:
507; LV-NEXT:    [[IND_LVER_ORIG:%.*]] = phi i64 [ 0, [[FOR_BODY_PH_LVER_ORIG]] ], [ [[INC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
508; LV-NEXT:    [[IND1_LVER_ORIG:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH_LVER_ORIG]] ], [ [[DEC_LVER_ORIG:%.*]], [[FOR_BODY_LVER_ORIG]] ]
509; LV-NEXT:    [[MUL_LVER_ORIG:%.*]] = mul i32 [[IND1_LVER_ORIG]], 2
510; LV-NEXT:    [[ARRAYIDXA_LVER_ORIG:%.*]] = getelementptr inbounds i16, i16* [[A]], i32 [[MUL_LVER_ORIG]]
511; LV-NEXT:    [[LOADA_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXA_LVER_ORIG]], align 2
512; LV-NEXT:    [[ARRAYIDXB_LVER_ORIG:%.*]] = getelementptr inbounds i16, i16* [[B:%.*]], i64 [[IND_LVER_ORIG]]
513; LV-NEXT:    [[LOADB_LVER_ORIG:%.*]] = load i16, i16* [[ARRAYIDXB_LVER_ORIG]], align 2
514; LV-NEXT:    [[ADD_LVER_ORIG:%.*]] = mul i16 [[LOADA_LVER_ORIG]], [[LOADB_LVER_ORIG]]
515; LV-NEXT:    store i16 [[ADD_LVER_ORIG]], i16* [[ARRAYIDXA_LVER_ORIG]], align 2
516; LV-NEXT:    [[INC_LVER_ORIG]] = add nuw nsw i64 [[IND_LVER_ORIG]], 1
517; LV-NEXT:    [[DEC_LVER_ORIG]] = sub i32 [[IND1_LVER_ORIG]], 1
518; LV-NEXT:    [[EXITCOND_LVER_ORIG:%.*]] = icmp eq i64 [[INC_LVER_ORIG]], [[N]]
519; LV-NEXT:    br i1 [[EXITCOND_LVER_ORIG]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_LVER_ORIG]]
520; LV:       for.body.ph:
521; LV-NEXT:    br label [[FOR_BODY:%.*]]
522; LV:       for.body:
523; LV-NEXT:    [[IND:%.*]] = phi i64 [ 0, [[FOR_BODY_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
524; LV-NEXT:    [[IND1:%.*]] = phi i32 [ [[TRUNCN]], [[FOR_BODY_PH]] ], [ [[DEC:%.*]], [[FOR_BODY]] ]
525; LV-NEXT:    [[MUL:%.*]] = mul i32 [[IND1]], 2
526; LV-NEXT:    [[ARRAYIDXA:%.*]] = getelementptr inbounds i16, i16* [[A]], i32 [[MUL]]
527; LV-NEXT:    [[LOADA:%.*]] = load i16, i16* [[ARRAYIDXA]], align 2
528; LV-NEXT:    [[ARRAYIDXB:%.*]] = getelementptr inbounds i16, i16* [[B]], i64 [[IND]]
529; LV-NEXT:    [[LOADB:%.*]] = load i16, i16* [[ARRAYIDXB]], align 2
530; LV-NEXT:    [[ADD:%.*]] = mul i16 [[LOADA]], [[LOADB]]
531; LV-NEXT:    store i16 [[ADD]], i16* [[ARRAYIDXA]], align 2
532; LV-NEXT:    [[INC]] = add nuw nsw i64 [[IND]], 1
533; LV-NEXT:    [[DEC]] = sub i32 [[IND1]], 1
534; LV-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[N]]
535; LV-NEXT:    br i1 [[EXITCOND]], label [[FOR_END_LOOPEXIT6:%.*]], label [[FOR_BODY]]
536; LV:       for.end.loopexit:
537; LV-NEXT:    br label [[FOR_END:%.*]]
538; LV:       for.end.loopexit6:
539; LV-NEXT:    br label [[FOR_END]]
540; LV:       for.end:
541; LV-NEXT:    ret void
542;
543  i16* noalias %b, i64 %N) {
544entry:
545  %TruncN = trunc i64 %N to i32
546  br label %for.body
547
548for.body:                                         ; preds = %for.body, %entry
549  %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ]
550  %ind1 = phi i32 [ %TruncN, %entry ], [ %dec, %for.body ]
551
552  %mul = mul i32 %ind1, 2
553
554  %arrayidxA = getelementptr inbounds i16, i16* %a, i32 %mul
555  %loadA = load i16, i16* %arrayidxA, align 2
556
557  %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %ind
558  %loadB = load i16, i16* %arrayidxB, align 2
559
560  %add = mul i16 %loadA, %loadB
561
562  store i16 %add, i16* %arrayidxA, align 2
563
564  %inc = add nuw nsw i64 %ind, 1
565  %dec = sub i32 %ind1, 1
566
567  %exitcond = icmp eq i64 %inc, %N
568  br i1 %exitcond, label %for.end, label %for.body
569
570for.end:                                          ; preds = %for.body
571  ret void
572}
573