1; RUN: opt -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S < %s 2>&1 | FileCheck %s
2; RUN: opt -passes='loop-vectorize' -force-vector-width=4 -force-vector-interleave=1 -S < %s 2>&1 | FileCheck %s
3
4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
5
6; Make sure the selects generated from reduction are always emitted
7; in deterministic order.
8; CHECK-LABEL: @foo(
9; CHECK: vector.body:
10; CHECK:      [[VEC_PHI_1:%.+]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[ADD_5:%.+]], %vector.body ]
11; CHECK:      [[VEC_PHI_2:%.+]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[ADD_3:%.+]], %vector.body ]
12; CHECK:      icmp ule <4 x i64>
13; CHECK-NEXT: [[ADD_3]] = add <4 x i32> <i32 3, i32 3, i32 3, i32 3>, [[VEC_PHI_2]]
14; CHECK-NEXT: [[ADD_5]] = add <4 x i32> [[VEC_PHI_1]], <i32 5, i32 5, i32 5, i32 5>
15; CHECK:      select <4 x i1> {{.*}}, <4 x i32> [[ADD_5]], <4 x i32>
16; CHECK-NEXT: select <4 x i1> {{.*}}, <4 x i32> [[ADD_3]], <4 x i32>
17; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
18;
19define internal i64 @foo(i32* %t0) !prof !1 {
20t16:
21  br label %t20
22
23t17:                                               ; preds = %t20
24  %t18 = phi i32 [ %t24, %t20 ]
25  %t19 = phi i32 [ %t28, %t20 ]
26  br label %t31
27
28t20:                                               ; preds = %t20, %t16
29  %t21 = phi i64 [ 0, %t16 ], [ %t29, %t20 ]
30  %t22 = phi i32 [ 0, %t16 ], [ %t28, %t20 ]
31  %t23 = phi i32 [ 0, %t16 ], [ %t24, %t20 ]
32  %t24 = add i32 3, %t23
33  %t28 = add i32 %t22, 5
34  %t29 = add nuw nsw i64 %t21, 1
35  %t30 = icmp eq i64 %t29, 10
36  br i1 %t30, label %t17, label %t20, !prof !2
37
38t31:
39  ret i64 undef
40}
41
42; Make sure we do not fail when checking for ordered reduction. This test just
43; exercises the path and bails out without performing vectorization.
44; CHECK-LABEL: quux
45; CHECK-NOT: fadd <4 x
46define void @quux() {
47bb:
48  br label %header
49
50latch:                                              ; preds = %header
51  %tmp = phi double [ %tmp6, %header ]
52  br i1 undef, label %header, label %bb2
53
54bb2:                                              ; preds = %latch
55  %tmp3 = phi double [ %tmp, %latch ]
56  ret void
57
58header:                                              ; preds = %latch, %bb
59  %tmp5 = phi double [ 1.300000e+01, %bb ], [ %tmp, %latch ]
60  %tmp6 = fadd double %tmp5, 1.000000e+00
61  br label %latch
62}
63
64!1 = !{!"function_entry_count", i64 801}
65!2 = !{!"branch_weights", i32 746, i32 1}
66