1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -loop-vectorize -force-vector-width=2 -S -prefer-predicate-over-epilogue=predicate-dont-vectorize %s | FileCheck %s
3
4
5; Test case for PR46525. There are two candidates to pick for
6; `udiv i64 %y, %add` when expanding SCEV expressions. Make sure we pick %div,
7; which dominates the vector loop.
8
9define void @test(i16 %x, i64 %y, i32* %ptr) {
10; CHECK-LABEL: @test(
11; CHECK-NEXT:  entry:
12; CHECK-NEXT:    [[CONV19:%.*]] = sext i16 [[X:%.*]] to i64
13; CHECK-NEXT:    [[ADD:%.*]] = add i64 [[CONV19]], 492802768830814067
14; CHECK-NEXT:    br label [[LOOP_PREHEADER:%.*]]
15; CHECK:       loop.preheader:
16; CHECK-NEXT:    [[DIV:%.*]] = udiv i64 [[Y:%.*]], [[ADD]]
17; CHECK-NEXT:    [[INC:%.*]] = add i64 [[DIV]], 1
18; CHECK-NEXT:    [[TMP0:%.*]] = add nuw nsw i64 [[DIV]], 4
19; CHECK-NEXT:    [[TMP1:%.*]] = udiv i64 [[TMP0]], [[INC]]
20; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
21; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
22; CHECK:       vector.ph:
23; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i64 [[TMP2]], 1
24; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2
25; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
26; CHECK-NEXT:    [[IND_END:%.*]] = mul i64 [[N_VEC]], [[INC]]
27; CHECK-NEXT:    [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[TMP2]], 1
28; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i32 0
29; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
30; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
31; CHECK:       vector.body:
32; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE12:%.*]] ]
33; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[INC]]
34; CHECK-NEXT:    [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i64> poison, i64 [[OFFSET_IDX]], i32 0
35; CHECK-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT1]], <2 x i64> poison, <2 x i32> zeroinitializer
36; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[INC]], i32 0
37; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <2 x i64> [[DOTSPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
38; CHECK-NEXT:    [[TMP3:%.*]] = mul <2 x i64> <i64 0, i64 1>, [[DOTSPLAT]]
39; CHECK-NEXT:    [[INDUCTION:%.*]] = add <2 x i64> [[BROADCAST_SPLAT2]], [[TMP3]]
40; CHECK-NEXT:    [[TMP4:%.*]] = mul i64 0, [[INC]]
41; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], [[TMP4]]
42; CHECK-NEXT:    [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <2 x i64> poison, i64 [[INDEX]], i32 0
43; CHECK-NEXT:    [[BROADCAST_SPLAT4:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT3]], <2 x i64> poison, <2 x i32> zeroinitializer
44; CHECK-NEXT:    [[VEC_IV:%.*]] = add <2 x i64> [[BROADCAST_SPLAT4]], <i64 0, i64 1>
45; CHECK-NEXT:    [[OFFSET_IDX5:%.*]] = mul i64 [[INDEX]], [[INC]]
46; CHECK-NEXT:    [[TMP6:%.*]] = trunc i64 [[OFFSET_IDX5]] to i8
47; CHECK-NEXT:    [[TMP7:%.*]] = trunc i64 [[INC]] to i8
48; CHECK-NEXT:    [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <2 x i8> poison, i8 [[TMP6]], i32 0
49; CHECK-NEXT:    [[BROADCAST_SPLAT7:%.*]] = shufflevector <2 x i8> [[BROADCAST_SPLATINSERT6]], <2 x i8> poison, <2 x i32> zeroinitializer
50; CHECK-NEXT:    [[DOTSPLATINSERT8:%.*]] = insertelement <2 x i8> poison, i8 [[TMP7]], i32 0
51; CHECK-NEXT:    [[DOTSPLAT9:%.*]] = shufflevector <2 x i8> [[DOTSPLATINSERT8]], <2 x i8> poison, <2 x i32> zeroinitializer
52; CHECK-NEXT:    [[TMP8:%.*]] = mul <2 x i8> <i8 0, i8 1>, [[DOTSPLAT9]]
53; CHECK-NEXT:    [[INDUCTION10:%.*]] = add <2 x i8> [[BROADCAST_SPLAT7]], [[TMP8]]
54; CHECK-NEXT:    [[TMP9:%.*]] = mul i8 0, [[TMP7]]
55; CHECK-NEXT:    [[TMP10:%.*]] = add i8 [[TMP6]], [[TMP9]]
56; CHECK-NEXT:    [[TMP11:%.*]] = icmp ule <2 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]]
57; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <2 x i1> [[TMP11]], i32 0
58; CHECK-NEXT:    br i1 [[TMP12]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
59; CHECK:       pred.store.if:
60; CHECK-NEXT:    store i32 0, i32* [[PTR:%.*]], align 4
61; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE]]
62; CHECK:       pred.store.continue:
63; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <2 x i1> [[TMP11]], i32 1
64; CHECK-NEXT:    br i1 [[TMP13]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12]]
65; CHECK:       pred.store.if11:
66; CHECK-NEXT:    store i32 0, i32* [[PTR]], align 4
67; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE12]]
68; CHECK:       pred.store.continue12:
69; CHECK-NEXT:    [[TMP14:%.*]] = add i8 [[TMP10]], 1
70; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 2
71; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
72; CHECK-NEXT:    br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
73; CHECK:       middle.block:
74; CHECK-NEXT:    br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]]
75; CHECK:       scalar.ph:
76; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_PREHEADER]] ]
77; CHECK-NEXT:    br label [[LOOP:%.*]]
78; CHECK:       loop:
79; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
80; CHECK-NEXT:    store i32 0, i32* [[PTR]], align 4
81; CHECK-NEXT:    [[V2:%.*]] = trunc i64 [[IV]] to i8
82; CHECK-NEXT:    [[V3:%.*]] = add i8 [[V2]], 1
83; CHECK-NEXT:    [[CMP15:%.*]] = icmp slt i8 [[V3]], 5
84; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], [[INC]]
85; CHECK-NEXT:    br i1 [[CMP15]], label [[LOOP]], label [[LOOP_EXIT]], !llvm.loop [[LOOP2:![0-9]+]]
86; CHECK:       loop.exit:
87; CHECK-NEXT:    [[DIV_1:%.*]] = udiv i64 [[Y]], [[ADD]]
88; CHECK-NEXT:    [[V1:%.*]] = add i64 [[DIV_1]], 1
89; CHECK-NEXT:    br label [[LOOP_2:%.*]]
90; CHECK:       loop.2:
91; CHECK-NEXT:    [[IV_1:%.*]] = phi i64 [ [[IV_NEXT_1:%.*]], [[LOOP_2]] ], [ 0, [[LOOP_EXIT]] ]
92; CHECK-NEXT:    [[IV_NEXT_1]] = add i64 [[IV_1]], [[V1]]
93; CHECK-NEXT:    call void @use(i64 [[IV_NEXT_1]])
94; CHECK-NEXT:    [[EC:%.*]] = icmp ult i64 [[IV_NEXT_1]], 200
95; CHECK-NEXT:    br i1 [[EC]], label [[LOOP_2]], label [[LOOP_2_EXIT:%.*]]
96; CHECK:       loop.2.exit:
97; CHECK-NEXT:    [[C:%.*]] = call i1 @cond()
98; CHECK-NEXT:    br i1 [[C]], label [[LOOP_PREHEADER]], label [[EXIT:%.*]]
99; CHECK:       exit:
100; CHECK-NEXT:    ret void
101;
102entry:
103  %conv19 = sext i16 %x to i64
104  %add = add i64 %conv19, 492802768830814067
105  br label %loop.preheader
106
107loop.preheader:
108  %div = udiv i64 %y, %add
109  %inc = add i64 %div, 1
110  br label %loop
111
112loop:
113  %iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
114  store i32 0, i32* %ptr, align 4
115  %v2 = trunc i64 %iv to i8
116  %v3 = add i8 %v2, 1
117  %cmp15 = icmp slt i8 %v3, 5
118  %iv.next = add i64 %iv, %inc
119  br i1 %cmp15, label %loop, label %loop.exit
120
121loop.exit:
122  %div.1 = udiv i64 %y, %add
123  %v1 = add i64 %div.1, 1
124  br label %loop.2
125
126loop.2:
127  %iv.1 = phi i64 [ %iv.next.1, %loop.2 ], [ 0, %loop.exit ]
128  %iv.next.1 = add i64 %iv.1, %v1
129  call void @use(i64 %iv.next.1)
130  %ec = icmp ult i64 %iv.next.1, 200
131  br i1 %ec, label %loop.2, label %loop.2.exit
132
133loop.2.exit:
134  %c = call i1 @cond()
135  br i1 %c, label %loop.preheader, label %exit
136
137exit:
138  ret void
139}
140
141declare void @use(i64)
142declare i1 @cond()
143