1; RUN: opt < %s -licm -loop-vectorize -force-vector-width=4 -dce -instcombine -licm -S | FileCheck %s
2
3; First licm pass is to hoist/sink invariant stores if possible. Today LICM does
4; not hoist/sink the invariant stores. Even if that changes, we should still
5; vectorize this loop in case licm is not run.
6
7; The next licm pass after vectorization is to hoist/sink loop invariant
8; instructions.
9target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
10
11; all tests check that it is legal to vectorize the stores to invariant
12; address.
13
14
15; CHECK-LABEL: inv_val_store_to_inv_address_with_reduction(
16; memory check is found.conflict = b[max(n-1,1)] > a && (i8* a)+1 > (i8* b)
17; CHECK: vector.memcheck:
18; CHECK:    found.conflict
19
20; CHECK-LABEL: vector.body:
21; CHECK:         %vec.phi = phi <4 x i32>  [ zeroinitializer, %vector.ph ], [ [[ADD:%[a-zA-Z0-9.]+]], %vector.body ]
22; CHECK:         %wide.load = load <4 x i32>
23; CHECK:         [[ADD]] = add <4 x i32> %vec.phi, %wide.load
24; CHECK-NEXT:    store i32 %ntrunc, i32* %a
25; CHECK-NEXT:    %index.next = add nuw i64 %index, 4
26; CHECK-NEXT:    icmp eq i64 %index.next, %n.vec
27; CHECK-NEXT:    br i1
28
29; CHECK-LABEL: middle.block:
30; CHECK:         call i32 @llvm.vector.reduce.add.v4i32(<4 x i32>
31define i32 @inv_val_store_to_inv_address_with_reduction(i32* %a, i64 %n, i32* %b) {
32entry:
33  %ntrunc = trunc i64 %n to i32
34  br label %for.body
35
36for.body:                                         ; preds = %for.body, %entry
37  %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
38  %i0 = phi i32 [ %i3, %for.body ], [ 0, %entry ]
39  %i1 = getelementptr inbounds i32, i32* %b, i64 %i
40  %i2 = load i32, i32* %i1, align 8
41  %i3 = add i32 %i0, %i2
42  store i32 %ntrunc, i32* %a
43  %i.next = add nuw nsw i64 %i, 1
44  %cond = icmp slt i64 %i.next, %n
45  br i1 %cond, label %for.body, label %for.end
46
47for.end:                                          ; preds = %for.body
48  %i4 = phi i32 [ %i3, %for.body ]
49  ret i32 %i4
50}
51
52; CHECK-LABEL: inv_val_store_to_inv_address(
53; CHECK-LABEL: vector.body:
54; CHECK:         store i32 %ntrunc, i32* %a
55; CHECK:         store <4 x i32>
56; CHECK-NEXT:    %index.next = add nuw i64 %index, 4
57; CHECK-NEXT:    icmp eq i64 %index.next, %n.vec
58; CHECK-NEXT:    br i1
59define void @inv_val_store_to_inv_address(i32* %a, i64 %n, i32* %b) {
60entry:
61  %ntrunc = trunc i64 %n to i32
62  br label %for.body
63
64for.body:                                         ; preds = %for.body, %entry
65  %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
66  %i1 = getelementptr inbounds i32, i32* %b, i64 %i
67  %i2 = load i32, i32* %i1, align 8
68  store i32 %ntrunc, i32* %a
69  store i32 %ntrunc, i32* %i1
70  %i.next = add nuw nsw i64 %i, 1
71  %cond = icmp slt i64 %i.next, %n
72  br i1 %cond, label %for.body, label %for.end
73
74for.end:                                          ; preds = %for.body
75  ret void
76}
77
78
79; Both of these tests below are handled as predicated stores.
80
81; Conditional store
82; if (b[i] == k) a = ntrunc
83; TODO: We can be better with the code gen for the first test and we can have
84; just one scalar store if vector.or.reduce(vector_cmp(b[i] == k)) is 1.
85
86; CHECK-LABEL:inv_val_store_to_inv_address_conditional(
87; CHECK-LABEL: vector.body:
88; CHECK:           %wide.load = load <4 x i32>, <4 x i32>*
89; CHECK:           [[CMP:%[a-zA-Z0-9.]+]] = icmp eq <4 x i32> %wide.load, %{{.*}}
90; CHECK:           store <4 x i32>
91; CHECK-NEXT:      [[EE:%[a-zA-Z0-9.]+]] =  extractelement <4 x i1> [[CMP]], i32 0
92; CHECK-NEXT:      br i1 [[EE]], label %pred.store.if, label %pred.store.continue
93
94; CHECK-LABEL: pred.store.if:
95; CHECK-NEXT:      store i32 %ntrunc, i32* %a
96; CHECK-NEXT:      br label %pred.store.continue
97
98; CHECK-LABEL: pred.store.continue:
99; CHECK-NEXT:      [[EE1:%[a-zA-Z0-9.]+]] =  extractelement <4 x i1> [[CMP]], i32 1
100define void @inv_val_store_to_inv_address_conditional(i32* %a, i64 %n, i32* %b, i32 %k) {
101entry:
102  %ntrunc = trunc i64 %n to i32
103  br label %for.body
104
105for.body:                                         ; preds = %for.body, %entry
106  %i = phi i64 [ %i.next, %latch ], [ 0, %entry ]
107  %i1 = getelementptr inbounds i32, i32* %b, i64 %i
108  %i2 = load i32, i32* %i1, align 8
109  %cmp = icmp eq i32 %i2, %k
110  store i32 %ntrunc, i32* %i1
111  br i1 %cmp, label %cond_store, label %latch
112
113cond_store:
114  store i32 %ntrunc, i32* %a
115  br label %latch
116
117latch:
118  %i.next = add nuw nsw i64 %i, 1
119  %cond = icmp slt i64 %i.next, %n
120  br i1 %cond, label %for.body, label %for.end
121
122for.end:                                          ; preds = %for.body
123  ret void
124}
125
126; if (b[i] == k)
127;    a = ntrunc
128; else a = k;
129; TODO: We could vectorize this once we support multiple uniform stores to the
130; same address.
131; CHECK-LABEL:inv_val_store_to_inv_address_conditional_diff_values(
132; CHECK-NOT:           load <4 x i32>
133define void @inv_val_store_to_inv_address_conditional_diff_values(i32* %a, i64 %n, i32* %b, i32 %k) {
134entry:
135  %ntrunc = trunc i64 %n to i32
136  br label %for.body
137
138for.body:                                         ; preds = %for.body, %entry
139  %i = phi i64 [ %i.next, %latch ], [ 0, %entry ]
140  %i1 = getelementptr inbounds i32, i32* %b, i64 %i
141  %i2 = load i32, i32* %i1, align 8
142  %cmp = icmp eq i32 %i2, %k
143  store i32 %ntrunc, i32* %i1
144  br i1 %cmp, label %cond_store, label %cond_store_k
145
146cond_store:
147  store i32 %ntrunc, i32* %a
148  br label %latch
149
150cond_store_k:
151  store i32 %k, i32 * %a
152  br label %latch
153
154latch:
155  %i.next = add nuw nsw i64 %i, 1
156  %cond = icmp slt i64 %i.next, %n
157  br i1 %cond, label %for.body, label %for.end
158
159for.end:                                          ; preds = %for.body
160  ret void
161}
162
163; Multiple variant stores to the same uniform address
164; We do not vectorize such loops currently.
165;  for(; i < itr; i++) {
166;    for(; j < itr; j++) {
167;      var1[i] = var2[j] + var1[i];
168;      var1[i]++;
169;    }
170;  }
171
172; CHECK-LABEL: multiple_uniform_stores
173; CHECK-NOT:     <4 x i32>
174define i32 @multiple_uniform_stores(i32* nocapture %var1, i32* nocapture readonly %var2, i32 %itr) #0 {
175entry:
176  %cmp20 = icmp eq i32 %itr, 0
177  br i1 %cmp20, label %for.end10, label %for.cond1.preheader
178
179for.cond1.preheader:                              ; preds = %entry, %for.inc8
180  %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ]
181  %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ]
182  %cmp218 = icmp ult i32 %j.022, %itr
183  br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8
184
185for.body3.lr.ph:                                  ; preds = %for.cond1.preheader
186  %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23
187  %0 = zext i32 %j.022 to i64
188  br label %for.body3
189
190for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
191  %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ]
192  %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv
193  %1 = load i32, i32* %arrayidx, align 4
194  %2 = load i32, i32* %arrayidx5, align 4
195  %add = add nsw i32 %2, %1
196  store i32 %add, i32* %arrayidx5, align 4
197  %3 = load i32, i32* %arrayidx5, align 4
198  %4 = add nsw i32 %3, 1
199  store i32 %4, i32* %arrayidx5, align 4
200  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
201  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
202  %exitcond = icmp eq i32 %lftr.wideiv, %itr
203  br i1 %exitcond, label %for.inc8, label %for.body3
204
205for.inc8:                                         ; preds = %for.body3, %for.cond1.preheader
206  %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ]
207  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
208  %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32
209  %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr
210  br i1 %exitcond26, label %for.end10, label %for.cond1.preheader
211
212for.end10:                                        ; preds = %for.inc8, %entry
213  ret i32 undef
214}
215
216; second uniform store to the same address is conditional.
217; we do not vectorize this.
218; CHECK-LABEL: multiple_uniform_stores_conditional
219; CHECK-NOT:    <4 x i32>
220define i32 @multiple_uniform_stores_conditional(i32* nocapture %var1, i32* nocapture readonly %var2, i32 %itr) #0 {
221entry:
222  %cmp20 = icmp eq i32 %itr, 0
223  br i1 %cmp20, label %for.end10, label %for.cond1.preheader
224
225for.cond1.preheader:                              ; preds = %entry, %for.inc8
226  %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ]
227  %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ]
228  %cmp218 = icmp ult i32 %j.022, %itr
229  br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8
230
231for.body3.lr.ph:                                  ; preds = %for.cond1.preheader
232  %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23
233  %0 = zext i32 %j.022 to i64
234  br label %for.body3
235
236for.body3:                                        ; preds = %for.body3, %for.body3.lr.ph
237  %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %latch ]
238  %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv
239  %1 = load i32, i32* %arrayidx, align 4
240  %2 = load i32, i32* %arrayidx5, align 4
241  %add = add nsw i32 %2, %1
242  store i32 %add, i32* %arrayidx5, align 4
243  %3 = load i32, i32* %arrayidx5, align 4
244  %4 = add nsw i32 %3, 1
245  %5 = icmp ugt i32 %3, 42
246  br i1 %5, label %cond_store, label %latch
247
248cond_store:
249  store i32 %4, i32* %arrayidx5, align 4
250  br label %latch
251
252latch:
253  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
254  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
255  %exitcond = icmp eq i32 %lftr.wideiv, %itr
256  br i1 %exitcond, label %for.inc8, label %for.body3
257
258for.inc8:                                         ; preds = %for.body3, %for.cond1.preheader
259  %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %latch ]
260  %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1
261  %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32
262  %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr
263  br i1 %exitcond26, label %for.end10, label %for.cond1.preheader
264
265for.end10:                                        ; preds = %for.inc8, %entry
266  ret i32 undef
267}
268
269; cannot vectorize loop with unsafe dependency between uniform load (%i10) and store
270; (%i12) to the same address
271; PR39653
272; Note: %i10 could be replaced by phi(%arg4, %i12), a potentially vectorizable
273; 1st-order-recurrence
274define void @unsafe_dep_uniform_load_store(i32 %arg, i32 %arg1, i64 %arg2, i16* %arg3, i32 %arg4, i64 %arg5) {
275; CHECK-LABEL: unsafe_dep_uniform_load_store
276; CHECK-NOT: <4 x i32>
277bb:
278  %i = alloca i32
279  store i32 %arg4, i32* %i
280  %i6 = getelementptr inbounds i16, i16* %arg3, i64 %arg5
281  br label %bb7
282
283bb7:
284  %i8 = phi i64 [ 0, %bb ], [ %i24, %bb7 ]
285  %i9 = phi i32 [ %arg1, %bb ], [ %i23, %bb7 ]
286  %i10 = load i32, i32* %i
287  %i11 = mul nsw i32 %i9, %i10
288  %i12 = srem i32 %i11, 65536
289  %i13 = add nsw i32 %i12, %i9
290  %i14 = trunc i32 %i13 to i16
291  %i15 = trunc i64 %i8 to i32
292  %i16 = add i32 %arg, %i15
293  %i17 = zext i32 %i16 to i64
294  %i18 = getelementptr inbounds i16, i16* %i6, i64 %i17
295  store i16 %i14, i16* %i18, align 2
296  %i19 = add i32 %i13, %i9
297  %i20 = trunc i32 %i19 to i16
298  %i21 = and i16 %i20, 255
299  %i22 = getelementptr inbounds i16, i16* %arg3, i64 %i17
300  store i16 %i21, i16* %i22, align 2
301  %i23 = add nsw i32 %i9, 1
302  %i24 = add nuw nsw i64 %i8, 1
303  %i25 = icmp eq i64 %i24, %arg2
304  store i32 %i12, i32* %i
305  br i1 %i25, label %bb26, label %bb7
306
307bb26:
308  ret void
309}
310
311; Make sure any check-not directives are not triggered by function declarations.
312; CHECK: declare
313