1; REQUIRES: asserts
2; RUN: opt < %s -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
3
4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
5
6; CHECK-LABEL: more_than_one_use
7;
8; PR30627. Check that a compare instruction with more than one use is not
9; recognized as uniform and is vectorized.
10;
11; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n
12; CHECK:     vector.body
13; CHECK:       %[[I:.+]] = add nuw nsw <4 x i64> %vec.ind, <i64 1, i64 1, i64 1, i64 1>
14; CHECK:       icmp slt <4 x i64> %[[I]], %broadcast.splat
15; CHECK:       br i1 {{.*}}, label %middle.block, label %vector.body
16;
17define i32 @more_than_one_use(i32* %a, i64 %n) {
18entry:
19  br label %for.body
20
21for.body:
22  %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
23  %r = phi i32 [ %tmp3, %for.body ], [ 0, %entry ]
24  %i.next = add nuw nsw i64 %i, 1
25  %cond = icmp slt i64 %i.next, %n
26  %tmp0 = select i1 %cond, i64 %i.next, i64 0
27  %tmp1 = getelementptr inbounds i32, i32* %a, i64 %tmp0
28  %tmp2 = load i32, i32* %tmp1, align 8
29  %tmp3 = add i32 %r, %tmp2
30  br i1 %cond, label %for.body, label %for.end
31
32for.end:
33  %tmp4 = phi i32 [ %tmp3, %for.body ]
34  ret i32 %tmp4
35}
36
37; Check for crash exposed by D76992.
38; CHECK-LABEL: 'test'
39; CHECK:      VPlan 'Initial VPlan for VF={4},UF>=1' {
40; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
41; CHECK-EMPTY:
42; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
43; CHECK-EMPTY:
44; CHECK-NEXT: <x1> vector loop: {
45; CHECK-NEXT: loop:
46; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
47; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
48; CHECK-NEXT:   EMIT vp<[[COND:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
49; CHECK-NEXT:   WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>
50; CHECK-NEXT:   WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>
51; CHECK-NEXT: Successor(s): pred.store
52; CHECK-EMPTY:
53; CHECK-NEXT:  <xVFxUF> pred.store: {
54; CHECK-NEXT:    pred.store.entry:
55; CHECK-NEXT:      BRANCH-ON-MASK vp<[[COND]]>
56; CHECK-NEXT:    Successor(s): pred.store.if, pred.store.continue
57; CHECK-NEXT:    CondBit: vp<[[COND]]> (loop)
58; CHECK-EMPTY:
59; CHECK-NEXT:    pred.store.if:
60; CHECK-NEXT:      REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
61; CHECK-NEXT:      REPLICATE store ir<%s>, ir<%gep>
62; CHECK-NEXT:    Successor(s): pred.store.continue
63; CHECK-EMPTY:
64; CHECK-NEXT:    pred.store.continue:
65; CHECK-NEXT:    No successors
66; CHECK-NEXT:  }
67; CHECK-NEXT:  Successor(s): loop.0
68; CHECK-EMPTY:
69; CHECK-NEXT: loop.0:
70; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
71; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
72; CHECK-NEXT: No successor
73; CHECK-NEXT: }
74define void @test(i32* %ptr) {
75entry:
76  br label %loop
77
78loop:                       ; preds = %loop, %entry
79  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
80  %cond0 = icmp ult i64 %iv, 13
81  %s = select i1 %cond0, i32 10, i32 20
82  %gep = getelementptr inbounds i32, i32* %ptr, i64 %iv
83  store i32 %s, i32* %gep
84  %iv.next = add nuw nsw i64 %iv, 1
85  %exitcond = icmp eq i64 %iv.next, 14
86  br i1 %exitcond, label %exit, label %loop
87
88exit:
89  ret void
90}
91