1; REQUIRES: asserts
2; RUN: opt < %s -loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s
3
4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
5
6; Test cases for PR50009, which require sinking a replicate-region due to a
7; first-order recurrence.
8
9define void @sink_replicate_region_1(i32 %x, i8* %ptr) optsize {
10; CHECK-LABEL: sink_replicate_region_1
11; CHECK:      VPlan 'Initial VPlan for VF={2},UF>=1' {
12; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
13; CHECK-EMPTY:
14; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
15; CHECK-EMPTY:
16; CHECK-NEXT: <x1> vector loop: {
17; CHECK-NEXT: loop:
18; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
19; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv>
20; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
21; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
22; CHECK-NEXT: Successor(s): loop.0
23; CHECK-EMPTY:
24; CHECK-NEXT: loop.0:
25; CHECK-NEXT: Successor(s): pred.load
26; CHECK-EMPTY:
27; CHECK-NEXT: <xVFxUF> pred.load: {
28; CHECK-NEXT:   pred.load.entry:
29; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
30; CHECK-NEXT:   Successor(s): pred.load.if, pred.load.continue
31; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
32; CHECK-EMPTY:
33; CHECK-NEXT:   pred.load.if:
34; CHECK-NEXT:     REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
35; CHECK-NEXT:     REPLICATE ir<%lv> = load ir<%gep> (S->V)
36; CHECK-NEXT:   Successor(s): pred.load.continue
37; CHECK-EMPTY:
38; CHECK-NEXT:   pred.load.continue:
39; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%lv>
40; CHECK-NEXT:   No successors
41; CHECK-NEXT: }
42; CHECK-NEXT: Successor(s): loop.1
43; CHECK-EMPTY:
44; CHECK-NEXT: loop.1:
45; CHECK-NEXT:   WIDEN ir<%conv> = sext vp<[[PRED1]]>
46; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0> ir<%conv>
47; CHECK-NEXT: Successor(s): pred.srem
48; CHECK-EMPTY:
49; CHECK-NEXT: <xVFxUF> pred.srem: {
50; CHECK-NEXT:   pred.srem.entry:
51; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
52; CHECK-NEXT:   Successor(s): pred.srem.if, pred.srem.continue
53; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
54; CHECK-EMPTY:
55; CHECK-NEXT:   pred.srem.if:
56; CHECK-NEXT:     REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> (S->V)
57; CHECK-NEXT:   Successor(s): pred.srem.continue
58; CHECK-EMPTY:
59; CHECK-NEXT:   pred.srem.continue:
60; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%rem>
61; CHECK-NEXT:   No successors
62; CHECK-NEXT: }
63; CHECK-NEXT: Successor(s): loop.1.split
64; CHECK-EMPTY:
65; CHECK-NEXT: loop.1.split:
66; CHECK-NEXT:   WIDEN ir<%add> = add ir<%conv>, vp<[[PRED2]]>
67; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
68; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
69; CHECK-NEXT: No successors
70; CHECK-NEXT: }
71; CHECK-NEXT: No successors
72; CHECK-NEXT: }
73;
74entry:
75  br label %loop
76
77loop:
78  %0 = phi i32 [ 0, %entry ], [ %conv, %loop ]
79  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
80  %rem = srem i32 %0, %x
81  %gep = getelementptr i8, i8* %ptr, i32 %iv
82  %lv = load i8, i8* %gep
83  %conv = sext i8 %lv to i32
84  %add = add i32 %conv, %rem
85  %iv.next = add nsw i32 %iv, 1
86  %ec = icmp eq i32 %iv.next, 20001
87  br i1 %ec, label %exit, label %loop
88
89exit:
90  ret void
91}
92
93define void @sink_replicate_region_2(i32 %x, i8 %y, i32* %ptr) optsize {
94; CHECK-LABEL: sink_replicate_region_2
95; CHECK:      VPlan 'Initial VPlan for VF={2},UF>=1' {
96; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
97; CHECK-EMPTY:
98; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
99; CHECK-EMPTY:
100; CHECK-NEXT: <x1> vector loop: {
101; CHECK-NEXT: loop:
102; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
103; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
104; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
105; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
106; CHECK-NEXT: Successor(s): loop.0
107; CHECK-EMPTY:
108; CHECK-NEXT: loop.0:
109; CHECK-NEXT:   WIDEN ir<%recur.next> = sext ir<%y>
110; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur> ir<%recur.next>
111; CHECK-NEXT: Successor(s): loop.0.split
112; CHECK-EMPTY:
113; CHECK-NEXT: loop.0.split:
114; CHECK-NEXT:   Successor(s): pred.store
115; CHECK-EMPTY:
116; CHECK-NEXT: <xVFxUF> pred.store: {
117; CHECK-NEXT:  pred.store.entry:
118; CHECK-NEXT:    BRANCH-ON-MASK vp<[[MASK]]>
119; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
120; CHECK-NEXT:  CondBit: vp<[[MASK]]> (loop)
121; CHECK-EMPTY:
122; CHECK-NEXT:  pred.store.if:
123; CHECK-NEXT:     REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
124; CHECK-NEXT:     REPLICATE ir<%add> = add ir<%rem>, ir<%recur.next>
125; CHECK-NEXT:     REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
126; CHECK-NEXT:     REPLICATE store ir<%add>, ir<%gep>
127; CHECK-NEXT:   Successor(s): pred.store.continue
128; CHECK-EMPTY:
129; CHECK-NEXT:   pred.store.continue:
130; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
131; CHECK-NEXT:   No successors
132; CHECK-NEXT: }
133; CHECK-NEXT: Successor(s): loop.1
134; CHECK-EMPTY:
135; CHECK-NEXT: loop.1:
136; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
137; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
138; CHECK-NEXT: No successors
139; CHECK-NEXT: }
140; CHECK-NEXT: No successors
141; CHECK-NEXT: }
142;
143entry:
144  br label %loop
145
146loop:
147  %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ]
148  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
149  %rem = srem i32 %recur, %x
150  %recur.next = sext i8 %y to i32
151  %add = add i32 %rem, %recur.next
152  %gep = getelementptr i32, i32* %ptr, i32 %iv
153  store i32 %add, i32* %gep
154  %iv.next = add nsw i32 %iv, 1
155  %ec = icmp eq i32 %iv.next, 20001
156  br i1 %ec, label %exit, label %loop
157
158exit:
159  ret void
160}
161
162define i32 @sink_replicate_region_3_reduction(i32 %x, i8 %y, i32* %ptr) optsize {
163; CHECK-LABEL: sink_replicate_region_3_reduction
164; CHECK:      VPlan 'Initial VPlan for VF={2},UF>=1' {
165; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
166; CHECK-EMPTY:
167; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
168; CHECK-EMPTY:
169; CHECK-NEXT: <x1> vector loop: {
170; CHECK-NEXT: loop:
171; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
172; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
173; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
174; CHECK-NEXT:   WIDEN-REDUCTION-PHI ir<%and.red> = phi ir<1234>, ir<%and.red.next>
175; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
176; CHECK-NEXT: Successor(s): loop.0
177; CHECK-EMPTY:
178; CHECK-NEXT: loop.0:
179; CHECK-NEXT:   WIDEN ir<%recur.next> = sext ir<%y>
180; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur> ir<%recur.next>
181; CHECK-NEXT: Successor(s): pred.srem
182; CHECK-EMPTY:
183; CHECK-NEXT: <xVFxUF> pred.srem: {
184; CHECK-NEXT:   pred.srem.entry:
185; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
186; CHECK-NEXT:   Successor(s): pred.srem.if, pred.srem.continue
187; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
188; CHECK-EMPTY:
189; CHECK-NEXT:   pred.srem.if:
190; CHECK-NEXT:     REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> (S->V)
191; CHECK-NEXT:   Successor(s): pred.srem.continue
192; CHECK-EMPTY:
193; CHECK-NEXT:   pred.srem.continue:
194; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
195; CHECK-NEXT:   No successors
196; CHECK-NEXT: }
197; CHECK-NEXT: Successor(s): loop.0.split
198; CHECK-EMPTY:
199; CHECK-NEXT: loop.0.split:
200; CHECK-NEXT:   WIDEN ir<%add> = add vp<[[PRED]]>, ir<%recur.next>
201; CHECK-NEXT:   WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add>
202; CHECK-NEXT:   EMIT vp<[[SEL:%.+]]> = select vp<[[MASK]]> ir<%and.red.next> ir<%and.red>
203; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
204; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
205; CHECK-NEXT: No successors
206; CHECK-NEXT: }
207; CHECK-NEXT: No successors
208; CHECK-NEXT: }
209;
210entry:
211  br label %loop
212
213loop:
214  %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ]
215  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
216  %and.red = phi i32 [ 1234, %entry ], [ %and.red.next, %loop ]
217  %rem = srem i32 %recur, %x
218  %recur.next = sext i8 %y to i32
219  %add = add i32 %rem, %recur.next
220  %and.red.next = and i32 %and.red, %add
221  %iv.next = add nsw i32 %iv, 1
222  %ec = icmp eq i32 %iv.next, 20001
223  br i1 %ec, label %exit, label %loop
224
225exit:
226  %res = phi i32 [ %and.red.next, %loop ]
227  ret i32 %res
228}
229
230; To sink the replicate region containing %rem, we need to split the block
231; containing %conv at the end, because %conv is the last recipe in the block.
232define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, i8* %ptr) optsize {
233; CHECK-LABEL: sink_replicate_region_4_requires_split_at_end_of_block
234; CHECK:      VPlan 'Initial VPlan for VF={2},UF>=1' {
235; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
236; CHECK-EMPTY:
237; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
238; CHECK-EMPTY:
239; CHECK-NEXT: <x1> vector loop: {
240; CHECK-NEXT: loop:
241; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
242; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv>
243; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
244; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
245; CHECK-NEXT:   REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
246; CHECK-NEXT: Successor(s): loop.0
247; CHECK-EMPTY:
248; CHECK-NEXT: loop.0:
249; CHECK-NEXT: Successor(s): pred.load
250; CHECK-EMPTY:
251; CHECK-NEXT: <xVFxUF> pred.load: {
252; CHECK-NEXT:   pred.load.entry:
253; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
254; CHECK-NEXT:   Successor(s): pred.load.if, pred.load.continue
255; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
256; CHECK-EMPTY:
257; CHECK-NEXT:   pred.load.if:
258; CHECK-NEXT:     REPLICATE ir<%lv> = load ir<%gep> (S->V)
259; CHECK-NEXT:   Successor(s): pred.load.continue
260; CHECK-EMPTY:
261; CHECK-NEXT:   pred.load.continue:
262; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv>
263; CHECK-NEXT:   No successors
264; CHECK-NEXT: }
265; CHECK-NEXT: Successor(s): loop.1
266; CHECK-EMPTY:
267; CHECK-NEXT: loop.1:
268; CHECK-NEXT:   WIDEN ir<%conv> = sext vp<[[PRED]]>
269; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0> ir<%conv>
270; CHECK-NEXT: Successor(s): loop.1.split
271
272; CHECK:      loop.1.split:
273; CHECK-NEXT: Successor(s): pred.load
274
275; CHECK:      <xVFxUF> pred.load: {
276; CHECK-NEXT:   pred.load.entry:
277; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
278; CHECK-NEXT:   Successor(s): pred.load.if, pred.load.continue
279; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
280
281; CHECK:        pred.load.if:
282; CHECK-NEXT:     REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> (S->V)
283; CHECK-NEXT:     REPLICATE ir<%lv.2> = load ir<%gep> (S->V)
284; CHECK-NEXT:   Successor(s): pred.load.continue
285
286; CHECK:        pred.load.continue:
287; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%rem>
288; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%lv.2>
289; CHECK-NEXT:   No successors
290; CHECK-NEXT: }
291
292; CHECK:      loop.2:
293; CHECK-NEXT:   WIDEN ir<%add.1> = add ir<%conv>, vp<[[PRED1]]>
294; CHECK-NEXT:   WIDEN ir<%conv.lv.2> = sext vp<[[PRED2]]>
295; CHECK-NEXT:   WIDEN ir<%add> = add ir<%add.1>, ir<%conv.lv.2>
296; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
297; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
298; CHECK-NEXT: No successors
299; CHECK-NEXT: }
300; CHECK-NEXT: No successors
301; CHECK-NEXT: }
302;
303entry:
304  br label %loop
305
306loop:
307  %0 = phi i32 [ 0, %entry ], [ %conv, %loop ]
308  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
309  %gep = getelementptr i8, i8* %ptr, i32 %iv
310  %rem = srem i32 %0, %x
311  %lv = load i8, i8* %gep
312  %conv = sext i8 %lv to i32
313  %lv.2 = load i8, i8* %gep
314  %add.1 = add i32 %conv, %rem
315  %conv.lv.2 = sext i8 %lv.2 to i32
316  %add = add i32 %add.1, %conv.lv.2
317  %iv.next = add nsw i32 %iv, 1
318  %ec = icmp eq i32 %iv.next, 20001
319  br i1 %ec, label %exit, label %loop
320
321exit:
322  ret void
323}
324
325; Test case that requires sinking a recipe in a replicate region after another replicate region.
326define void @sink_replicate_region_after_replicate_region(i32* %ptr, i32 %x, i8 %y) optsize {
327; CHECK-LABEL: sink_replicate_region_after_replicate_region
328; CHECK:      VPlan 'Initial VPlan for VF={2},UF>=1' {
329; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
330; CHECK-EMPTY:
331; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
332; CHECK-EMPTY:
333; CHECK-NEXT: <x1> vector loop: {
334; CHECK-NEXT: loop:
335; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
336; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
337; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next
338; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
339; CHECK-NEXT: Successor(s): loop.0
340; CHECK-EMPTY:
341; CHECK-NEXT: loop.0:
342; CHECK-NEXT: Successor(s): loop.1
343; CHECK-EMPTY:
344; CHECK-NEXT:  loop.1:
345; CHECK-NEXT:   WIDEN ir<%recur.next> = sext ir<%y>
346; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur> ir<%recur.next>
347; CHECK-NEXT: Successor(s): pred.srem
348; CHECK-EMPTY:
349; CHECK-NEXT: <xVFxUF> pred.srem: {
350; CHECK-NEXT:   pred.srem.entry:
351; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
352; CHECK-NEXT:   Successor(s): pred.srem.if, pred.srem.continue
353; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
354; CHECK-EMPTY:
355; CHECK-NEXT:   pred.srem.if:
356; CHECK-NEXT:     REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
357; CHECK-NEXT:   Successor(s): pred.srem.continue
358; CHECK-EMPTY:
359; CHECK-NEXT:   pred.srem.continue:
360; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
361; CHECK-NEXT:   No successors
362; CHECK-NEXT: }
363; CHECK-NEXT: Successor(s): loop.1.split
364; CHECK-EMPTY:
365; CHECK-NEXT: loop.1.split:
366; CHECK-NEXT: Successor(s): pred.store
367; CHECK-EMPTY:
368; CHECK-NEXT: <xVFxUF> pred.store: {
369; CHECK-NEXT:   pred.store.entry:
370; CHECK-NEXT:     BRANCH-ON-MASK vp<[[MASK]]>
371; CHECK-NEXT:   Successor(s): pred.store.if, pred.store.continue
372; CHECK-NEXT:   CondBit: vp<[[MASK]]> (loop)
373; CHECK-EMPTY:
374; CHECK-NEXT:   pred.store.if:
375; CHECK-NEXT:     REPLICATE ir<%rem.div> = sdiv ir<20>, vp<[[PRED]]>
376; CHECK-NEXT:     REPLICATE ir<%gep> = getelementptr ir<%ptr>, ir<%iv>
377; CHECK-NEXT:     REPLICATE store ir<%rem.div>, ir<%gep>
378; CHECK-NEXT:   Successor(s): pred.store.continue
379; CHECK-EMPTY:
380; CHECK-NEXT:   pred.store.continue:
381; CHECK-NEXT:     PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%rem.div>
382; CHECK-NEXT:   No successors
383; CHECK-NEXT: }
384; CHECK-NEXT: Successor(s): loop.2
385; CHECK-EMPTY:
386; CHECK-NEXT: loop.2:
387; CHECK-NEXT:   EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
388; CHECK-NEXT:   EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
389; CHECK-NEXT: No successors
390; CHECK-NEXT: }
391; CHECK-NEXT: No successors
392; CHECK-NEXT: }
393;
394entry:
395  br label %loop
396
397loop:                                             ; preds = %loop, %entry
398  %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ]
399  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
400  %rem = srem i32 %recur, %x
401  %rem.div = sdiv i32 20, %rem
402  %recur.next = sext i8 %y to i32
403  %gep = getelementptr i32, i32* %ptr, i32 %iv
404  store i32 %rem.div, i32* %gep
405  %iv.next = add nsw i32 %iv, 1
406  %C = icmp sgt i32 %iv.next, %recur.next
407  br i1 %C, label %exit, label %loop
408
409exit:                                             ; preds = %loop
410  ret void
411}
412