1; REQUIRES: asserts 2; RUN: opt < %s -loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s 3 4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" 5 6; Test cases for PR50009, which require sinking a replicate-region due to a 7; first-order recurrence. 8 9define void @sink_replicate_region_1(i32 %x, i8* %ptr) optsize { 10; CHECK-LABEL: sink_replicate_region_1 11; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { 12; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 13; CHECK-EMPTY: 14; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count 15; CHECK-EMPTY: 16; CHECK-NEXT: <x1> vector loop: { 17; CHECK-NEXT: loop: 18; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 19; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv> 20; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 21; CHECK-NEXT: vp<[[STEPS:%.]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1> 22; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]> 23; CHECK-NEXT: Successor(s): loop.0 24; CHECK-EMPTY: 25; CHECK-NEXT: loop.0: 26; CHECK-NEXT: Successor(s): pred.load 27; CHECK-EMPTY: 28; CHECK-NEXT: <xVFxUF> pred.load: { 29; CHECK-NEXT: pred.load.entry: 30; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 31; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue 32; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 33; CHECK-EMPTY: 34; CHECK-NEXT: pred.load.if: 35; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> 36; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V) 37; CHECK-NEXT: Successor(s): pred.load.continue 38; CHECK-EMPTY: 39; CHECK-NEXT: pred.load.continue: 40; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%lv> 41; CHECK-NEXT: No successors 42; CHECK-NEXT: } 43; CHECK-NEXT: Successor(s): loop.1 44; CHECK-EMPTY: 45; CHECK-NEXT: loop.1: 46; CHECK-NEXT: WIDEN ir<%conv> = sext vp<[[PRED1]]> 47; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0> ir<%conv> 48; CHECK-NEXT: Successor(s): pred.srem 49; CHECK-EMPTY: 50; CHECK-NEXT: <xVFxUF> pred.srem: { 51; CHECK-NEXT: pred.srem.entry: 52; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 53; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue 54; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 55; CHECK-EMPTY: 56; CHECK-NEXT: pred.srem.if: 57; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> (S->V) 58; CHECK-NEXT: Successor(s): pred.srem.continue 59; CHECK-EMPTY: 60; CHECK-NEXT: pred.srem.continue: 61; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%rem> 62; CHECK-NEXT: No successors 63; CHECK-NEXT: } 64; CHECK-NEXT: Successor(s): loop.1.split 65; CHECK-EMPTY: 66; CHECK-NEXT: loop.1.split: 67; CHECK-NEXT: WIDEN ir<%add> = add ir<%conv>, vp<[[PRED2]]> 68; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]> 69; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 70; CHECK-NEXT: No successors 71; CHECK-NEXT: } 72; CHECK-NEXT: No successors 73; CHECK-NEXT: } 74; 75entry: 76 br label %loop 77 78loop: 79 %0 = phi i32 [ 0, %entry ], [ %conv, %loop ] 80 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 81 %rem = srem i32 %0, %x 82 %gep = getelementptr i8, i8* %ptr, i32 %iv 83 %lv = load i8, i8* %gep 84 %conv = sext i8 %lv to i32 85 %add = add i32 %conv, %rem 86 %iv.next = add nsw i32 %iv, 1 87 %ec = icmp eq i32 %iv.next, 20001 88 br i1 %ec, label %exit, label %loop 89 90exit: 91 ret void 92} 93 94define void @sink_replicate_region_2(i32 %x, i8 %y, i32* %ptr) optsize { 95; CHECK-LABEL: sink_replicate_region_2 96; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { 97; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 98; CHECK-EMPTY: 99; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count 100; CHECK-EMPTY: 101; CHECK-NEXT: <x1> vector loop: { 102; CHECK-NEXT: loop: 103; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 104; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> 105; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 106; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1> 107; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]> 108; CHECK-NEXT: Successor(s): loop.0 109; CHECK-EMPTY: 110; CHECK-NEXT: loop.0: 111; CHECK-NEXT: WIDEN ir<%recur.next> = sext ir<%y> 112; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur> ir<%recur.next> 113; CHECK-NEXT: Successor(s): loop.0.split 114; CHECK-EMPTY: 115; CHECK-NEXT: loop.0.split: 116; CHECK-NEXT: Successor(s): pred.store 117; CHECK-EMPTY: 118; CHECK-NEXT: <xVFxUF> pred.store: { 119; CHECK-NEXT: pred.store.entry: 120; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 121; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue 122; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 123; CHECK-EMPTY: 124; CHECK-NEXT: pred.store.if: 125; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> 126; CHECK-NEXT: REPLICATE ir<%add> = add ir<%rem>, ir<%recur.next> 127; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> 128; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep> 129; CHECK-NEXT: Successor(s): pred.store.continue 130; CHECK-EMPTY: 131; CHECK-NEXT: pred.store.continue: 132; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem> 133; CHECK-NEXT: No successors 134; CHECK-NEXT: } 135; CHECK-NEXT: Successor(s): loop.1 136; CHECK-EMPTY: 137; CHECK-NEXT: loop.1: 138; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]> 139; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 140; CHECK-NEXT: No successors 141; CHECK-NEXT: } 142; CHECK-NEXT: No successors 143; CHECK-NEXT: } 144; 145entry: 146 br label %loop 147 148loop: 149 %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ] 150 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 151 %rem = srem i32 %recur, %x 152 %recur.next = sext i8 %y to i32 153 %add = add i32 %rem, %recur.next 154 %gep = getelementptr i32, i32* %ptr, i32 %iv 155 store i32 %add, i32* %gep 156 %iv.next = add nsw i32 %iv, 1 157 %ec = icmp eq i32 %iv.next, 20001 158 br i1 %ec, label %exit, label %loop 159 160exit: 161 ret void 162} 163 164define i32 @sink_replicate_region_3_reduction(i32 %x, i8 %y, i32* %ptr) optsize { 165; CHECK-LABEL: sink_replicate_region_3_reduction 166; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { 167; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 168; CHECK-EMPTY: 169; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count 170; CHECK-EMPTY: 171; CHECK-NEXT: <x1> vector loop: { 172; CHECK-NEXT: loop: 173; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 174; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> 175; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%and.red> = phi ir<1234>, ir<%and.red.next> 176; CHECK-NEXT: EMIT vp<[[WIDEN_CAN:%.+]]> = WIDEN-CANONICAL-INDUCTION vp<[[CAN_IV]]> 177; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule vp<[[WIDEN_CAN]]> vp<[[BTC]]> 178; CHECK-NEXT: Successor(s): loop.0 179; CHECK-EMPTY: 180; CHECK-NEXT: loop.0: 181; CHECK-NEXT: WIDEN ir<%recur.next> = sext ir<%y> 182; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur> ir<%recur.next> 183; CHECK-NEXT: Successor(s): pred.srem 184; CHECK-EMPTY: 185; CHECK-NEXT: <xVFxUF> pred.srem: { 186; CHECK-NEXT: pred.srem.entry: 187; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 188; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue 189; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 190; CHECK-EMPTY: 191; CHECK-NEXT: pred.srem.if: 192; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> (S->V) 193; CHECK-NEXT: Successor(s): pred.srem.continue 194; CHECK-EMPTY: 195; CHECK-NEXT: pred.srem.continue: 196; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem> 197; CHECK-NEXT: No successors 198; CHECK-NEXT: } 199; CHECK-NEXT: Successor(s): loop.0.split 200; CHECK-EMPTY: 201; CHECK-NEXT: loop.0.split: 202; CHECK-NEXT: WIDEN ir<%add> = add vp<[[PRED]]>, ir<%recur.next> 203; CHECK-NEXT: WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add> 204; CHECK-NEXT: EMIT vp<[[SEL:%.+]]> = select vp<[[MASK]]> ir<%and.red.next> ir<%and.red> 205; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]> 206; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 207; CHECK-NEXT: No successors 208; CHECK-NEXT: } 209; CHECK-NEXT: No successors 210; CHECK-NEXT: } 211; 212entry: 213 br label %loop 214 215loop: 216 %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ] 217 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 218 %and.red = phi i32 [ 1234, %entry ], [ %and.red.next, %loop ] 219 %rem = srem i32 %recur, %x 220 %recur.next = sext i8 %y to i32 221 %add = add i32 %rem, %recur.next 222 %and.red.next = and i32 %and.red, %add 223 %iv.next = add nsw i32 %iv, 1 224 %ec = icmp eq i32 %iv.next, 20001 225 br i1 %ec, label %exit, label %loop 226 227exit: 228 %res = phi i32 [ %and.red.next, %loop ] 229 ret i32 %res 230} 231 232; To sink the replicate region containing %rem, we need to split the block 233; containing %conv at the end, because %conv is the last recipe in the block. 234define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, i8* %ptr) optsize { 235; CHECK-LABEL: sink_replicate_region_4_requires_split_at_end_of_block 236; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { 237; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 238; CHECK-EMPTY: 239; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count 240; CHECK-EMPTY: 241; CHECK-NEXT: <x1> vector loop: { 242; CHECK-NEXT: loop: 243; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 244; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv> 245; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 246; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1> 247; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]> 248; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> 249; CHECK-NEXT: Successor(s): loop.0 250; CHECK-EMPTY: 251; CHECK-NEXT: loop.0: 252; CHECK-NEXT: Successor(s): pred.load 253; CHECK-EMPTY: 254; CHECK-NEXT: <xVFxUF> pred.load: { 255; CHECK-NEXT: pred.load.entry: 256; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 257; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue 258; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 259; CHECK-EMPTY: 260; CHECK-NEXT: pred.load.if: 261; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V) 262; CHECK-NEXT: Successor(s): pred.load.continue 263; CHECK-EMPTY: 264; CHECK-NEXT: pred.load.continue: 265; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv> 266; CHECK-NEXT: No successors 267; CHECK-NEXT: } 268; CHECK-NEXT: Successor(s): loop.1 269; CHECK-EMPTY: 270; CHECK-NEXT: loop.1: 271; CHECK-NEXT: WIDEN ir<%conv> = sext vp<[[PRED]]> 272; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0> ir<%conv> 273; CHECK-NEXT: Successor(s): loop.1.split 274 275; CHECK: loop.1.split: 276; CHECK-NEXT: Successor(s): pred.load 277 278; CHECK: <xVFxUF> pred.load: { 279; CHECK-NEXT: pred.load.entry: 280; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 281; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue 282; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 283 284; CHECK: pred.load.if: 285; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> (S->V) 286; CHECK-NEXT: REPLICATE ir<%lv.2> = load ir<%gep> (S->V) 287; CHECK-NEXT: Successor(s): pred.load.continue 288 289; CHECK: pred.load.continue: 290; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%rem> 291; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%lv.2> 292; CHECK-NEXT: No successors 293; CHECK-NEXT: } 294 295; CHECK: loop.2: 296; CHECK-NEXT: WIDEN ir<%add.1> = add ir<%conv>, vp<[[PRED1]]> 297; CHECK-NEXT: WIDEN ir<%conv.lv.2> = sext vp<[[PRED2]]> 298; CHECK-NEXT: WIDEN ir<%add> = add ir<%add.1>, ir<%conv.lv.2> 299; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]> 300; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 301; CHECK-NEXT: No successors 302; CHECK-NEXT: } 303; CHECK-NEXT: No successors 304; CHECK-NEXT: } 305; 306entry: 307 br label %loop 308 309loop: 310 %0 = phi i32 [ 0, %entry ], [ %conv, %loop ] 311 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 312 %gep = getelementptr i8, i8* %ptr, i32 %iv 313 %rem = srem i32 %0, %x 314 %lv = load i8, i8* %gep 315 %conv = sext i8 %lv to i32 316 %lv.2 = load i8, i8* %gep 317 %add.1 = add i32 %conv, %rem 318 %conv.lv.2 = sext i8 %lv.2 to i32 319 %add = add i32 %add.1, %conv.lv.2 320 %iv.next = add nsw i32 %iv, 1 321 %ec = icmp eq i32 %iv.next, 20001 322 br i1 %ec, label %exit, label %loop 323 324exit: 325 ret void 326} 327 328; Test case that requires sinking a recipe in a replicate region after another replicate region. 329define void @sink_replicate_region_after_replicate_region(i32* %ptr, i32 %x, i8 %y) optsize { 330; CHECK-LABEL: sink_replicate_region_after_replicate_region 331; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { 332; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 333; CHECK-EMPTY: 334; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count 335; CHECK-EMPTY: 336; CHECK-NEXT: <x1> vector loop: { 337; CHECK-NEXT: loop: 338; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 339; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> 340; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 341; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1> 342; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]> 343; CHECK-NEXT: Successor(s): loop.0 344; CHECK-EMPTY: 345; CHECK-NEXT: loop.0: 346; CHECK-NEXT: Successor(s): loop.1 347; CHECK-EMPTY: 348; CHECK-NEXT: loop.1: 349; CHECK-NEXT: WIDEN ir<%recur.next> = sext ir<%y> 350; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur> ir<%recur.next> 351; CHECK-NEXT: Successor(s): pred.srem 352; CHECK-EMPTY: 353; CHECK-NEXT: <xVFxUF> pred.srem: { 354; CHECK-NEXT: pred.srem.entry: 355; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 356; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue 357; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 358; CHECK-EMPTY: 359; CHECK-NEXT: pred.srem.if: 360; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> 361; CHECK-NEXT: Successor(s): pred.srem.continue 362; CHECK-EMPTY: 363; CHECK-NEXT: pred.srem.continue: 364; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem> 365; CHECK-NEXT: No successors 366; CHECK-NEXT: } 367; CHECK-NEXT: Successor(s): loop.1.split 368; CHECK-EMPTY: 369; CHECK-NEXT: loop.1.split: 370; CHECK-NEXT: Successor(s): pred.store 371; CHECK-EMPTY: 372; CHECK-NEXT: <xVFxUF> pred.store: { 373; CHECK-NEXT: pred.store.entry: 374; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> 375; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue 376; CHECK-NEXT: CondBit: vp<[[MASK]]> (loop) 377; CHECK-EMPTY: 378; CHECK-NEXT: pred.store.if: 379; CHECK-NEXT: REPLICATE ir<%rem.div> = sdiv ir<20>, vp<[[PRED]]> 380; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> 381; CHECK-NEXT: REPLICATE store ir<%rem.div>, ir<%gep> 382; CHECK-NEXT: Successor(s): pred.store.continue 383; CHECK-EMPTY: 384; CHECK-NEXT: pred.store.continue: 385; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED2:%.+]]> = ir<%rem.div> 386; CHECK-NEXT: No successors 387; CHECK-NEXT: } 388; CHECK-NEXT: Successor(s): loop.2 389; CHECK-EMPTY: 390; CHECK-NEXT: loop.2: 391; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]> 392; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 393; CHECK-NEXT: No successors 394; CHECK-NEXT: } 395; CHECK-NEXT: No successors 396; CHECK-NEXT: } 397; 398entry: 399 br label %loop 400 401loop: ; preds = %loop, %entry 402 %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ] 403 %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] 404 %rem = srem i32 %recur, %x 405 %rem.div = sdiv i32 20, %rem 406 %recur.next = sext i8 %y to i32 407 %gep = getelementptr i32, i32* %ptr, i32 %iv 408 store i32 %rem.div, i32* %gep 409 %iv.next = add nsw i32 %iv, 1 410 %C = icmp sgt i32 %iv.next, %recur.next 411 br i1 %C, label %exit, label %loop 412 413exit: ; preds = %loop 414 ret void 415} 416