1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN:opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s 3 4; For %for.1, we are fine initially, because the previous value %for.1.next dominates the 5; user of %for.1. But for %for.2, we have to sink the user (%for.1.next) past the previous 6; value %for.2.next. This however breaks the condition we have for %for.1. We cannot fix 7; both first order recurrences and cannot vectorize the loop. 8define i32 @c(i32 %N) { 9; CHECK-LABEL: @c( 10; CHECK-NEXT: entry: 11; CHECK-NEXT: br label [[FOR_BODY:%.*]] 12; CHECK: for.body: 13; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 10, [[ENTRY:%.*]] ] 14; CHECK-NEXT: [[FOR_1:%.*]] = phi i32 [ [[FOR_1_NEXT:%.*]], [[FOR_BODY]] ], [ 20, [[ENTRY]] ] 15; CHECK-NEXT: [[FOR_2:%.*]] = phi i32 [ [[FOR_2_NEXT:%.*]], [[FOR_BODY]] ], [ 11, [[ENTRY]] ] 16; CHECK-NEXT: [[FOR_1_NEXT]] = add nsw i32 [[FOR_2]], 1 17; CHECK-NEXT: [[FOR_2_NEXT]] = shl i32 [[FOR_1]], 24 18; CHECK-NEXT: [[INC]] = add nsw i32 [[IV]], 1 19; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N:%.*]] 20; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND1_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY]] 21; CHECK: for.cond1.for.end_crit_edge: 22; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[FOR_1_NEXT]], [[FOR_BODY]] ] 23; CHECK-NEXT: [[SEXT_LCSSA:%.*]] = phi i32 [ [[FOR_2_NEXT]], [[FOR_BODY]] ] 24; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_LCSSA]], [[SEXT_LCSSA]] 25; CHECK-NEXT: ret i32 [[RES]] 26; 27entry: 28 br label %for.body 29 30for.body: ; preds = %for.body.preheader, %for.body 31 %iv = phi i32 [ %inc, %for.body ], [ 10, %entry ] 32 %for.1 = phi i32 [ %for.1.next, %for.body ], [ 20, %entry ] 33 %for.2 = phi i32 [ %for.2.next, %for.body ], [ 11, %entry ] 34 %for.1.next = add nsw i32 %for.2, 1 35 %for.2.next = shl i32 %for.1, 24 36 %inc = add nsw i32 %iv, 1 37 %exitcond = icmp eq i32 %inc, %N 38 br i1 %exitcond, label %for.cond1.for.end_crit_edge, label %for.body 39 40for.cond1.for.end_crit_edge: ; preds = %for.body 41 %add.lcssa = phi i32 [ %for.1.next, %for.body ] 42 %sext.lcssa = phi i32 [ %for.2.next, %for.body ] 43 %res = add i32 %add.lcssa, %sext.lcssa 44 ret i32 %res 45} 46 47 48; The 'previous' instruction of %for.2 is in a separate block. 49; PR54195. 50define void @multiple_recurrences_with_previous_in_different_block(i32 %a, i8 %b, i64* %ptr) { 51; CHECK-LABEL: @multiple_recurrences_with_previous_in_different_block( 52; CHECK-NEXT: entry: 53; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] 54; CHECK: loop.header: 55; CHECK-NEXT: [[FOR_1:%.*]] = phi i8 [ 10, [[ENTRY:%.*]] ], [ [[FOR_1_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] 56; CHECK-NEXT: [[FOR_2:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[FOR_2_NEXT:%.*]], [[LOOP_LATCH]] ] 57; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ] 58; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[FOR_1]] to i64 59; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[CONV]], [[FOR_2]] 60; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1 61; CHECK-NEXT: [[FOR_1_NEXT]] = xor i8 [[B:%.*]], 6 62; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1000 63; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP_LATCH]] 64; CHECK: loop.latch: 65; CHECK-NEXT: [[PTR_GEP:%.*]] = getelementptr inbounds i64, i64* [[PTR:%.*]], i64 [[IV]] 66; CHECK-NEXT: store i64 [[SUB]], i64* [[PTR_GEP]], align 4 67; CHECK-NEXT: [[FOR_2_NEXT]] = zext i32 [[A:%.*]] to i64 68; CHECK-NEXT: br label [[LOOP_HEADER]] 69; CHECK: exit: 70; CHECK-NEXT: ret void 71; 72entry: 73 br label %loop.header 74 75loop.header: 76 %for.1 = phi i8 [ 10, %entry ], [ %for.1.next, %loop.latch ] 77 %for.2 = phi i64 [0, %entry ], [ %for.2.next, %loop.latch ] 78 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 79 %conv = sext i8 %for.1 to i64 80 %sub = sub nsw i64 %conv, %for.2 81 %iv.next = add nuw i64 %iv, 1 82 %for.1.next = xor i8 %b, 6 83 %exitcond = icmp eq i64 %iv, 1000 84 br i1 %exitcond, label %exit, label %loop.latch 85 86loop.latch: 87 %ptr.gep = getelementptr inbounds i64, i64* %ptr, i64 %iv 88 store i64 %sub, i64* %ptr.gep 89 %for.2.next = zext i32 %a to i64 90 br label %loop.header 91 92exit: 93 ret void 94} 95 96define void @test_pr54223_sink_after_insertion_order(float* noalias %a, float* noalias %b, float* noalias %dst) { 97; CHECK-LABEL: @test_pr54223_sink_after_insertion_order( 98; CHECK-NEXT: entry: 99; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 100; CHECK: vector.ph: 101; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 102; CHECK: vector.body: 103; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 104; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x float> [ <float poison, float poison, float poison, float 0.000000e+00>, [[VECTOR_PH]] ], [ [[BROADCAST_SPLAT:%.*]], [[VECTOR_BODY]] ] 105; CHECK-NEXT: [[VECTOR_RECUR1:%.*]] = phi <4 x float> [ <float poison, float poison, float poison, float 0.000000e+00>, [[VECTOR_PH]] ], [ [[BROADCAST_SPLAT3:%.*]], [[VECTOR_BODY]] ] 106; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 107; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, float* [[DST:%.*]], i64 [[TMP0]] 108; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[A:%.*]], align 4 109; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0 110; CHECK-NEXT: [[BROADCAST_SPLAT]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer 111; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[VECTOR_RECUR]], <4 x float> [[BROADCAST_SPLAT]], <4 x i32> <i32 3, i32 4, i32 5, i32 6> 112; CHECK-NEXT: [[TMP4:%.*]] = load float, float* [[B:%.*]], align 4 113; CHECK-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x float> poison, float [[TMP4]], i32 0 114; CHECK-NEXT: [[BROADCAST_SPLAT3]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT2]], <4 x float> poison, <4 x i32> zeroinitializer 115; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[VECTOR_RECUR1]], <4 x float> [[BROADCAST_SPLAT3]], <4 x i32> <i32 3, i32 4, i32 5, i32 6> 116; CHECK-NEXT: [[TMP6:%.*]] = fneg <4 x float> [[TMP5]] 117; CHECK-NEXT: [[TMP7:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP3]], <4 x float> [[TMP6]], <4 x float> zeroinitializer) 118; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, float* [[TMP1]], i32 0 119; CHECK-NEXT: [[TMP9:%.*]] = bitcast float* [[TMP8]] to <4 x float>* 120; CHECK-NEXT: store <4 x float> [[TMP7]], <4 x float>* [[TMP9]], align 4 121; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 122; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10000 123; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 124; CHECK: middle.block: 125; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 10000, 10000 126; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x float> [[BROADCAST_SPLAT]], i32 3 127; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x float> [[BROADCAST_SPLAT]], i32 2 128; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT4:%.*]] = extractelement <4 x float> [[BROADCAST_SPLAT3]], i32 3 129; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI5:%.*]] = extractelement <4 x float> [[BROADCAST_SPLAT3]], i32 2 130; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 131; CHECK: scalar.ph: 132; CHECK-NEXT: [[SCALAR_RECUR_INIT6:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT4]], [[MIDDLE_BLOCK]] ] 133; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] 134; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 10000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] 135; CHECK-NEXT: br label [[LOOP:%.*]] 136; CHECK: loop: 137; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 138; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi float [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[FOR_1_NEXT:%.*]], [[LOOP]] ] 139; CHECK-NEXT: [[SCALAR_RECUR7:%.*]] = phi float [ [[SCALAR_RECUR_INIT6]], [[SCALAR_PH]] ], [ [[FOR_2_NEXT:%.*]], [[LOOP]] ] 140; CHECK-NEXT: [[NEG:%.*]] = fneg float [[SCALAR_RECUR7]] 141; CHECK-NEXT: [[MULADD:%.*]] = call float @llvm.fmuladd.f32(float [[SCALAR_RECUR]], float [[NEG]], float 0.000000e+00) 142; CHECK-NEXT: [[DST_GEP:%.*]] = getelementptr inbounds float, float* [[DST]], i64 [[IV]] 143; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 144; CHECK-NEXT: [[FOR_1_NEXT]] = load float, float* [[A]], align 4 145; CHECK-NEXT: [[FOR_2_NEXT]] = load float, float* [[B]], align 4 146; CHECK-NEXT: store float [[MULADD]], float* [[DST_GEP]], align 4 147; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 10000 148; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]] 149; CHECK: exit: 150; CHECK-NEXT: ret void 151; 152entry: 153 br label %loop 154 155loop: 156 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 157 %for.1 = phi float [ 0.0, %entry ], [ %for.1.next, %loop ] 158 %for.2 = phi float [ 0.0, %entry ], [ %for.2.next, %loop ] 159 %neg = fneg float %for.2 160 %muladd = call float @llvm.fmuladd.f32(float %for.1, float %neg, float 0.000000e+00) 161 %dst.gep = getelementptr inbounds float, float* %dst, i64 %iv 162 %iv.next = add nuw nsw i64 %iv, 1 163 %for.1.next = load float, float* %a, align 4 164 %for.2.next = load float, float* %b, align 4 165 store float %muladd, float* %dst.gep 166 %exitcond.not = icmp eq i64 %iv.next, 10000 167 br i1 %exitcond.not, label %exit, label %loop 168 169exit: 170 ret void 171} 172 173declare float @llvm.fmuladd.f32(float, float, float) #1 174 175define void @test_pr54227(i32* noalias %a, i32* noalias %b) { 176; CHECK-LABEL: @test_pr54227( 177; CHECK-NEXT: entry: 178; CHECK-NEXT: br label [[LOOP:%.*]] 179; CHECK: loop: 180; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 181; CHECK-NEXT: [[AND17:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[AND1:%.*]], [[LOOP]] ] 182; CHECK-NEXT: [[F_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[MUL:%.*]], [[LOOP]] ] 183; CHECK-NEXT: [[E_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[LOOP]] ] 184; CHECK-NEXT: [[AND:%.*]] = and i32 [[AND17]], 255 185; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[E_0]] 186; CHECK-NEXT: [[AND1]] = and i32 [[E_0]], [[F_0]] 187; CHECK-NEXT: [[MUL]] = shl nsw i32 [[OR]], 1 188; CHECK-NEXT: [[ADD]] = or i32 [[AND1]], 1 189; CHECK-NEXT: [[A_GEP:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[IV]] 190; CHECK-NEXT: store i32 [[ADD]], i32* [[A_GEP]], align 4 191; CHECK-NEXT: [[B_GEP:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[IV]] 192; CHECK-NEXT: store i32 [[MUL]], i32* [[B_GEP]], align 4 193; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1 194; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1000 195; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]] 196; CHECK: exit: 197; CHECK-NEXT: ret void 198; 199entry: 200 br label %loop 201 202loop: 203 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 204 %and17 = phi i32 [ 0, %entry ], [ %and1, %loop ] 205 %f.0 = phi i32 [ 0, %entry ], [ %mul, %loop ] 206 %e.0 = phi i32 [ 0, %entry ], [ %add, %loop ] 207 %and = and i32 %and17, 255 208 %or = or i32 %and, %e.0 209 %and1 = and i32 %e.0, %f.0 210 %mul = shl nsw i32 %or, 1 211 %add = or i32 %and1, 1 212 %a.gep = getelementptr inbounds i32, i32* %a, i64 %iv 213 store i32 %add, i32* %a.gep, align 4 214 %b.gep = getelementptr inbounds i32, i32* %a, i64 %iv 215 store i32 %mul, i32* %b.gep, align 4 216 %iv.next = add nuw i64 %iv, 1 217 %exitcond = icmp eq i64 %iv, 1000 218 br i1 %exitcond, label %exit, label %loop 219 220exit: 221 ret void 222} 223 224define void @test_pr54233_for_depend_on_each_other(i32* noalias %a, i32* noalias %b) { 225; CHECK-LABEL: @test_pr54233_for_depend_on_each_other( 226; CHECK-NEXT: entry: 227; CHECK-NEXT: br label [[LOOP:%.*]] 228; CHECK: loop: 229; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 230; CHECK-NEXT: [[FOR_1:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[FOR_1_NEXT:%.*]], [[LOOP]] ] 231; CHECK-NEXT: [[FOR_2:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[FOR_2_NEXT:%.*]], [[LOOP]] ] 232; CHECK-NEXT: [[OR:%.*]] = or i32 [[FOR_2]], 10 233; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[FOR_2]], [[FOR_1]] 234; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 255 235; CHECK-NEXT: [[AND:%.*]] = and i32 [[XOR]], [[OR]] 236; CHECK-NEXT: [[FOR_1_NEXT]] = xor i32 12, [[FOR_2]] 237; CHECK-NEXT: [[FOR_2_NEXT]] = load i32, i32* [[B:%.*]], align 4 238; CHECK-NEXT: [[A_GEP:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[IV]] 239; CHECK-NEXT: store i32 [[AND]], i32* [[A_GEP]], align 4 240; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1 241; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1000 242; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]] 243; CHECK: exit: 244; CHECK-NEXT: ret void 245; 246entry: 247 br label %loop 248 249loop: 250 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 251 %for.1 = phi i32 [ 0, %entry ], [ %for.1.next, %loop ] 252 %for.2 = phi i32 [ 0, %entry ], [ %for.2.next, %loop ] 253 %or = or i32 %for.2, 10 254 %shl = shl i32 %for.2, %for.1 255 %xor = xor i32 %shl, 255 256 %and = and i32 %xor, %or 257 %for.1.next = xor i32 12, %for.2 258 %for.2.next = load i32, i32* %b 259 %a.gep = getelementptr inbounds i32, i32* %a, i64 %iv 260 store i32 %and, i32* %a.gep, align 4 261 %iv.next = add nuw i64 %iv, 1 262 %exitcond = icmp eq i64 %iv, 1000 263 br i1 %exitcond, label %exit, label %loop 264 265exit: 266 ret void 267} 268 269define void @pr54218(i8* %dst, i32* noalias %d) { 270; CHECK-LABEL: @pr54218( 271; CHECK-NEXT: entry: 272; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] 273; CHECK: loop.header: 274; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] 275; CHECK-NEXT: [[FOR_1:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[FOR_1_NEXT:%.*]], [[LOOP_LATCH]] ] 276; CHECK-NEXT: [[P:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[P_NEXT:%.*]], [[LOOP_LATCH]] ] 277; CHECK-NEXT: [[C_1:%.*]] = icmp eq i32 [[FOR_1]], 0 278; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C_1]], i8 [[P]], i8 0 279; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1000 280; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP_LATCH]] 281; CHECK: loop.latch: 282; CHECK-NEXT: [[FOR_1_NEXT]] = load i32, i32* [[D:%.*]], align 4 283; CHECK-NEXT: [[P_NEXT]] = add i8 [[SEL]], -1 284; CHECK-NEXT: [[DST_GEP:%.*]] = getelementptr inbounds i8, i8* [[DST:%.*]], i64 [[IV]] 285; CHECK-NEXT: store i8 [[SEL]], i8* [[DST_GEP]], align 1 286; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1 287; CHECK-NEXT: br label [[LOOP_HEADER]] 288; CHECK: exit: 289; CHECK-NEXT: ret void 290; 291entry: 292 br label %loop.header 293 294loop.header: 295 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] 296 %for.1 = phi i32 [ 0, %entry ], [ %for.1.next, %loop.latch ] 297 %p = phi i8 [ 0, %entry ], [ %p.next, %loop.latch ] 298 %c.1 = icmp eq i32 %for.1, 0 299 %sel = select i1 %c.1, i8 %p, i8 0 300 %exitcond = icmp eq i64 %iv, 1000 301 br i1 %exitcond, label %exit, label %loop.latch 302 303loop.latch: 304 %for.1.next = load i32, i32* %d, align 4 305 %p.next = add i8 %sel, -1 306 %dst.gep = getelementptr inbounds i8, i8* %dst, i64 %iv 307 store i8 %sel, i8* %dst.gep 308 %iv.next = add nuw i64 %iv, 1 309 br label %loop.header 310 311exit: 312 ret void 313} 314 315define void @pr54254_fors_depend_on_each_other(i32* %dst) { 316; CHECK-LABEL: @pr54254_fors_depend_on_each_other( 317; CHECK-NEXT: entry: 318; CHECK-NEXT: br label [[LOOP:%.*]] 319; CHECK: loop: 320; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 321; CHECK-NEXT: [[D_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[XOR:%.*]], [[LOOP]] ] 322; CHECK-NEXT: [[C_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[REM_NEXT:%.*]], [[LOOP]] ] 323; CHECK-NEXT: [[F_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[XOR1:%.*]], [[LOOP]] ] 324; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[D_0]], -1 325; CHECK-NEXT: [[REM:%.*]] = srem i32 [[F_0]], [[NEG]] 326; CHECK-NEXT: [[XOR]] = xor i32 [[C_0]], 1 327; CHECK-NEXT: [[XOR1]] = xor i32 [[REM]], 1 328; CHECK-NEXT: [[DST_GEP:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 [[IV]] 329; CHECK-NEXT: [[REM_NEXT]] = add i32 [[REM]], 10 330; CHECK-NEXT: store i32 [[REM]], i32* [[DST_GEP]], align 4 331; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1 332; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1000 333; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT:%.*]], label [[LOOP]] 334; CHECK: exit: 335; CHECK-NEXT: ret void 336; 337entry: 338 br label %loop 339 340loop: 341 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 342 %d.0 = phi i32 [ 0, %entry ], [ %xor, %loop ] 343 %c.0 = phi i32 [ 0, %entry ], [ %rem.next, %loop ] 344 %f.0 = phi i32 [ 0, %entry ], [ %xor1, %loop ] 345 %neg = xor i32 %d.0, -1 346 %rem = srem i32 %f.0, %neg 347 %xor = xor i32 %c.0, 1 348 %xor1 = xor i32 %rem, 1 349 %dst.gep = getelementptr inbounds i32, i32* %dst, i64 %iv 350 %rem.next = add i32 %rem, 10 351 store i32 %rem, i32* %dst.gep 352 %iv.next = add nuw i64 %iv, 1 353 %exitcond = icmp eq i64 %iv, 1000 354 br i1 %exitcond, label %exit, label %loop 355 356exit: 357 ret void 358} 359