1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -loop-vectorize -simplifycfg -mcpu=knl -S | FileCheck %s -check-prefix=AVX512 3; RUN: opt < %s -loop-vectorize -simplifycfg -mcpu=knl -force-vector-width=2 -force-target-max-vector-interleave=1 -S | FileCheck %s -check-prefix=FVW2 4 5; With a force-vector-width, it is sometimes more profitable to generate 6; scalarized and predicated stores instead of masked scatter. Disable 7; interleaving to simplify CHECKs in that scenario. 8 9target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 10target triple = "x86_64-pc_linux" 11 12; The source code: 13; 14;void foo1(float * __restrict__ in, float * __restrict__ out, int * __restrict__ trigger, int * __restrict__ index) { 15; 16; for (int i=0; i < SIZE; ++i) { 17; if (trigger[i] > 0) { 18; out[i] = in[index[i]] + (float) 0.5; 19; } 20; } 21;} 22 23; Function Attrs: nounwind uwtable 24define void @foo1(float* noalias %in, float* noalias %out, i32* noalias %trigger, i32* noalias %index) { 25; AVX512-LABEL: @foo1( 26; AVX512-NEXT: iter.check: 27; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 28; AVX512: vector.body: 29; AVX512-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ITER_CHECK:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 30; AVX512-NEXT: [[TMP0:%.*]] = add i64 [[INDEX1]], 0 31; AVX512-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 32; AVX512-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0 33; AVX512-NEXT: [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <16 x i32>* 34; AVX512-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i32>, <16 x i32>* [[TMP3]], align 4 35; AVX512-NEXT: [[TMP4:%.*]] = icmp sgt <16 x i32> [[WIDE_LOAD]], zeroinitializer 36; AVX512-NEXT: [[TMP5:%.*]] = getelementptr i32, i32* [[INDEX:%.*]], i64 [[TMP0]] 37; AVX512-NEXT: [[TMP6:%.*]] = getelementptr i32, i32* [[TMP5]], i32 0 38; AVX512-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <16 x i32>* 39; AVX512-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* [[TMP7]], i32 4, <16 x i1> [[TMP4]], <16 x i32> poison) 40; AVX512-NEXT: [[TMP8:%.*]] = sext <16 x i32> [[WIDE_MASKED_LOAD]] to <16 x i64> 41; AVX512-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, float* [[IN:%.*]], <16 x i64> [[TMP8]] 42; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[TMP9]], i32 4, <16 x i1> [[TMP4]], <16 x float> undef) 43; AVX512-NEXT: [[TMP10:%.*]] = fadd <16 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> 44; AVX512-NEXT: [[TMP11:%.*]] = getelementptr float, float* [[OUT:%.*]], i64 [[TMP0]] 45; AVX512-NEXT: [[TMP12:%.*]] = getelementptr float, float* [[TMP11]], i32 0 46; AVX512-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP12]] to <16 x float>* 47; AVX512-NEXT: call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> [[TMP10]], <16 x float>* [[TMP13]], i32 4, <16 x i1> [[TMP4]]) 48; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 16 49; AVX512-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 50; AVX512-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 51; AVX512: middle.block: 52; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, 4096 53; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 54; AVX512: for.body: 55; AVX512-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 56; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 57; AVX512-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 58; AVX512-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP15]], 0 59; AVX512-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 60; AVX512: if.then: 61; AVX512-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[INDEX]], i64 [[INDVARS_IV]] 62; AVX512-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 63; AVX512-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP16]] to i64 64; AVX512-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[IN]], i64 [[IDXPROM4]] 65; AVX512-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX5]], align 4 66; AVX512-NEXT: [[ADD:%.*]] = fadd float [[TMP17]], 5.000000e-01 67; AVX512-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDVARS_IV]] 68; AVX512-NEXT: store float [[ADD]], float* [[ARRAYIDX7]], align 4 69; AVX512-NEXT: br label [[FOR_INC]] 70; AVX512: for.inc: 71; AVX512-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 72; AVX512-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096 73; AVX512-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] 74; AVX512: for.end: 75; AVX512-NEXT: ret void 76; 77; FVW2-LABEL: @foo1( 78; FVW2-NEXT: entry: 79; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 80; FVW2: vector.body: 81; FVW2-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 82; FVW2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX1]], 0 83; FVW2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 84; FVW2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0 85; FVW2-NEXT: [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <2 x i32>* 86; FVW2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP3]], align 4 87; FVW2-NEXT: [[TMP4:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD]], zeroinitializer 88; FVW2-NEXT: [[TMP5:%.*]] = getelementptr i32, i32* [[INDEX:%.*]], i64 [[TMP0]] 89; FVW2-NEXT: [[TMP6:%.*]] = getelementptr i32, i32* [[TMP5]], i32 0 90; FVW2-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <2 x i32>* 91; FVW2-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* [[TMP7]], i32 4, <2 x i1> [[TMP4]], <2 x i32> poison) 92; FVW2-NEXT: [[TMP8:%.*]] = sext <2 x i32> [[WIDE_MASKED_LOAD]] to <2 x i64> 93; FVW2-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, float* [[IN:%.*]], <2 x i64> [[TMP8]] 94; FVW2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> [[TMP9]], i32 4, <2 x i1> [[TMP4]], <2 x float> undef) 95; FVW2-NEXT: [[TMP10:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01> 96; FVW2-NEXT: [[TMP11:%.*]] = getelementptr float, float* [[OUT:%.*]], i64 [[TMP0]] 97; FVW2-NEXT: [[TMP12:%.*]] = getelementptr float, float* [[TMP11]], i32 0 98; FVW2-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP12]] to <2 x float>* 99; FVW2-NEXT: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> [[TMP10]], <2 x float>* [[TMP13]], i32 4, <2 x i1> [[TMP4]]) 100; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 2 101; FVW2-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 102; FVW2-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 103; FVW2: middle.block: 104; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, 4096 105; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 106; FVW2: for.body: 107; FVW2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 108; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 109; FVW2-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 110; FVW2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP15]], 0 111; FVW2-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 112; FVW2: if.then: 113; FVW2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[INDEX]], i64 [[INDVARS_IV]] 114; FVW2-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 115; FVW2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP16]] to i64 116; FVW2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[IN]], i64 [[IDXPROM4]] 117; FVW2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX5]], align 4 118; FVW2-NEXT: [[ADD:%.*]] = fadd float [[TMP17]], 5.000000e-01 119; FVW2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDVARS_IV]] 120; FVW2-NEXT: store float [[ADD]], float* [[ARRAYIDX7]], align 4 121; FVW2-NEXT: br label [[FOR_INC]] 122; FVW2: for.inc: 123; FVW2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 124; FVW2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096 125; FVW2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] 126; FVW2: for.end: 127; FVW2-NEXT: ret void 128; 129entry: 130 br label %for.body 131 132for.body: 133 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] 134 %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv 135 %0 = load i32, i32* %arrayidx, align 4 136 %cmp1 = icmp sgt i32 %0, 0 137 br i1 %cmp1, label %if.then, label %for.inc 138 139if.then: 140 %arrayidx3 = getelementptr inbounds i32, i32* %index, i64 %indvars.iv 141 %1 = load i32, i32* %arrayidx3, align 4 142 %idxprom4 = sext i32 %1 to i64 143 %arrayidx5 = getelementptr inbounds float, float* %in, i64 %idxprom4 144 %2 = load float, float* %arrayidx5, align 4 145 %add = fadd float %2, 5.000000e-01 146 %arrayidx7 = getelementptr inbounds float, float* %out, i64 %indvars.iv 147 store float %add, float* %arrayidx7, align 4 148 br label %for.inc 149 150for.inc: 151 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 152 %exitcond.not = icmp eq i64 %indvars.iv.next, 4096 153 br i1 %exitcond.not, label %for.end, label %for.body 154 155for.end: 156 ret void 157} 158 159; The source code 160;void foo2 (In * __restrict__ in, float * __restrict__ out, int * __restrict__ trigger) { 161; 162; for (int i=0; i<SIZE; i += 16) { 163; if (trigger[i] > 0) { 164; out[i] = in[i].b + (float) 0.5; 165; } 166; } 167;} 168 169%struct.In = type { float, float } 170 171define void @foo2(%struct.In* noalias %in, float* noalias %out, i32* noalias %trigger, i32* noalias %index) #0 { 172; AVX512-LABEL: @foo2( 173; AVX512-NEXT: entry: 174; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 175; AVX512: vector.body: 176; AVX512-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 177; AVX512-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 16, i64 32, i64 48, i64 64, i64 80, i64 96, i64 112, i64 128, i64 144, i64 160, i64 176, i64 192, i64 208, i64 224, i64 240>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 178; AVX512-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 179; AVX512-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 180; AVX512-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 181; AVX512-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 32 182; AVX512-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 48 183; AVX512-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 64 184; AVX512-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 80 185; AVX512-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 96 186; AVX512-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 112 187; AVX512-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 128 188; AVX512-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 144 189; AVX512-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 160 190; AVX512-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 176 191; AVX512-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 192 192; AVX512-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 208 193; AVX512-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 224 194; AVX512-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 240 195; AVX512-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], <16 x i64> [[VEC_IND]] 196; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP16]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i32> undef) 197; AVX512-NEXT: [[TMP17:%.*]] = icmp sgt <16 x i32> [[WIDE_MASKED_GATHER]], zeroinitializer 198; AVX512-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], %struct.In* [[IN:%.*]], <16 x i64> [[VEC_IND]], i32 1 199; AVX512-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[TMP18]], i32 4, <16 x i1> [[TMP17]], <16 x float> undef) 200; AVX512-NEXT: [[TMP19:%.*]] = fadd <16 x float> [[WIDE_MASKED_GATHER2]], <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> 201; AVX512-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, float* [[OUT:%.*]], <16 x i64> [[VEC_IND]] 202; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> [[TMP19]], <16 x float*> [[TMP20]], i32 4, <16 x i1> [[TMP17]]) 203; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 16 204; AVX512-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], <i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256> 205; AVX512-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 206; AVX512-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 207; AVX512: middle.block: 208; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 209; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 210; AVX512: for.body: 211; AVX512-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 212; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 213; AVX512-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 214; AVX512-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP22]], 0 215; AVX512-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 216; AVX512: if.then: 217; AVX512-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], %struct.In* [[IN]], i64 [[INDVARS_IV]], i32 1 218; AVX512-NEXT: [[TMP23:%.*]] = load float, float* [[B]], align 4 219; AVX512-NEXT: [[ADD:%.*]] = fadd float [[TMP23]], 5.000000e-01 220; AVX512-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDVARS_IV]] 221; AVX512-NEXT: store float [[ADD]], float* [[ARRAYIDX5]], align 4 222; AVX512-NEXT: br label [[FOR_INC]] 223; AVX512: for.inc: 224; AVX512-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 225; AVX512-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 226; AVX512-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP5:![0-9]+]] 227; AVX512: for.end: 228; AVX512-NEXT: ret void 229; 230; FVW2-LABEL: @foo2( 231; FVW2-NEXT: entry: 232; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 233; FVW2: vector.body: 234; FVW2-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ] 235; FVW2-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 16>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE3]] ] 236; FVW2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 237; FVW2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 238; FVW2-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 239; FVW2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 240; FVW2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[TMP1]] 241; FVW2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 242; FVW2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 243; FVW2-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i32 0 244; FVW2-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP5]], i32 1 245; FVW2-NEXT: [[TMP8:%.*]] = icmp sgt <2 x i32> [[TMP7]], zeroinitializer 246; FVW2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], %struct.In* [[IN:%.*]], <2 x i64> [[VEC_IND]], i32 1 247; FVW2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> [[TMP9]], i32 4, <2 x i1> [[TMP8]], <2 x float> undef) 248; FVW2-NEXT: [[TMP10:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01> 249; FVW2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0 250; FVW2-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 251; FVW2: pred.store.if: 252; FVW2-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, float* [[OUT:%.*]], i64 [[TMP0]] 253; FVW2-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[TMP10]], i32 0 254; FVW2-NEXT: store float [[TMP13]], float* [[TMP12]], align 4 255; FVW2-NEXT: br label [[PRED_STORE_CONTINUE]] 256; FVW2: pred.store.continue: 257; FVW2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1 258; FVW2-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]] 259; FVW2: pred.store.if2: 260; FVW2-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[TMP1]] 261; FVW2-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP10]], i32 1 262; FVW2-NEXT: store float [[TMP16]], float* [[TMP15]], align 4 263; FVW2-NEXT: br label [[PRED_STORE_CONTINUE3]] 264; FVW2: pred.store.continue3: 265; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 2 266; FVW2-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 32, i64 32> 267; FVW2-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 268; FVW2-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 269; FVW2: middle.block: 270; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 271; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 272; FVW2: for.body: 273; FVW2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 274; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 275; FVW2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 276; FVW2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP18]], 0 277; FVW2-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 278; FVW2: if.then: 279; FVW2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], %struct.In* [[IN]], i64 [[INDVARS_IV]], i32 1 280; FVW2-NEXT: [[TMP19:%.*]] = load float, float* [[B]], align 4 281; FVW2-NEXT: [[ADD:%.*]] = fadd float [[TMP19]], 5.000000e-01 282; FVW2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDVARS_IV]] 283; FVW2-NEXT: store float [[ADD]], float* [[ARRAYIDX5]], align 4 284; FVW2-NEXT: br label [[FOR_INC]] 285; FVW2: for.inc: 286; FVW2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 287; FVW2-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 288; FVW2-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP5:![0-9]+]] 289; FVW2: for.end: 290; FVW2-NEXT: ret void 291; 292entry: 293 br label %for.body 294 295for.body: 296 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] 297 %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv 298 %0 = load i32, i32* %arrayidx, align 4 299 %cmp1 = icmp sgt i32 %0, 0 300 br i1 %cmp1, label %if.then, label %for.inc 301 302if.then: 303 %b = getelementptr inbounds %struct.In, %struct.In* %in, i64 %indvars.iv, i32 1 304 %1 = load float, float* %b, align 4 305 %add = fadd float %1, 5.000000e-01 306 %arrayidx5 = getelementptr inbounds float, float* %out, i64 %indvars.iv 307 store float %add, float* %arrayidx5, align 4 308 br label %for.inc 309 310for.inc: 311 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16 312 %cmp = icmp ult i64 %indvars.iv, 4080 313 br i1 %cmp, label %for.body, label %for.end 314 315for.end: 316 ret void 317} 318 319; The source code 320;struct Out { 321; float a; 322; float b; 323;}; 324;void foo3 (In * __restrict__ in, Out * __restrict__ out, int * __restrict__ trigger) { 325; 326; for (int i=0; i<SIZE; i += 16) { 327; if (trigger[i] > 0) { 328; out[i].b = in[i].b + (float) 0.5; 329; } 330; } 331;} 332 333%struct.Out = type { float, float } 334 335define void @foo3(%struct.In* noalias %in, %struct.Out* noalias %out, i32* noalias %trigger) { 336; AVX512-LABEL: @foo3( 337; AVX512-NEXT: entry: 338; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 339; AVX512: vector.body: 340; AVX512-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 341; AVX512-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 16, i64 32, i64 48, i64 64, i64 80, i64 96, i64 112, i64 128, i64 144, i64 160, i64 176, i64 192, i64 208, i64 224, i64 240>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 342; AVX512-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 16 343; AVX512-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 344; AVX512-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 345; AVX512-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 32 346; AVX512-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 48 347; AVX512-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 64 348; AVX512-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 80 349; AVX512-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 96 350; AVX512-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 112 351; AVX512-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 128 352; AVX512-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 144 353; AVX512-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 160 354; AVX512-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 176 355; AVX512-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 192 356; AVX512-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 208 357; AVX512-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 224 358; AVX512-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 240 359; AVX512-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], <16 x i64> [[VEC_IND]] 360; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP16]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i32> undef) 361; AVX512-NEXT: [[TMP17:%.*]] = icmp sgt <16 x i32> [[WIDE_MASKED_GATHER]], zeroinitializer 362; AVX512-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], %struct.In* [[IN:%.*]], <16 x i64> [[VEC_IND]], i32 1 363; AVX512-NEXT: [[WIDE_MASKED_GATHER1:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[TMP18]], i32 4, <16 x i1> [[TMP17]], <16 x float> undef) 364; AVX512-NEXT: [[TMP19:%.*]] = fadd <16 x float> [[WIDE_MASKED_GATHER1]], <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> 365; AVX512-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_OUT:%.*]], %struct.Out* [[OUT:%.*]], <16 x i64> [[VEC_IND]], i32 1 366; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> [[TMP19]], <16 x float*> [[TMP20]], i32 4, <16 x i1> [[TMP17]]) 367; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 368; AVX512-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], <i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256> 369; AVX512-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 370; AVX512-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 371; AVX512: middle.block: 372; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 373; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 374; AVX512: for.body: 375; AVX512-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 376; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 377; AVX512-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 378; AVX512-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP22]], 0 379; AVX512-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 380; AVX512: if.then: 381; AVX512-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], %struct.In* [[IN]], i64 [[INDVARS_IV]], i32 1 382; AVX512-NEXT: [[TMP23:%.*]] = load float, float* [[B]], align 4 383; AVX512-NEXT: [[ADD:%.*]] = fadd float [[TMP23]], 5.000000e-01 384; AVX512-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_OUT]], %struct.Out* [[OUT]], i64 [[INDVARS_IV]], i32 1 385; AVX512-NEXT: store float [[ADD]], float* [[B6]], align 4 386; AVX512-NEXT: br label [[FOR_INC]] 387; AVX512: for.inc: 388; AVX512-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 389; AVX512-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 390; AVX512-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP7:![0-9]+]] 391; AVX512: for.end: 392; AVX512-NEXT: ret void 393; 394; FVW2-LABEL: @foo3( 395; FVW2-NEXT: entry: 396; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 397; FVW2: vector.body: 398; FVW2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ] 399; FVW2-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 16>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] 400; FVW2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 16 401; FVW2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 402; FVW2-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 403; FVW2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 404; FVW2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[TMP1]] 405; FVW2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 406; FVW2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 407; FVW2-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i32 0 408; FVW2-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP5]], i32 1 409; FVW2-NEXT: [[TMP8:%.*]] = icmp sgt <2 x i32> [[TMP7]], zeroinitializer 410; FVW2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], %struct.In* [[IN:%.*]], <2 x i64> [[VEC_IND]], i32 1 411; FVW2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> [[TMP9]], i32 4, <2 x i1> [[TMP8]], <2 x float> undef) 412; FVW2-NEXT: [[TMP10:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01> 413; FVW2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0 414; FVW2-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 415; FVW2: pred.store.if: 416; FVW2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_OUT:%.*]], %struct.Out* [[OUT:%.*]], i64 [[TMP0]], i32 1 417; FVW2-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[TMP10]], i32 0 418; FVW2-NEXT: store float [[TMP13]], float* [[TMP12]], align 4 419; FVW2-NEXT: br label [[PRED_STORE_CONTINUE]] 420; FVW2: pred.store.continue: 421; FVW2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1 422; FVW2-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]] 423; FVW2: pred.store.if1: 424; FVW2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_OUT]], %struct.Out* [[OUT]], i64 [[TMP1]], i32 1 425; FVW2-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP10]], i32 1 426; FVW2-NEXT: store float [[TMP16]], float* [[TMP15]], align 4 427; FVW2-NEXT: br label [[PRED_STORE_CONTINUE2]] 428; FVW2: pred.store.continue2: 429; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 430; FVW2-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 32, i64 32> 431; FVW2-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 432; FVW2-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 433; FVW2: middle.block: 434; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 435; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 436; FVW2: for.body: 437; FVW2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 438; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 439; FVW2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 440; FVW2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP18]], 0 441; FVW2-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 442; FVW2: if.then: 443; FVW2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], %struct.In* [[IN]], i64 [[INDVARS_IV]], i32 1 444; FVW2-NEXT: [[TMP19:%.*]] = load float, float* [[B]], align 4 445; FVW2-NEXT: [[ADD:%.*]] = fadd float [[TMP19]], 5.000000e-01 446; FVW2-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_OUT]], %struct.Out* [[OUT]], i64 [[INDVARS_IV]], i32 1 447; FVW2-NEXT: store float [[ADD]], float* [[B6]], align 4 448; FVW2-NEXT: br label [[FOR_INC]] 449; FVW2: for.inc: 450; FVW2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 451; FVW2-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 452; FVW2-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP7:![0-9]+]] 453; FVW2: for.end: 454; FVW2-NEXT: ret void 455; 456entry: 457 br label %for.body 458 459for.body: 460 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] 461 %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv 462 %0 = load i32, i32* %arrayidx, align 4 463 %cmp1 = icmp sgt i32 %0, 0 464 br i1 %cmp1, label %if.then, label %for.inc 465 466if.then: 467 %b = getelementptr inbounds %struct.In, %struct.In* %in, i64 %indvars.iv, i32 1 468 %1 = load float, float* %b, align 4 469 %add = fadd float %1, 5.000000e-01 470 %b6 = getelementptr inbounds %struct.Out, %struct.Out* %out, i64 %indvars.iv, i32 1 471 store float %add, float* %b6, align 4 472 br label %for.inc 473 474for.inc: 475 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16 476 %cmp = icmp ult i64 %indvars.iv, 4080 477 br i1 %cmp, label %for.body, label %for.end 478 479for.end: 480 ret void 481} 482declare void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float>, <16 x float*>, i32, <16 x i1>) 483 484; The same as @foo2 but scatter/gather argument is a vecotr of ptrs with addresspace 1 485 486define void @foo2_addrspace(%struct.In addrspace(1)* noalias %in, float addrspace(1)* noalias %out, i32* noalias %trigger, i32* noalias %index) #0 { 487; AVX512-LABEL: @foo2_addrspace( 488; AVX512-NEXT: entry: 489; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 490; AVX512: vector.body: 491; AVX512-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 492; AVX512-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 16, i64 32, i64 48, i64 64, i64 80, i64 96, i64 112, i64 128, i64 144, i64 160, i64 176, i64 192, i64 208, i64 224, i64 240>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 493; AVX512-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 494; AVX512-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 495; AVX512-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 496; AVX512-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 32 497; AVX512-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 48 498; AVX512-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 64 499; AVX512-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 80 500; AVX512-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 96 501; AVX512-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 112 502; AVX512-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 128 503; AVX512-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 144 504; AVX512-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 160 505; AVX512-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 176 506; AVX512-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 192 507; AVX512-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 208 508; AVX512-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 224 509; AVX512-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 240 510; AVX512-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], <16 x i64> [[VEC_IND]] 511; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP16]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i32> undef) 512; AVX512-NEXT: [[TMP17:%.*]] = icmp sgt <16 x i32> [[WIDE_MASKED_GATHER]], zeroinitializer 513; AVX512-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], [[STRUCT_IN]] addrspace(1)* [[IN:%.*]], <16 x i64> [[VEC_IND]], i32 1 514; AVX512-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p1f32(<16 x float addrspace(1)*> [[TMP18]], i32 4, <16 x i1> [[TMP17]], <16 x float> undef) 515; AVX512-NEXT: [[TMP19:%.*]] = fadd <16 x float> [[WIDE_MASKED_GATHER2]], <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> 516; AVX512-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT:%.*]], <16 x i64> [[VEC_IND]] 517; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p1f32(<16 x float> [[TMP19]], <16 x float addrspace(1)*> [[TMP20]], i32 4, <16 x i1> [[TMP17]]) 518; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 16 519; AVX512-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], <i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256> 520; AVX512-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 521; AVX512-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 522; AVX512: middle.block: 523; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 524; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 525; AVX512: for.body: 526; AVX512-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 527; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 528; AVX512-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 529; AVX512-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP22]], 0 530; AVX512-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 531; AVX512: if.then: 532; AVX512-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], [[STRUCT_IN]] addrspace(1)* [[IN]], i64 [[INDVARS_IV]], i32 1 533; AVX512-NEXT: [[TMP23:%.*]] = load float, float addrspace(1)* [[B]], align 4 534; AVX512-NEXT: [[ADD:%.*]] = fadd float [[TMP23]], 5.000000e-01 535; AVX512-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT]], i64 [[INDVARS_IV]] 536; AVX512-NEXT: store float [[ADD]], float addrspace(1)* [[ARRAYIDX5]], align 4 537; AVX512-NEXT: br label [[FOR_INC]] 538; AVX512: for.inc: 539; AVX512-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 540; AVX512-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 541; AVX512-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP9:![0-9]+]] 542; AVX512: for.end: 543; AVX512-NEXT: ret void 544; 545; FVW2-LABEL: @foo2_addrspace( 546; FVW2-NEXT: entry: 547; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 548; FVW2: vector.body: 549; FVW2-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ] 550; FVW2-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 16>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE3]] ] 551; FVW2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 552; FVW2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 553; FVW2-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 554; FVW2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 555; FVW2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[TMP1]] 556; FVW2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 557; FVW2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 558; FVW2-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i32 0 559; FVW2-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP5]], i32 1 560; FVW2-NEXT: [[TMP8:%.*]] = icmp sgt <2 x i32> [[TMP7]], zeroinitializer 561; FVW2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], [[STRUCT_IN]] addrspace(1)* [[IN:%.*]], <2 x i64> [[VEC_IND]], i32 1 562; FVW2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p1f32(<2 x float addrspace(1)*> [[TMP9]], i32 4, <2 x i1> [[TMP8]], <2 x float> undef) 563; FVW2-NEXT: [[TMP10:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01> 564; FVW2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0 565; FVW2-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 566; FVW2: pred.store.if: 567; FVW2-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT:%.*]], i64 [[TMP0]] 568; FVW2-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[TMP10]], i32 0 569; FVW2-NEXT: store float [[TMP13]], float addrspace(1)* [[TMP12]], align 4 570; FVW2-NEXT: br label [[PRED_STORE_CONTINUE]] 571; FVW2: pred.store.continue: 572; FVW2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1 573; FVW2-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]] 574; FVW2: pred.store.if2: 575; FVW2-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT]], i64 [[TMP1]] 576; FVW2-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP10]], i32 1 577; FVW2-NEXT: store float [[TMP16]], float addrspace(1)* [[TMP15]], align 4 578; FVW2-NEXT: br label [[PRED_STORE_CONTINUE3]] 579; FVW2: pred.store.continue3: 580; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 2 581; FVW2-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 32, i64 32> 582; FVW2-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 583; FVW2-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 584; FVW2: middle.block: 585; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 586; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 587; FVW2: for.body: 588; FVW2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 589; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 590; FVW2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 591; FVW2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP18]], 0 592; FVW2-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 593; FVW2: if.then: 594; FVW2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], [[STRUCT_IN]] addrspace(1)* [[IN]], i64 [[INDVARS_IV]], i32 1 595; FVW2-NEXT: [[TMP19:%.*]] = load float, float addrspace(1)* [[B]], align 4 596; FVW2-NEXT: [[ADD:%.*]] = fadd float [[TMP19]], 5.000000e-01 597; FVW2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT]], i64 [[INDVARS_IV]] 598; FVW2-NEXT: store float [[ADD]], float addrspace(1)* [[ARRAYIDX5]], align 4 599; FVW2-NEXT: br label [[FOR_INC]] 600; FVW2: for.inc: 601; FVW2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 602; FVW2-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 603; FVW2-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP9:![0-9]+]] 604; FVW2: for.end: 605; FVW2-NEXT: ret void 606; 607entry: 608 br label %for.body 609 610for.body: 611 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] 612 %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv 613 %0 = load i32, i32* %arrayidx, align 4 614 %cmp1 = icmp sgt i32 %0, 0 615 br i1 %cmp1, label %if.then, label %for.inc 616 617if.then: 618 %b = getelementptr inbounds %struct.In, %struct.In addrspace(1)* %in, i64 %indvars.iv, i32 1 619 %1 = load float, float addrspace(1)* %b, align 4 620 %add = fadd float %1, 5.000000e-01 621 %arrayidx5 = getelementptr inbounds float, float addrspace(1)* %out, i64 %indvars.iv 622 store float %add, float addrspace(1)* %arrayidx5, align 4 623 br label %for.inc 624 625for.inc: 626 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16 627 %cmp = icmp ult i64 %indvars.iv, 4080 628 br i1 %cmp, label %for.body, label %for.end 629 630for.end: 631 ret void 632} 633 634; Same as foo2_addrspace but here only the input has the non-default address space. 635 636define void @foo2_addrspace2(%struct.In addrspace(1)* noalias %in, float addrspace(0)* noalias %out, i32* noalias %trigger, i32* noalias %index) { 637; AVX512-LABEL: @foo2_addrspace2( 638; AVX512-NEXT: entry: 639; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 640; AVX512: vector.body: 641; AVX512-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 642; AVX512-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 16, i64 32, i64 48, i64 64, i64 80, i64 96, i64 112, i64 128, i64 144, i64 160, i64 176, i64 192, i64 208, i64 224, i64 240>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 643; AVX512-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 644; AVX512-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 645; AVX512-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 646; AVX512-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 32 647; AVX512-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 48 648; AVX512-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 64 649; AVX512-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 80 650; AVX512-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 96 651; AVX512-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 112 652; AVX512-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 128 653; AVX512-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 144 654; AVX512-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 160 655; AVX512-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 176 656; AVX512-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 192 657; AVX512-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 208 658; AVX512-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 224 659; AVX512-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 240 660; AVX512-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], <16 x i64> [[VEC_IND]] 661; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP16]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i32> undef) 662; AVX512-NEXT: [[TMP17:%.*]] = icmp sgt <16 x i32> [[WIDE_MASKED_GATHER]], zeroinitializer 663; AVX512-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], [[STRUCT_IN]] addrspace(1)* [[IN:%.*]], <16 x i64> [[VEC_IND]], i32 1 664; AVX512-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p1f32(<16 x float addrspace(1)*> [[TMP18]], i32 4, <16 x i1> [[TMP17]], <16 x float> undef) 665; AVX512-NEXT: [[TMP19:%.*]] = fadd <16 x float> [[WIDE_MASKED_GATHER2]], <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> 666; AVX512-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, float* [[OUT:%.*]], <16 x i64> [[VEC_IND]] 667; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> [[TMP19]], <16 x float*> [[TMP20]], i32 4, <16 x i1> [[TMP17]]) 668; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 16 669; AVX512-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], <i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256> 670; AVX512-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 671; AVX512-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 672; AVX512: middle.block: 673; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 674; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 675; AVX512: for.body: 676; AVX512-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 677; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 678; AVX512-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 679; AVX512-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP22]], 0 680; AVX512-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 681; AVX512: if.then: 682; AVX512-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], [[STRUCT_IN]] addrspace(1)* [[IN]], i64 [[INDVARS_IV]], i32 1 683; AVX512-NEXT: [[TMP23:%.*]] = load float, float addrspace(1)* [[B]], align 4 684; AVX512-NEXT: [[ADD:%.*]] = fadd float [[TMP23]], 5.000000e-01 685; AVX512-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDVARS_IV]] 686; AVX512-NEXT: store float [[ADD]], float* [[ARRAYIDX5]], align 4 687; AVX512-NEXT: br label [[FOR_INC]] 688; AVX512: for.inc: 689; AVX512-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 690; AVX512-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 691; AVX512-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP11:![0-9]+]] 692; AVX512: for.end: 693; AVX512-NEXT: ret void 694; 695; FVW2-LABEL: @foo2_addrspace2( 696; FVW2-NEXT: entry: 697; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 698; FVW2: vector.body: 699; FVW2-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ] 700; FVW2-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 16>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE3]] ] 701; FVW2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 702; FVW2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 703; FVW2-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 704; FVW2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 705; FVW2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[TMP1]] 706; FVW2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 707; FVW2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 708; FVW2-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i32 0 709; FVW2-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP5]], i32 1 710; FVW2-NEXT: [[TMP8:%.*]] = icmp sgt <2 x i32> [[TMP7]], zeroinitializer 711; FVW2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], [[STRUCT_IN]] addrspace(1)* [[IN:%.*]], <2 x i64> [[VEC_IND]], i32 1 712; FVW2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p1f32(<2 x float addrspace(1)*> [[TMP9]], i32 4, <2 x i1> [[TMP8]], <2 x float> undef) 713; FVW2-NEXT: [[TMP10:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01> 714; FVW2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0 715; FVW2-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 716; FVW2: pred.store.if: 717; FVW2-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, float* [[OUT:%.*]], i64 [[TMP0]] 718; FVW2-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[TMP10]], i32 0 719; FVW2-NEXT: store float [[TMP13]], float* [[TMP12]], align 4 720; FVW2-NEXT: br label [[PRED_STORE_CONTINUE]] 721; FVW2: pred.store.continue: 722; FVW2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1 723; FVW2-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]] 724; FVW2: pred.store.if2: 725; FVW2-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[TMP1]] 726; FVW2-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP10]], i32 1 727; FVW2-NEXT: store float [[TMP16]], float* [[TMP15]], align 4 728; FVW2-NEXT: br label [[PRED_STORE_CONTINUE3]] 729; FVW2: pred.store.continue3: 730; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 2 731; FVW2-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 32, i64 32> 732; FVW2-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 733; FVW2-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 734; FVW2: middle.block: 735; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 736; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 737; FVW2: for.body: 738; FVW2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 739; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 740; FVW2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 741; FVW2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP18]], 0 742; FVW2-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 743; FVW2: if.then: 744; FVW2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], [[STRUCT_IN]] addrspace(1)* [[IN]], i64 [[INDVARS_IV]], i32 1 745; FVW2-NEXT: [[TMP19:%.*]] = load float, float addrspace(1)* [[B]], align 4 746; FVW2-NEXT: [[ADD:%.*]] = fadd float [[TMP19]], 5.000000e-01 747; FVW2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDVARS_IV]] 748; FVW2-NEXT: store float [[ADD]], float* [[ARRAYIDX5]], align 4 749; FVW2-NEXT: br label [[FOR_INC]] 750; FVW2: for.inc: 751; FVW2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 752; FVW2-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 753; FVW2-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP11:![0-9]+]] 754; FVW2: for.end: 755; FVW2-NEXT: ret void 756; 757entry: 758 br label %for.body 759 760for.body: 761 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] 762 %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv 763 %0 = load i32, i32* %arrayidx, align 4 764 %cmp1 = icmp sgt i32 %0, 0 765 br i1 %cmp1, label %if.then, label %for.inc 766 767if.then: 768 %b = getelementptr inbounds %struct.In, %struct.In addrspace(1)* %in, i64 %indvars.iv, i32 1 769 %1 = load float, float addrspace(1)* %b, align 4 770 %add = fadd float %1, 5.000000e-01 771 %arrayidx5 = getelementptr inbounds float, float* %out, i64 %indvars.iv 772 store float %add, float* %arrayidx5, align 4 773 br label %for.inc 774 775for.inc: 776 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16 777 %cmp = icmp ult i64 %indvars.iv, 4080 778 br i1 %cmp, label %for.body, label %for.end 779 780for.end: 781 ret void 782} 783 784; Same as foo2_addrspace but here only the output has the non-default address space. 785 786define void @foo2_addrspace3(%struct.In addrspace(0)* noalias %in, float addrspace(1)* noalias %out, i32* noalias %trigger, i32* noalias %index) { 787; AVX512-LABEL: @foo2_addrspace3( 788; AVX512-NEXT: entry: 789; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 790; AVX512: vector.body: 791; AVX512-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 792; AVX512-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 16, i64 32, i64 48, i64 64, i64 80, i64 96, i64 112, i64 128, i64 144, i64 160, i64 176, i64 192, i64 208, i64 224, i64 240>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 793; AVX512-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 794; AVX512-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 795; AVX512-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 796; AVX512-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 32 797; AVX512-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 48 798; AVX512-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 64 799; AVX512-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 80 800; AVX512-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 96 801; AVX512-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 112 802; AVX512-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 128 803; AVX512-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 144 804; AVX512-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 160 805; AVX512-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 176 806; AVX512-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 192 807; AVX512-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 208 808; AVX512-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 224 809; AVX512-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 240 810; AVX512-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], <16 x i64> [[VEC_IND]] 811; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP16]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x i32> undef) 812; AVX512-NEXT: [[TMP17:%.*]] = icmp sgt <16 x i32> [[WIDE_MASKED_GATHER]], zeroinitializer 813; AVX512-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], %struct.In* [[IN:%.*]], <16 x i64> [[VEC_IND]], i32 1 814; AVX512-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[TMP18]], i32 4, <16 x i1> [[TMP17]], <16 x float> undef) 815; AVX512-NEXT: [[TMP19:%.*]] = fadd <16 x float> [[WIDE_MASKED_GATHER2]], <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> 816; AVX512-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT:%.*]], <16 x i64> [[VEC_IND]] 817; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p1f32(<16 x float> [[TMP19]], <16 x float addrspace(1)*> [[TMP20]], i32 4, <16 x i1> [[TMP17]]) 818; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 16 819; AVX512-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], <i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256, i64 256> 820; AVX512-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 821; AVX512-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 822; AVX512: middle.block: 823; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 824; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 825; AVX512: for.body: 826; AVX512-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 827; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 828; AVX512-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 829; AVX512-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP22]], 0 830; AVX512-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 831; AVX512: if.then: 832; AVX512-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], %struct.In* [[IN]], i64 [[INDVARS_IV]], i32 1 833; AVX512-NEXT: [[TMP23:%.*]] = load float, float* [[B]], align 4 834; AVX512-NEXT: [[ADD:%.*]] = fadd float [[TMP23]], 5.000000e-01 835; AVX512-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT]], i64 [[INDVARS_IV]] 836; AVX512-NEXT: store float [[ADD]], float addrspace(1)* [[ARRAYIDX5]], align 4 837; AVX512-NEXT: br label [[FOR_INC]] 838; AVX512: for.inc: 839; AVX512-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 840; AVX512-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 841; AVX512-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP13:![0-9]+]] 842; AVX512: for.end: 843; AVX512-NEXT: ret void 844; 845; FVW2-LABEL: @foo2_addrspace3( 846; FVW2-NEXT: entry: 847; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 848; FVW2: vector.body: 849; FVW2-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE3:%.*]] ] 850; FVW2-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 16>, [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE3]] ] 851; FVW2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX1]], 16 852; FVW2-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 853; FVW2-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 854; FVW2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[TMP0]] 855; FVW2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[TMP1]] 856; FVW2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 857; FVW2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 858; FVW2-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i32 0 859; FVW2-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP5]], i32 1 860; FVW2-NEXT: [[TMP8:%.*]] = icmp sgt <2 x i32> [[TMP7]], zeroinitializer 861; FVW2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_IN:%.*]], %struct.In* [[IN:%.*]], <2 x i64> [[VEC_IND]], i32 1 862; FVW2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> [[TMP9]], i32 4, <2 x i1> [[TMP8]], <2 x float> undef) 863; FVW2-NEXT: [[TMP10:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER]], <float 5.000000e-01, float 5.000000e-01> 864; FVW2-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0 865; FVW2-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] 866; FVW2: pred.store.if: 867; FVW2-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT:%.*]], i64 [[TMP0]] 868; FVW2-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[TMP10]], i32 0 869; FVW2-NEXT: store float [[TMP13]], float addrspace(1)* [[TMP12]], align 4 870; FVW2-NEXT: br label [[PRED_STORE_CONTINUE]] 871; FVW2: pred.store.continue: 872; FVW2-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1 873; FVW2-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3]] 874; FVW2: pred.store.if2: 875; FVW2-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT]], i64 [[TMP1]] 876; FVW2-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP10]], i32 1 877; FVW2-NEXT: store float [[TMP16]], float addrspace(1)* [[TMP15]], align 4 878; FVW2-NEXT: br label [[PRED_STORE_CONTINUE3]] 879; FVW2: pred.store.continue3: 880; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 2 881; FVW2-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 32, i64 32> 882; FVW2-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 883; FVW2-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 884; FVW2: middle.block: 885; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 256, 256 886; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]] 887; FVW2: for.body: 888; FVW2-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ], [ 4096, [[MIDDLE_BLOCK]] ] 889; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDVARS_IV]] 890; FVW2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 891; FVW2-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP18]], 0 892; FVW2-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[FOR_INC]] 893; FVW2: if.then: 894; FVW2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_IN]], %struct.In* [[IN]], i64 [[INDVARS_IV]], i32 1 895; FVW2-NEXT: [[TMP19:%.*]] = load float, float* [[B]], align 4 896; FVW2-NEXT: [[ADD:%.*]] = fadd float [[TMP19]], 5.000000e-01 897; FVW2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float addrspace(1)* [[OUT]], i64 [[INDVARS_IV]] 898; FVW2-NEXT: store float [[ADD]], float addrspace(1)* [[ARRAYIDX5]], align 4 899; FVW2-NEXT: br label [[FOR_INC]] 900; FVW2: for.inc: 901; FVW2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 16 902; FVW2-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 4080 903; FVW2-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop [[LOOP13:![0-9]+]] 904; FVW2: for.end: 905; FVW2-NEXT: ret void 906; 907entry: 908 br label %for.body 909 910for.body: 911 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] 912 %arrayidx = getelementptr inbounds i32, i32* %trigger, i64 %indvars.iv 913 %0 = load i32, i32* %arrayidx, align 4 914 %cmp1 = icmp sgt i32 %0, 0 915 br i1 %cmp1, label %if.then, label %for.inc 916 917if.then: 918 %b = getelementptr inbounds %struct.In, %struct.In* %in, i64 %indvars.iv, i32 1 919 %1 = load float, float* %b, align 4 920 %add = fadd float %1, 5.000000e-01 921 %arrayidx5 = getelementptr inbounds float, float addrspace(1)* %out, i64 %indvars.iv 922 store float %add, float addrspace(1)* %arrayidx5, align 4 923 br label %for.inc 924 925for.inc: 926 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16 927 %cmp = icmp ult i64 %indvars.iv, 4080 928 br i1 %cmp, label %for.body, label %for.end 929 930for.end: 931 ret void 932} 933 934; Using gathers is not profitable for this function. PR48429. 935define void @test_gather_not_profitable_pr48429(i32 %d, float* readonly noalias %ptr, float* nocapture noalias %dest) { 936; AVX512-LABEL: @test_gather_not_profitable_pr48429( 937; AVX512-NEXT: entry: 938; AVX512-NEXT: [[DEST1:%.*]] = bitcast float* [[DEST:%.*]] to i8* 939; AVX512-NEXT: [[PTR3:%.*]] = bitcast float* [[PTR:%.*]] to i8* 940; AVX512-NEXT: [[IDX_EXT:%.*]] = sext i32 [[D:%.*]] to i64 941; AVX512-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 [[IDX_EXT]] 942; AVX512-NEXT: [[CMP_NOT10:%.*]] = icmp eq i32 [[D]], 0 943; AVX512-NEXT: br i1 [[CMP_NOT10]], label [[FOR_END:%.*]], label [[FOR_BODY_LR_PH:%.*]] 944; AVX512: for.body.lr.ph: 945; AVX512-NEXT: [[MUL:%.*]] = sub nsw i32 0, [[D]] 946; AVX512-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64 947; AVX512-NEXT: [[TMP0:%.*]] = shl nsw i64 [[IDX_EXT]], 2 948; AVX512-NEXT: [[TMP1:%.*]] = add nsw i64 [[TMP0]], -4 949; AVX512-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2 950; AVX512-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1 951; AVX512-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 16 952; AVX512-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 953; AVX512: vector.memcheck: 954; AVX512-NEXT: [[TMP4:%.*]] = shl nsw i64 [[IDX_EXT]], 2 955; AVX512-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], -4 956; AVX512-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 2 957; AVX512-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 4 958; AVX512-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP7]], 2 959; AVX512-NEXT: [[SCEVGEP:%.*]] = getelementptr float, float* [[DEST]], i64 [[TMP8]] 960; AVX512-NEXT: [[SCEVGEP2:%.*]] = bitcast float* [[SCEVGEP]] to i8* 961; AVX512-NEXT: [[TMP9:%.*]] = add nuw nsw i64 [[TMP6]], 1 962; AVX512-NEXT: [[SCEVGEP4:%.*]] = getelementptr float, float* [[PTR]], i64 [[TMP9]] 963; AVX512-NEXT: [[SCEVGEP45:%.*]] = bitcast float* [[SCEVGEP4]] to i8* 964; AVX512-NEXT: [[SCEVGEP6:%.*]] = getelementptr float, float* [[PTR]], i64 [[IDXPROM]] 965; AVX512-NEXT: [[SCEVGEP67:%.*]] = bitcast float* [[SCEVGEP6]] to i8* 966; AVX512-NEXT: [[TMP10:%.*]] = add i64 [[TMP6]], 1 967; AVX512-NEXT: [[TMP11:%.*]] = sub i64 [[TMP10]], [[IDX_EXT]] 968; AVX512-NEXT: [[SCEVGEP8:%.*]] = getelementptr float, float* [[PTR]], i64 [[TMP11]] 969; AVX512-NEXT: [[SCEVGEP89:%.*]] = bitcast float* [[SCEVGEP8]] to i8* 970; AVX512-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[DEST1]], [[SCEVGEP45]] 971; AVX512-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[PTR3]], [[SCEVGEP2]] 972; AVX512-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 973; AVX512-NEXT: [[BOUND010:%.*]] = icmp ult i8* [[DEST1]], [[SCEVGEP89]] 974; AVX512-NEXT: [[BOUND111:%.*]] = icmp ult i8* [[SCEVGEP67]], [[SCEVGEP2]] 975; AVX512-NEXT: [[FOUND_CONFLICT12:%.*]] = and i1 [[BOUND010]], [[BOUND111]] 976; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT12]] 977; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 978; AVX512: vector.ph: 979; AVX512-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 16 980; AVX512-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]] 981; AVX512-NEXT: [[IND_END:%.*]] = getelementptr float, float* [[PTR]], i64 [[N_VEC]] 982; AVX512-NEXT: [[TMP12:%.*]] = mul i64 [[N_VEC]], 16 983; AVX512-NEXT: [[IND_END14:%.*]] = getelementptr float, float* [[DEST]], i64 [[TMP12]] 984; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] 985; AVX512: vector.body: 986; AVX512-NEXT: [[POINTER_PHI:%.*]] = phi float* [ [[DEST]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ] 987; AVX512-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 988; AVX512-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 0 989; AVX512-NEXT: [[NEXT_GEP:%.*]] = getelementptr float, float* [[PTR]], i64 [[TMP13]] 990; AVX512-NEXT: [[TMP14:%.*]] = getelementptr float, float* [[POINTER_PHI]], <16 x i64> <i64 0, i64 16, i64 32, i64 48, i64 64, i64 80, i64 96, i64 112, i64 128, i64 144, i64 160, i64 176, i64 192, i64 208, i64 224, i64 240> 991; AVX512-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, float* [[NEXT_GEP]], i64 [[IDXPROM]] 992; AVX512-NEXT: [[TMP16:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 0 993; AVX512-NEXT: [[TMP17:%.*]] = bitcast float* [[TMP16]] to <16 x float>* 994; AVX512-NEXT: [[WIDE_LOAD:%.*]] = load <16 x float>, <16 x float>* [[TMP17]], align 4, !alias.scope !14 995; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> [[WIDE_LOAD]], <16 x float*> [[TMP14]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>), !alias.scope !17, !noalias !19 996; AVX512-NEXT: [[TMP18:%.*]] = getelementptr float, float* [[NEXT_GEP]], i32 0 997; AVX512-NEXT: [[TMP19:%.*]] = bitcast float* [[TMP18]] to <16 x float>* 998; AVX512-NEXT: [[WIDE_LOAD15:%.*]] = load <16 x float>, <16 x float>* [[TMP19]], align 4, !alias.scope !21 999; AVX512-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, <16 x float*> [[TMP14]], i64 1 1000; AVX512-NEXT: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> [[WIDE_LOAD15]], <16 x float*> [[TMP20]], i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>), !alias.scope !17, !noalias !19 1001; AVX512-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1002; AVX512-NEXT: [[PTR_IND]] = getelementptr float, float* [[POINTER_PHI]], i64 256 1003; AVX512-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1004; AVX512-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] 1005; AVX512: middle.block: 1006; AVX512-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]] 1007; AVX512-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[SCALAR_PH]] 1008; AVX512: scalar.ph: 1009; AVX512-NEXT: [[BC_RESUME_VAL:%.*]] = phi float* [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[PTR]], [[FOR_BODY_LR_PH]] ], [ [[PTR]], [[VECTOR_MEMCHECK]] ] 1010; AVX512-NEXT: [[BC_RESUME_VAL13:%.*]] = phi float* [ [[IND_END14]], [[MIDDLE_BLOCK]] ], [ [[DEST]], [[FOR_BODY_LR_PH]] ], [ [[DEST]], [[VECTOR_MEMCHECK]] ] 1011; AVX512-NEXT: br label [[FOR_BODY:%.*]] 1012; AVX512: for.body: 1013; AVX512-NEXT: [[PTR_ADDR_012:%.*]] = phi float* [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ] 1014; AVX512-NEXT: [[DEST_ADDR_011:%.*]] = phi float* [ [[BC_RESUME_VAL13]], [[SCALAR_PH]] ], [ [[ADD_PTR6:%.*]], [[FOR_BODY]] ] 1015; AVX512-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[PTR_ADDR_012]], i64 [[IDXPROM]] 1016; AVX512-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX]], align 4 1017; AVX512-NEXT: store float [[TMP22]], float* [[DEST_ADDR_011]], align 4 1018; AVX512-NEXT: [[TMP23:%.*]] = load float, float* [[PTR_ADDR_012]], align 4 1019; AVX512-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[DEST_ADDR_011]], i64 1 1020; AVX512-NEXT: store float [[TMP23]], float* [[ARRAYIDX5]], align 4 1021; AVX512-NEXT: [[INCDEC_PTR]] = getelementptr inbounds float, float* [[PTR_ADDR_012]], i64 1 1022; AVX512-NEXT: [[ADD_PTR6]] = getelementptr inbounds float, float* [[DEST_ADDR_011]], i64 16 1023; AVX512-NEXT: [[CMP_NOT:%.*]] = icmp eq float* [[INCDEC_PTR]], [[ADD_PTR]] 1024; AVX512-NEXT: br i1 [[CMP_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]] 1025; AVX512: for.end: 1026; AVX512-NEXT: ret void 1027; 1028; FVW2-LABEL: @test_gather_not_profitable_pr48429( 1029; FVW2-NEXT: entry: 1030; FVW2-NEXT: [[DEST1:%.*]] = bitcast float* [[DEST:%.*]] to i8* 1031; FVW2-NEXT: [[PTR3:%.*]] = bitcast float* [[PTR:%.*]] to i8* 1032; FVW2-NEXT: [[IDX_EXT:%.*]] = sext i32 [[D:%.*]] to i64 1033; FVW2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 [[IDX_EXT]] 1034; FVW2-NEXT: [[CMP_NOT10:%.*]] = icmp eq i32 [[D]], 0 1035; FVW2-NEXT: br i1 [[CMP_NOT10]], label [[FOR_END:%.*]], label [[FOR_BODY_LR_PH:%.*]] 1036; FVW2: for.body.lr.ph: 1037; FVW2-NEXT: [[MUL:%.*]] = sub nsw i32 0, [[D]] 1038; FVW2-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64 1039; FVW2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[IDX_EXT]], 2 1040; FVW2-NEXT: [[TMP1:%.*]] = add nsw i64 [[TMP0]], -4 1041; FVW2-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2 1042; FVW2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1 1043; FVW2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2 1044; FVW2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 1045; FVW2: vector.memcheck: 1046; FVW2-NEXT: [[TMP4:%.*]] = shl nsw i64 [[IDX_EXT]], 2 1047; FVW2-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], -4 1048; FVW2-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 2 1049; FVW2-NEXT: [[TMP7:%.*]] = shl i64 [[TMP6]], 4 1050; FVW2-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP7]], 2 1051; FVW2-NEXT: [[SCEVGEP:%.*]] = getelementptr float, float* [[DEST]], i64 [[TMP8]] 1052; FVW2-NEXT: [[SCEVGEP2:%.*]] = bitcast float* [[SCEVGEP]] to i8* 1053; FVW2-NEXT: [[TMP9:%.*]] = add nuw nsw i64 [[TMP6]], 1 1054; FVW2-NEXT: [[SCEVGEP4:%.*]] = getelementptr float, float* [[PTR]], i64 [[TMP9]] 1055; FVW2-NEXT: [[SCEVGEP45:%.*]] = bitcast float* [[SCEVGEP4]] to i8* 1056; FVW2-NEXT: [[SCEVGEP6:%.*]] = getelementptr float, float* [[PTR]], i64 [[IDXPROM]] 1057; FVW2-NEXT: [[SCEVGEP67:%.*]] = bitcast float* [[SCEVGEP6]] to i8* 1058; FVW2-NEXT: [[TMP10:%.*]] = add i64 [[TMP6]], 1 1059; FVW2-NEXT: [[TMP11:%.*]] = sub i64 [[TMP10]], [[IDX_EXT]] 1060; FVW2-NEXT: [[SCEVGEP8:%.*]] = getelementptr float, float* [[PTR]], i64 [[TMP11]] 1061; FVW2-NEXT: [[SCEVGEP89:%.*]] = bitcast float* [[SCEVGEP8]] to i8* 1062; FVW2-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[DEST1]], [[SCEVGEP45]] 1063; FVW2-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[PTR3]], [[SCEVGEP2]] 1064; FVW2-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 1065; FVW2-NEXT: [[BOUND010:%.*]] = icmp ult i8* [[DEST1]], [[SCEVGEP89]] 1066; FVW2-NEXT: [[BOUND111:%.*]] = icmp ult i8* [[SCEVGEP67]], [[SCEVGEP2]] 1067; FVW2-NEXT: [[FOUND_CONFLICT12:%.*]] = and i1 [[BOUND010]], [[BOUND111]] 1068; FVW2-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT12]] 1069; FVW2-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 1070; FVW2: vector.ph: 1071; FVW2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2 1072; FVW2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]] 1073; FVW2-NEXT: [[IND_END:%.*]] = getelementptr float, float* [[PTR]], i64 [[N_VEC]] 1074; FVW2-NEXT: [[TMP12:%.*]] = mul i64 [[N_VEC]], 16 1075; FVW2-NEXT: [[IND_END14:%.*]] = getelementptr float, float* [[DEST]], i64 [[TMP12]] 1076; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] 1077; FVW2: vector.body: 1078; FVW2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 1079; FVW2-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 0 1080; FVW2-NEXT: [[NEXT_GEP:%.*]] = getelementptr float, float* [[PTR]], i64 [[TMP13]] 1081; FVW2-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 0 1082; FVW2-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 16 1083; FVW2-NEXT: [[NEXT_GEP15:%.*]] = getelementptr float, float* [[DEST]], i64 [[TMP15]] 1084; FVW2-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 1 1085; FVW2-NEXT: [[TMP17:%.*]] = mul i64 [[TMP16]], 16 1086; FVW2-NEXT: [[NEXT_GEP16:%.*]] = getelementptr float, float* [[DEST]], i64 [[TMP17]] 1087; FVW2-NEXT: [[TMP18:%.*]] = getelementptr inbounds float, float* [[NEXT_GEP]], i64 [[IDXPROM]] 1088; FVW2-NEXT: [[TMP19:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 0 1089; FVW2-NEXT: [[TMP20:%.*]] = bitcast float* [[TMP19]] to <2 x float>* 1090; FVW2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x float>, <2 x float>* [[TMP20]], align 4, !alias.scope !14 1091; FVW2-NEXT: [[TMP21:%.*]] = extractelement <2 x float> [[WIDE_LOAD]], i32 0 1092; FVW2-NEXT: store float [[TMP21]], float* [[NEXT_GEP15]], align 4, !alias.scope !17, !noalias !19 1093; FVW2-NEXT: [[TMP22:%.*]] = extractelement <2 x float> [[WIDE_LOAD]], i32 1 1094; FVW2-NEXT: store float [[TMP22]], float* [[NEXT_GEP16]], align 4, !alias.scope !17, !noalias !19 1095; FVW2-NEXT: [[TMP23:%.*]] = getelementptr float, float* [[NEXT_GEP]], i32 0 1096; FVW2-NEXT: [[TMP24:%.*]] = bitcast float* [[TMP23]] to <2 x float>* 1097; FVW2-NEXT: [[WIDE_LOAD17:%.*]] = load <2 x float>, <2 x float>* [[TMP24]], align 4, !alias.scope !21 1098; FVW2-NEXT: [[TMP25:%.*]] = getelementptr inbounds float, float* [[NEXT_GEP15]], i64 1 1099; FVW2-NEXT: [[TMP26:%.*]] = getelementptr inbounds float, float* [[NEXT_GEP16]], i64 1 1100; FVW2-NEXT: [[TMP27:%.*]] = extractelement <2 x float> [[WIDE_LOAD17]], i32 0 1101; FVW2-NEXT: store float [[TMP27]], float* [[TMP25]], align 4, !alias.scope !17, !noalias !19 1102; FVW2-NEXT: [[TMP28:%.*]] = extractelement <2 x float> [[WIDE_LOAD17]], i32 1 1103; FVW2-NEXT: store float [[TMP28]], float* [[TMP26]], align 4, !alias.scope !17, !noalias !19 1104; FVW2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 1105; FVW2-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1106; FVW2-NEXT: br i1 [[TMP29]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] 1107; FVW2: middle.block: 1108; FVW2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]] 1109; FVW2-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[SCALAR_PH]] 1110; FVW2: scalar.ph: 1111; FVW2-NEXT: [[BC_RESUME_VAL:%.*]] = phi float* [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[PTR]], [[FOR_BODY_LR_PH]] ], [ [[PTR]], [[VECTOR_MEMCHECK]] ] 1112; FVW2-NEXT: [[BC_RESUME_VAL13:%.*]] = phi float* [ [[IND_END14]], [[MIDDLE_BLOCK]] ], [ [[DEST]], [[FOR_BODY_LR_PH]] ], [ [[DEST]], [[VECTOR_MEMCHECK]] ] 1113; FVW2-NEXT: br label [[FOR_BODY:%.*]] 1114; FVW2: for.body: 1115; FVW2-NEXT: [[PTR_ADDR_012:%.*]] = phi float* [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ] 1116; FVW2-NEXT: [[DEST_ADDR_011:%.*]] = phi float* [ [[BC_RESUME_VAL13]], [[SCALAR_PH]] ], [ [[ADD_PTR6:%.*]], [[FOR_BODY]] ] 1117; FVW2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[PTR_ADDR_012]], i64 [[IDXPROM]] 1118; FVW2-NEXT: [[TMP30:%.*]] = load float, float* [[ARRAYIDX]], align 4 1119; FVW2-NEXT: store float [[TMP30]], float* [[DEST_ADDR_011]], align 4 1120; FVW2-NEXT: [[TMP31:%.*]] = load float, float* [[PTR_ADDR_012]], align 4 1121; FVW2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[DEST_ADDR_011]], i64 1 1122; FVW2-NEXT: store float [[TMP31]], float* [[ARRAYIDX5]], align 4 1123; FVW2-NEXT: [[INCDEC_PTR]] = getelementptr inbounds float, float* [[PTR_ADDR_012]], i64 1 1124; FVW2-NEXT: [[ADD_PTR6]] = getelementptr inbounds float, float* [[DEST_ADDR_011]], i64 16 1125; FVW2-NEXT: [[CMP_NOT:%.*]] = icmp eq float* [[INCDEC_PTR]], [[ADD_PTR]] 1126; FVW2-NEXT: br i1 [[CMP_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]] 1127; FVW2: for.end: 1128; FVW2-NEXT: ret void 1129; 1130entry: 1131 %idx.ext = sext i32 %d to i64 1132 %add.ptr = getelementptr inbounds float, float* %ptr, i64 %idx.ext 1133 %cmp.not10 = icmp eq i32 %d, 0 1134 br i1 %cmp.not10, label %for.end, label %for.body.lr.ph 1135 1136for.body.lr.ph: 1137 %mul = sub nsw i32 0, %d 1138 %idxprom = sext i32 %mul to i64 1139 br label %for.body 1140 1141for.body: 1142 %ptr.addr.012 = phi float* [ %ptr, %for.body.lr.ph ], [ %incdec.ptr, %for.body ] 1143 %dest.addr.011 = phi float* [ %dest, %for.body.lr.ph ], [ %add.ptr6, %for.body ] 1144 %arrayidx = getelementptr inbounds float, float* %ptr.addr.012, i64 %idxprom 1145 %0 = load float, float* %arrayidx, align 4 1146 store float %0, float* %dest.addr.011, align 4 1147 %1 = load float, float* %ptr.addr.012, align 4 1148 %arrayidx5 = getelementptr inbounds float, float* %dest.addr.011, i64 1 1149 store float %1, float* %arrayidx5, align 4 1150 %incdec.ptr = getelementptr inbounds float, float* %ptr.addr.012, i64 1 1151 %add.ptr6 = getelementptr inbounds float, float* %dest.addr.011, i64 16 1152 %cmp.not = icmp eq float* %incdec.ptr, %add.ptr 1153 br i1 %cmp.not, label %for.end, label %for.body 1154 1155for.end: 1156 ret void 1157} 1158