1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -loop-vectorize -S | FileCheck %s 3 4; This is a bugpoint reduction of a test from PR43582: 5; https://bugs.llvm.org/show_bug.cgi?id=43582 6 7; ...but it's over-simplifying the underlying question: 8; TODO: Should this be vectorized rather than allowing the backend to load combine? 9; The original code is a bswap pattern. 10 11target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 12target triple = "x86_64-w64-windows-gnu" 13 14define void @cff_index_load_offsets(i1 %cond, i8 %x, i8* %p) #0 { 15; CHECK-LABEL: @cff_index_load_offsets( 16; CHECK-NEXT: entry: 17; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[EXIT:%.*]] 18; CHECK: if.then: 19; CHECK-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 20; CHECK: vector.ph: 21; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[X:%.*]], i32 0 22; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer 23; CHECK-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i32 0 24; CHECK-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT2]], <4 x i8> poison, <4 x i32> zeroinitializer 25; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 26; CHECK: vector.body: 27; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 28; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 29; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 30; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* null, i64 [[TMP1]] 31; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 4 32; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 4 33; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, i8* null, i64 [[TMP3]] 34; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32> 35; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT3]] to <4 x i32> 36; CHECK-NEXT: [[TMP6:%.*]] = shl nuw <4 x i32> [[TMP4]], <i32 24, i32 24, i32 24, i32 24> 37; CHECK-NEXT: [[TMP7:%.*]] = shl nuw <4 x i32> [[TMP5]], <i32 24, i32 24, i32 24, i32 24> 38; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[P:%.*]], align 1, !tbaa [[TBAA1:![0-9]+]] 39; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x i8> poison, i8 [[TMP8]], i32 0 40; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT4]], <4 x i8> poison, <4 x i32> zeroinitializer 41; CHECK-NEXT: [[TMP9:%.*]] = load i8, i8* [[P]], align 1, !tbaa [[TBAA1]] 42; CHECK-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <4 x i8> poison, i8 [[TMP9]], i32 0 43; CHECK-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT6]], <4 x i8> poison, <4 x i32> zeroinitializer 44; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT5]] to <4 x i32> 45; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT7]] to <4 x i32> 46; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw <4 x i32> [[TMP10]], <i32 16, i32 16, i32 16, i32 16> 47; CHECK-NEXT: [[TMP13:%.*]] = shl nuw nsw <4 x i32> [[TMP11]], <i32 16, i32 16, i32 16, i32 16> 48; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP12]], [[TMP6]] 49; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP13]], [[TMP7]] 50; CHECK-NEXT: [[TMP16:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]] 51; CHECK-NEXT: [[TMP17:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]] 52; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i32> [[TMP14]], zeroinitializer 53; CHECK-NEXT: [[TMP19:%.*]] = or <4 x i32> [[TMP15]], zeroinitializer 54; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i32> [[TMP18]], zeroinitializer 55; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i32> [[TMP19]], zeroinitializer 56; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i32> [[TMP20]], i32 0 57; CHECK-NEXT: store i32 [[TMP22]], i32* undef, align 4, !tbaa [[TBAA4:![0-9]+]] 58; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i32> [[TMP20]], i32 1 59; CHECK-NEXT: store i32 [[TMP23]], i32* undef, align 4, !tbaa [[TBAA4]] 60; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[TMP20]], i32 2 61; CHECK-NEXT: store i32 [[TMP24]], i32* undef, align 4, !tbaa [[TBAA4]] 62; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i32> [[TMP20]], i32 3 63; CHECK-NEXT: store i32 [[TMP25]], i32* undef, align 4, !tbaa [[TBAA4]] 64; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i32> [[TMP21]], i32 0 65; CHECK-NEXT: store i32 [[TMP26]], i32* undef, align 4, !tbaa [[TBAA4]] 66; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP21]], i32 1 67; CHECK-NEXT: store i32 [[TMP27]], i32* undef, align 4, !tbaa [[TBAA4]] 68; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i32> [[TMP21]], i32 2 69; CHECK-NEXT: store i32 [[TMP28]], i32* undef, align 4, !tbaa [[TBAA4]] 70; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> [[TMP21]], i32 3 71; CHECK-NEXT: store i32 [[TMP29]], i32* undef, align 4, !tbaa [[TBAA4]] 72; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 73; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 74; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 75; CHECK: middle.block: 76; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1, 0 77; CHECK-NEXT: br i1 [[CMP_N]], label [[SW_EPILOG:%.*]], label [[SCALAR_PH]] 78; CHECK: scalar.ph: 79; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8* [ null, [[MIDDLE_BLOCK]] ], [ null, [[IF_THEN]] ] 80; CHECK-NEXT: br label [[FOR_BODY68:%.*]] 81; CHECK: for.body68: 82; CHECK-NEXT: [[P_359:%.*]] = phi i8* [ [[ADD_PTR86:%.*]], [[FOR_BODY68]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 83; CHECK-NEXT: [[CONV70:%.*]] = zext i8 [[X]] to i32 84; CHECK-NEXT: [[SHL71:%.*]] = shl nuw i32 [[CONV70]], 24 85; CHECK-NEXT: [[TMP31:%.*]] = load i8, i8* [[P]], align 1, !tbaa [[TBAA1]] 86; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP31]] to i32 87; CHECK-NEXT: [[SHL74:%.*]] = shl nuw nsw i32 [[CONV73]], 16 88; CHECK-NEXT: [[OR75:%.*]] = or i32 [[SHL74]], [[SHL71]] 89; CHECK-NEXT: [[TMP32:%.*]] = load i8, i8* undef, align 1, !tbaa [[TBAA1]] 90; CHECK-NEXT: [[SHL78:%.*]] = shl nuw nsw i32 undef, 8 91; CHECK-NEXT: [[OR79:%.*]] = or i32 [[OR75]], [[SHL78]] 92; CHECK-NEXT: [[CONV81:%.*]] = zext i8 undef to i32 93; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR79]], [[CONV81]] 94; CHECK-NEXT: store i32 [[OR83]], i32* undef, align 4, !tbaa [[TBAA4]] 95; CHECK-NEXT: [[ADD_PTR86]] = getelementptr inbounds i8, i8* [[P_359]], i64 4 96; CHECK-NEXT: [[CMP66:%.*]] = icmp ult i8* [[ADD_PTR86]], undef 97; CHECK-NEXT: br i1 [[CMP66]], label [[FOR_BODY68]], label [[SW_EPILOG]], !llvm.loop [[LOOP8:![0-9]+]] 98; CHECK: sw.epilog: 99; CHECK-NEXT: unreachable 100; CHECK: Exit: 101; CHECK-NEXT: ret void 102; 103entry: 104 br i1 %cond, label %if.then, label %Exit 105 106if.then: ; preds = %entry 107 br label %for.body68 108 109for.body68: ; preds = %for.body68, %if.then 110 %p.359 = phi i8* [ %add.ptr86, %for.body68 ], [ null, %if.then ] 111 %conv70 = zext i8 %x to i32 112 %shl71 = shl nuw i32 %conv70, 24 113 %0 = load i8, i8* %p, align 1, !tbaa !1 114 %conv73 = zext i8 %0 to i32 115 %shl74 = shl nuw nsw i32 %conv73, 16 116 %or75 = or i32 %shl74, %shl71 117 %1 = load i8, i8* undef, align 1, !tbaa !1 118 %shl78 = shl nuw nsw i32 undef, 8 119 %or79 = or i32 %or75, %shl78 120 %conv81 = zext i8 undef to i32 121 %or83 = or i32 %or79, %conv81 122 store i32 %or83, i32* undef, align 4, !tbaa !4 123 %add.ptr86 = getelementptr inbounds i8, i8* %p.359, i64 4 124 %cmp66 = icmp ult i8* %add.ptr86, undef 125 br i1 %cmp66, label %for.body68, label %sw.epilog 126 127sw.epilog: ; preds = %for.body68 128 unreachable 129 130Exit: ; preds = %entry 131 ret void 132} 133 134attributes #0 = { "use-soft-float"="false" } 135 136!llvm.ident = !{!0} 137 138!0 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git 0fedc26a0dc0066f3968b9fea6a4e1f746c8d5a4)"} 139!1 = !{!2, !2, i64 0} 140!2 = !{!"omnipotent char", !3, i64 0} 141!3 = !{!"Simple C/C++ TBAA"} 142!4 = !{!5, !5, i64 0} 143!5 = !{!"long", !2, i64 0} 144