1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -loop-vectorize -S | FileCheck %s 3 4; This is a bugpoint reduction of a test from PR43582: 5; https://bugs.llvm.org/show_bug.cgi?id=43582 6 7; ...but it's over-simplifying the underlying question: 8; TODO: Should this be vectorized rather than allowing the backend to load combine? 9; The original code is a bswap pattern. 10 11target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 12target triple = "x86_64-w64-windows-gnu" 13 14define void @cff_index_load_offsets(i1 %cond, i8 %x, i8* %p) #0 { 15; CHECK-LABEL: @cff_index_load_offsets( 16; CHECK-NEXT: entry: 17; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[EXIT:%.*]] 18; CHECK: if.then: 19; CHECK-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 20; CHECK: vector.ph: 21; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> undef, i8 [[X:%.*]], i32 0 22; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> undef, <4 x i32> zeroinitializer 23; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 24; CHECK: vector.body: 25; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 26; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 27; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 28; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* null, i64 [[TMP1]] 29; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32> 30; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <4 x i32> [[TMP2]], <i32 24, i32 24, i32 24, i32 24> 31; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[P:%.*]], align 1, [[TBAA1:!tbaa !.*]] 32; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i8> undef, i8 [[TMP4]], i32 0 33; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT1]], <4 x i8> undef, <4 x i32> zeroinitializer 34; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT2]] to <4 x i32> 35; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw <4 x i32> [[TMP5]], <i32 16, i32 16, i32 16, i32 16> 36; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i32> [[TMP6]], [[TMP3]] 37; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] 38; CHECK-NEXT: [[TMP9:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] 39; CHECK-NEXT: [[TMP10:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] 40; CHECK-NEXT: [[TMP11:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] 41; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer 42; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP12]], zeroinitializer 43; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[TMP13]], i32 0 44; CHECK-NEXT: store i32 [[TMP14]], i32* undef, align 4, [[TBAA4:!tbaa !.*]] 45; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP13]], i32 1 46; CHECK-NEXT: store i32 [[TMP15]], i32* undef, align 4, [[TBAA4]] 47; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[TMP13]], i32 2 48; CHECK-NEXT: store i32 [[TMP16]], i32* undef, align 4, [[TBAA4]] 49; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP13]], i32 3 50; CHECK-NEXT: store i32 [[TMP17]], i32* undef, align 4, [[TBAA4]] 51; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 52; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 53; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]] 54; CHECK: middle.block: 55; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1, 0 56; CHECK-NEXT: br i1 [[CMP_N]], label [[SW_EPILOG:%.*]], label [[SCALAR_PH]] 57; CHECK: scalar.ph: 58; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8* [ null, [[MIDDLE_BLOCK]] ], [ null, [[IF_THEN]] ] 59; CHECK-NEXT: br label [[FOR_BODY68:%.*]] 60; CHECK: for.body68: 61; CHECK-NEXT: [[P_359:%.*]] = phi i8* [ [[ADD_PTR86:%.*]], [[FOR_BODY68]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 62; CHECK-NEXT: [[CONV70:%.*]] = zext i8 [[X]] to i32 63; CHECK-NEXT: [[SHL71:%.*]] = shl nuw i32 [[CONV70]], 24 64; CHECK-NEXT: [[TMP19:%.*]] = load i8, i8* [[P]], align 1, [[TBAA1]] 65; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP19]] to i32 66; CHECK-NEXT: [[SHL74:%.*]] = shl nuw nsw i32 [[CONV73]], 16 67; CHECK-NEXT: [[OR75:%.*]] = or i32 [[SHL74]], [[SHL71]] 68; CHECK-NEXT: [[TMP20:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] 69; CHECK-NEXT: [[SHL78:%.*]] = shl nuw nsw i32 undef, 8 70; CHECK-NEXT: [[OR79:%.*]] = or i32 [[OR75]], [[SHL78]] 71; CHECK-NEXT: [[CONV81:%.*]] = zext i8 undef to i32 72; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR79]], [[CONV81]] 73; CHECK-NEXT: store i32 [[OR83]], i32* undef, align 4, [[TBAA4]] 74; CHECK-NEXT: [[ADD_PTR86]] = getelementptr inbounds i8, i8* [[P_359]], i64 4 75; CHECK-NEXT: [[CMP66:%.*]] = icmp ult i8* [[ADD_PTR86]], undef 76; CHECK-NEXT: br i1 [[CMP66]], label [[FOR_BODY68]], label [[SW_EPILOG]], [[LOOP8:!llvm.loop !.*]] 77; CHECK: sw.epilog: 78; CHECK-NEXT: unreachable 79; CHECK: Exit: 80; CHECK-NEXT: ret void 81; 82entry: 83 br i1 %cond, label %if.then, label %Exit 84 85if.then: ; preds = %entry 86 br label %for.body68 87 88for.body68: ; preds = %for.body68, %if.then 89 %p.359 = phi i8* [ %add.ptr86, %for.body68 ], [ null, %if.then ] 90 %conv70 = zext i8 %x to i32 91 %shl71 = shl nuw i32 %conv70, 24 92 %0 = load i8, i8* %p, align 1, !tbaa !1 93 %conv73 = zext i8 %0 to i32 94 %shl74 = shl nuw nsw i32 %conv73, 16 95 %or75 = or i32 %shl74, %shl71 96 %1 = load i8, i8* undef, align 1, !tbaa !1 97 %shl78 = shl nuw nsw i32 undef, 8 98 %or79 = or i32 %or75, %shl78 99 %conv81 = zext i8 undef to i32 100 %or83 = or i32 %or79, %conv81 101 store i32 %or83, i32* undef, align 4, !tbaa !4 102 %add.ptr86 = getelementptr inbounds i8, i8* %p.359, i64 4 103 %cmp66 = icmp ult i8* %add.ptr86, undef 104 br i1 %cmp66, label %for.body68, label %sw.epilog 105 106sw.epilog: ; preds = %for.body68 107 unreachable 108 109Exit: ; preds = %entry 110 ret void 111} 112 113attributes #0 = { "use-soft-float"="false" } 114 115!llvm.ident = !{!0} 116 117!0 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git 0fedc26a0dc0066f3968b9fea6a4e1f746c8d5a4)"} 118!1 = !{!2, !2, i64 0} 119!2 = !{!"omnipotent char", !3, i64 0} 120!3 = !{!"Simple C/C++ TBAA"} 121!4 = !{!5, !5, i64 0} 122!5 = !{!"long", !2, i64 0} 123