1; RUN: opt -loop-vectorize -S < %s | FileCheck %s
2
3target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
4target triple = "x86_64-unknown-linux-gnu"
5
6; PR34965/D39346
7
8; LV retains the original scalar loop intact as remainder loop. However,
9; after this transformation, analysis information concerning the remainder
10; loop may differ from the original scalar loop. This test is an example of
11; that behaviour, where values inside the remainder loop which SCEV could
12; originally analyze now require flow-sensitive analysis currently not
13; supported in SCEV. In particular, during LV code generation, after turning
14; the original scalar loop into the remainder loop, LV expected
15; Legal->isConsecutivePtr() to be consistent and return the same output as
16; during legal/cost model phases (original scalar loop). Unfortunately, that
17; condition was not satisfied because of the aforementioned SCEV limitation.
18; After D39346, LV code generation doesn't rely on Legal->isConsecutivePtr(),
19; i.e., SCEV. This test verifies that LV is able to handle the described cases.
20;
21; TODO: The SCEV limitation described before may affect plans to further
22; optimize the remainder loop of this particular test case. One tentative
23; solution is to detect the problematic IVs in LV (%7 and %8) and perform an
24; in-place IV optimization by replacing:
25;   %8 = phi i32 [ %.ph2, %.outer ], [ %7, %6 ] with
26; with
27;   %8 = sub i32 %7, 1.
28
29
30; Verify that store is vectorized as stride-1 memory access.
31
32; CHECK: vector.body:
33; CHECK: store <4 x i32>
34
35; Function Attrs: uwtable
36define void @test() {
37  br label %.outer
38
39; <label>:1:                                      ; preds = %2
40  ret void
41
42; <label>:2:                                      ; preds = %._crit_edge.loopexit
43  %3 = add nsw i32 %.ph, -2
44  br i1 undef, label %1, label %.outer
45
46.outer:                                           ; preds = %2, %0
47  %.ph = phi i32 [ %3, %2 ], [ 336, %0 ]
48  %.ph2 = phi i32 [ 62, %2 ], [ 110, %0 ]
49  %4 = and i32 %.ph, 30
50  %5 = add i32 %.ph2, 1
51  br label %6
52
53; <label>:6:                                      ; preds = %6, %.outer
54  %7 = phi i32 [ %5, %.outer ], [ %13, %6 ]
55  %8 = phi i32 [ %.ph2, %.outer ], [ %7, %6 ]
56  %9 = add i32 %8, 2
57  %10 = zext i32 %9 to i64
58  %11 = getelementptr inbounds i32, i32 addrspace(1)* undef, i64 %10
59  %12 = ashr i32 undef, %4
60  store i32 %12, i32 addrspace(1)* %11, align 4
61  %13 = add i32 %7, 1
62  %14 = icmp sgt i32 %13, 61
63  br i1 %14, label %._crit_edge.loopexit, label %6
64
65._crit_edge.loopexit:                             ; preds = %._crit_edge.loopexit, %6
66  br i1 undef, label %2, label %._crit_edge.loopexit
67}
68
69