1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py 2; This is the loop in c++ being vectorize in this file with 3;experimental.vector.reverse 4; #pragma clang loop vectorize_width(4, scalable) 5; for (int i = N-1; i >= 0; --i) 6; a[i] = b[i] + 1.0; 7 8; REQUIRES: asserts 9; RUN: opt -loop-vectorize -dce -instcombine -mtriple riscv64-linux-gnu \ 10; RUN: -mattr=+v -debug-only=loop-vectorize -scalable-vectorization=on \ 11; RUN: -riscv-v-vector-bits-min=128 -disable-output < %s 2>&1 | FileCheck %s 12 13define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocapture noundef readonly %B, i32 noundef signext %n) { 14; CHECK-LABEL: 'vector_reverse_i64' 15; CHECK-NEXT: LV: Loop hints: force=enabled width=vscale x 4 interleave=0 16; CHECK-NEXT: LV: Found a loop: for.body 17; CHECK-NEXT: LV: Found an induction variable. 18; CHECK-NEXT: LV: Found an induction variable. 19; CHECK-NEXT: LV: Did not find one integer induction var. 20; CHECK-NEXT: LV: We can vectorize this loop (with a runtime bound check)! 21; CHECK-NEXT: LV: Found trip count: 0 22; CHECK-NEXT: LV: Scalable vectorization is available 23; CHECK-NEXT: LV: The max safe fixed VF is: 67108864. 24; CHECK-NEXT: LV: The max safe scalable VF is: vscale x 4294967295. 25; CHECK-NEXT: LV: Found uniform instruction: %cmp = icmp ugt i64 %indvars.iv, 1 26; CHECK-NEXT: LV: Found uniform instruction: %arrayidx = getelementptr inbounds i32, ptr %B, i64 %idxprom 27; CHECK-NEXT: LV: Found uniform instruction: %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %idxprom 28; CHECK-NEXT: LV: Found uniform instruction: %idxprom = zext i32 %i.0 to i64 29; CHECK-NEXT: LV: Found uniform instruction: %idxprom = zext i32 %i.0 to i64 30; CHECK-NEXT: LV: Found uniform instruction: %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 31; CHECK-NEXT: LV: Found uniform instruction: %indvars.iv.next = add nsw i64 %indvars.iv, -1 32; CHECK-NEXT: LV: Found uniform instruction: %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 33; CHECK-NEXT: LV: Found uniform instruction: %i.0 = add nsw i32 %i.0.in8, -1 34; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 35; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 36; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0 = add nsw i32 %i.0.in8, -1 37; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %idxprom = zext i32 %i.0 to i64 38; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx = getelementptr inbounds i32, ptr %B, i64 %idxprom 39; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: %1 = load i32, ptr %arrayidx, align 4 40; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %add9 = add i32 %1, 1 41; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %idxprom 42; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: store i32 %add9, ptr %arrayidx3, align 4 43; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %cmp = icmp ugt i64 %indvars.iv, 1 44; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv.next = add nsw i64 %indvars.iv, -1 45; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit, !llvm.loop !0 46; CHECK-NEXT: LV: Using user VF vscale x 4. 47; CHECK-NEXT: LV: Scalarizing: %i.0 = add nsw i32 %i.0.in8, -1 48; CHECK-NEXT: LV: Scalarizing: %idxprom = zext i32 %i.0 to i64 49; CHECK-NEXT: LV: Scalarizing: %arrayidx = getelementptr inbounds i32, ptr %B, i64 %idxprom 50; CHECK-NEXT: LV: Scalarizing: %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %idxprom 51; CHECK-NEXT: VPlan 'Initial VPlan for VF={vscale x 4},UF>=1' { 52; CHECK-NEXT: Live-in vp<%2> = vector-trip-count 53; CHECK: vector.ph: 54; CHECK-NEXT: Successor(s): vector loop 55; CHECK: <x1> vector loop: { 56; CHECK-NEXT: vector.body: 57; CHECK-NEXT: EMIT vp<%3> = CANONICAL-INDUCTION 58; CHECK-NEXT: vp<%4> = SCALAR-STEPS vp<%3>, ir<%n>, ir<-1> 59; CHECK-NEXT: CLONE ir<%i.0> = add vp<%4>, ir<-1> 60; CHECK-NEXT: CLONE ir<%idxprom> = zext ir<%i.0> 61; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%B>, ir<%idxprom> 62; CHECK-NEXT: WIDEN ir<%1> = load ir<%arrayidx> 63; CHECK-NEXT: WIDEN ir<%add9> = add ir<%1>, ir<1> 64; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr ir<%A>, ir<%idxprom> 65; CHECK-NEXT: WIDEN store ir<%arrayidx3>, ir<%add9> 66; CHECK-NEXT: EMIT vp<%11> = VF * UF +(nuw) vp<%3> 67; CHECK-NEXT: EMIT branch-on-count vp<%11> vp<%2> 68; CHECK-NEXT: No successors 69; CHECK-NEXT: } 70; CHECK-NEXT: Successor(s): middle.block 71; CHECK: middle.block: 72; CHECK-NEXT: No successors 73; CHECK-NEXT: } 74; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 75; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 76; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0 = add nsw i32 %i.0.in8, -1 77; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %idxprom = zext i32 %i.0 to i64 78; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx = getelementptr inbounds i32, ptr %B, i64 %idxprom 79; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: %1 = load i32, ptr %arrayidx, align 4 80; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %add9 = add i32 %1, 1 81; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %idxprom 82; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: store i32 %add9, ptr %arrayidx3, align 4 83; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %cmp = icmp ugt i64 %indvars.iv, 1 84; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv.next = add nsw i64 %indvars.iv, -1 85; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit, !llvm.loop !0 86; CHECK-NEXT: LV(REG): Calculating max register usage: 87; CHECK-NEXT: LV(REG): At #0 Interval # 0 88; CHECK-NEXT: LV(REG): At #1 Interval # 1 89; CHECK-NEXT: LV(REG): At #2 Interval # 2 90; CHECK-NEXT: LV(REG): At #3 Interval # 2 91; CHECK-NEXT: LV(REG): At #4 Interval # 2 92; CHECK-NEXT: LV(REG): At #5 Interval # 3 93; CHECK-NEXT: LV(REG): At #6 Interval # 3 94; CHECK-NEXT: LV(REG): At #7 Interval # 3 95; CHECK-NEXT: LV(REG): At #9 Interval # 1 96; CHECK-NEXT: LV(REG): At #10 Interval # 2 97; CHECK-NEXT: LV(REG): VF = vscale x 4 98; CHECK-NEXT: LV(REG): Found max usage: 2 item 99; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers 100; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers 101; CHECK-NEXT: LV(REG): Found invariant usage: 1 item 102; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers 103; CHECK-NEXT: LV: The target has 31 registers of RISCV::GPRRC register class 104; CHECK-NEXT: LV: The target has 32 registers of RISCV::VRRC register class 105; CHECK-NEXT: LV: Loop cost is 22 106; CHECK-NEXT: LV: IC is 2 107; CHECK-NEXT: LV: VF is vscale x 4 108; CHECK-NEXT: LV: Not Interleaving. 109; CHECK-NEXT: LV: Interleaving is not beneficial. 110; CHECK-NEXT: LV: Found a vectorizable loop (vscale x 4) in <stdin> 111; CHECK-NEXT: LEV: Epilogue vectorization is not profitable for this loop 112; CHECK-NEXT: Executing best plan with VF=vscale x 4, UF=1 113; CHECK-NEXT: LV: Interleaving disabled by the pass manager 114; 115entry: 116 %cmp7 = icmp sgt i32 %n, 0 117 br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup 118 119for.body.preheader: ; preds = %entry 120 %0 = zext i32 %n to i64 121 br label %for.body 122 123for.cond.cleanup: ; preds = %for.body, %entry 124 ret void 125 126for.body: ; preds = %for.body.preheader, %for.body 127 %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 128 %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 129 %i.0 = add nsw i32 %i.0.in8, -1 130 %idxprom = zext i32 %i.0 to i64 131 %arrayidx = getelementptr inbounds i32, ptr %B, i64 %idxprom 132 %1 = load i32, ptr %arrayidx, align 4 133 %add9 = add i32 %1, 1 134 %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %idxprom 135 store i32 %add9, ptr %arrayidx3, align 4 136 %cmp = icmp ugt i64 %indvars.iv, 1 137 %indvars.iv.next = add nsw i64 %indvars.iv, -1 138 br i1 %cmp, label %for.body, label %for.cond.cleanup, !llvm.loop !0 139} 140 141define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocapture noundef readonly %B, i32 noundef signext %n) { 142; CHECK-LABEL: 'vector_reverse_f32' 143; CHECK-NEXT: LV: Loop hints: force=enabled width=vscale x 4 interleave=0 144; CHECK-NEXT: LV: Found a loop: for.body 145; CHECK-NEXT: LV: Found an induction variable. 146; CHECK-NEXT: LV: Found an induction variable. 147; CHECK-NEXT: LV: Found FP op with unsafe algebra. 148; CHECK-NEXT: LV: Did not find one integer induction var. 149; CHECK-NEXT: LV: We can vectorize this loop (with a runtime bound check)! 150; CHECK-NEXT: LV: Found trip count: 0 151; CHECK-NEXT: LV: Scalable vectorization is available 152; CHECK-NEXT: LV: The max safe fixed VF is: 67108864. 153; CHECK-NEXT: LV: The max safe scalable VF is: vscale x 4294967295. 154; CHECK-NEXT: LV: Found uniform instruction: %cmp = icmp ugt i64 %indvars.iv, 1 155; CHECK-NEXT: LV: Found uniform instruction: %arrayidx = getelementptr inbounds float, ptr %B, i64 %idxprom 156; CHECK-NEXT: LV: Found uniform instruction: %arrayidx3 = getelementptr inbounds float, ptr %A, i64 %idxprom 157; CHECK-NEXT: LV: Found uniform instruction: %idxprom = zext i32 %i.0 to i64 158; CHECK-NEXT: LV: Found uniform instruction: %idxprom = zext i32 %i.0 to i64 159; CHECK-NEXT: LV: Found uniform instruction: %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 160; CHECK-NEXT: LV: Found uniform instruction: %indvars.iv.next = add nsw i64 %indvars.iv, -1 161; CHECK-NEXT: LV: Found uniform instruction: %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 162; CHECK-NEXT: LV: Found uniform instruction: %i.0 = add nsw i32 %i.0.in8, -1 163; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 164; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 165; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0 = add nsw i32 %i.0.in8, -1 166; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %idxprom = zext i32 %i.0 to i64 167; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx = getelementptr inbounds float, ptr %B, i64 %idxprom 168; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: %1 = load float, ptr %arrayidx, align 4 169; CHECK-NEXT: LV: Found an estimated cost of 2 for VF vscale x 4 For instruction: %conv1 = fadd float %1, 1.000000e+00 170; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx3 = getelementptr inbounds float, ptr %A, i64 %idxprom 171; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: store float %conv1, ptr %arrayidx3, align 4 172; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %cmp = icmp ugt i64 %indvars.iv, 1 173; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv.next = add nsw i64 %indvars.iv, -1 174; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit, !llvm.loop !0 175; CHECK-NEXT: LV: Using user VF vscale x 4. 176; CHECK-NEXT: LV: Scalarizing: %i.0 = add nsw i32 %i.0.in8, -1 177; CHECK-NEXT: LV: Scalarizing: %idxprom = zext i32 %i.0 to i64 178; CHECK-NEXT: LV: Scalarizing: %arrayidx = getelementptr inbounds float, ptr %B, i64 %idxprom 179; CHECK-NEXT: LV: Scalarizing: %arrayidx3 = getelementptr inbounds float, ptr %A, i64 %idxprom 180; CHECK-NEXT: VPlan 'Initial VPlan for VF={vscale x 4},UF>=1' { 181; CHECK-NEXT: Live-in vp<%2> = vector-trip-count 182; CHECK: vector.ph: 183; CHECK-NEXT: Successor(s): vector loop 184; CHECK: <x1> vector loop: { 185; CHECK-NEXT: vector.body: 186; CHECK-NEXT: EMIT vp<%3> = CANONICAL-INDUCTION 187; CHECK-NEXT: vp<%4> = SCALAR-STEPS vp<%3>, ir<%n>, ir<-1> 188; CHECK-NEXT: CLONE ir<%i.0> = add vp<%4>, ir<-1> 189; CHECK-NEXT: CLONE ir<%idxprom> = zext ir<%i.0> 190; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%B>, ir<%idxprom> 191; CHECK-NEXT: WIDEN ir<%1> = load ir<%arrayidx> 192; CHECK-NEXT: WIDEN ir<%conv1> = fadd ir<%1>, ir<1.000000e+00> 193; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr ir<%A>, ir<%idxprom> 194; CHECK-NEXT: WIDEN store ir<%arrayidx3>, ir<%conv1> 195; CHECK-NEXT: EMIT vp<%11> = VF * UF +(nuw) vp<%3> 196; CHECK-NEXT: EMIT branch-on-count vp<%11> vp<%2> 197; CHECK-NEXT: No successors 198; CHECK-NEXT: } 199; CHECK-NEXT: Successor(s): middle.block 200; CHECK: middle.block: 201; CHECK-NEXT: No successors 202; CHECK-NEXT: } 203; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 204; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 205; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %i.0 = add nsw i32 %i.0.in8, -1 206; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %idxprom = zext i32 %i.0 to i64 207; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx = getelementptr inbounds float, ptr %B, i64 %idxprom 208; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: %1 = load float, ptr %arrayidx, align 4 209; CHECK-NEXT: LV: Found an estimated cost of 2 for VF vscale x 4 For instruction: %conv1 = fadd float %1, 1.000000e+00 210; CHECK-NEXT: LV: Found an estimated cost of 0 for VF vscale x 4 For instruction: %arrayidx3 = getelementptr inbounds float, ptr %A, i64 %idxprom 211; CHECK-NEXT: LV: Found an estimated cost of 7 for VF vscale x 4 For instruction: store float %conv1, ptr %arrayidx3, align 4 212; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %cmp = icmp ugt i64 %indvars.iv, 1 213; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: %indvars.iv.next = add nsw i64 %indvars.iv, -1 214; CHECK-NEXT: LV: Found an estimated cost of 1 for VF vscale x 4 For instruction: br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit, !llvm.loop !0 215; CHECK-NEXT: LV(REG): Calculating max register usage: 216; CHECK-NEXT: LV(REG): At #0 Interval # 0 217; CHECK-NEXT: LV(REG): At #1 Interval # 1 218; CHECK-NEXT: LV(REG): At #2 Interval # 2 219; CHECK-NEXT: LV(REG): At #3 Interval # 2 220; CHECK-NEXT: LV(REG): At #4 Interval # 2 221; CHECK-NEXT: LV(REG): At #5 Interval # 3 222; CHECK-NEXT: LV(REG): At #6 Interval # 3 223; CHECK-NEXT: LV(REG): At #7 Interval # 3 224; CHECK-NEXT: LV(REG): At #9 Interval # 1 225; CHECK-NEXT: LV(REG): At #10 Interval # 2 226; CHECK-NEXT: LV(REG): VF = vscale x 4 227; CHECK-NEXT: LV(REG): Found max usage: 2 item 228; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers 229; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers 230; CHECK-NEXT: LV(REG): Found invariant usage: 1 item 231; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers 232; CHECK-NEXT: LV: The target has 31 registers of RISCV::GPRRC register class 233; CHECK-NEXT: LV: The target has 32 registers of RISCV::VRRC register class 234; CHECK-NEXT: LV: Loop cost is 23 235; CHECK-NEXT: LV: IC is 2 236; CHECK-NEXT: LV: VF is vscale x 4 237; CHECK-NEXT: LV: Not Interleaving. 238; CHECK-NEXT: LV: Interleaving is not beneficial. 239; CHECK-NEXT: LV: Found a vectorizable loop (vscale x 4) in <stdin> 240; CHECK-NEXT: LEV: Epilogue vectorization is not profitable for this loop 241; CHECK-NEXT: Executing best plan with VF=vscale x 4, UF=1 242; CHECK-NEXT: LV: Interleaving disabled by the pass manager 243; 244entry: 245 %cmp7 = icmp sgt i32 %n, 0 246 br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup 247 248for.body.preheader: ; preds = %entry 249 %0 = zext i32 %n to i64 250 br label %for.body 251 252for.cond.cleanup: ; preds = %for.body, %entry 253 ret void 254 255for.body: ; preds = %for.body.preheader, %for.body 256 %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] 257 %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ] 258 %i.0 = add nsw i32 %i.0.in8, -1 259 %idxprom = zext i32 %i.0 to i64 260 %arrayidx = getelementptr inbounds float, ptr %B, i64 %idxprom 261 %1 = load float, ptr %arrayidx, align 4 262 %conv1 = fadd float %1, 1.000000e+00 263 %arrayidx3 = getelementptr inbounds float, ptr %A, i64 %idxprom 264 store float %conv1, ptr %arrayidx3, align 4 265 %cmp = icmp ugt i64 %indvars.iv, 1 266 %indvars.iv.next = add nsw i64 %indvars.iv, -1 267 br i1 %cmp, label %for.body, label %for.cond.cleanup, !llvm.loop !0 268} 269 270!0 = distinct !{!0, !1, !2, !3, !4} 271!1 = !{!"llvm.loop.mustprogress"} 272!2 = !{!"llvm.loop.vectorize.width", i32 4} 273!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true} 274!4 = !{!"llvm.loop.vectorize.enable", i1 true} 275