1; REQUIRES: asserts
2; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
3; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
4; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=1 \
5; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL1
6; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
7; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
8; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=2 \
9; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL2
10; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
11; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
12; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=4 \
13; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL4
14; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
15; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
16; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=8 \
17; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL8
18
19define void @add(float* noalias nocapture readonly %src1, float* noalias nocapture readonly %src2, i32 signext %size, float* noalias nocapture writeonly %result) {
20; CHECK-LABEL: add
21; CHECK-LMUL1:      LV(REG): Found max usage: 2 item
22; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
23; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 2 registers
24; CHECK-LMUL1-NEXT: LV(REG): Found invariant usage: 1 item
25; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 2 registers
26; CHECK-LMUL2:      LV(REG): Found max usage: 2 item
27; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
28; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 4 registers
29; CHECK-LMUL2-NEXT: LV(REG): Found invariant usage: 1 item
30; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 4 registers
31; CHECK-LMUL4:      LV(REG): Found max usage: 2 item
32; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
33; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers
34; CHECK-LMUL4-NEXT: LV(REG): Found invariant usage: 1 item
35; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers
36; CHECK-LMUL8:      LV(REG): Found max usage: 2 item
37; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
38; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 16 registers
39; CHECK-LMUL8-NEXT: LV(REG): Found invariant usage: 1 item
40; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 16 registers
41
42entry:
43  %conv = zext i32 %size to i64
44  %cmp10.not = icmp eq i32 %size, 0
45  br i1 %cmp10.not, label %for.cond.cleanup, label %for.body
46
47for.cond.cleanup:
48  ret void
49
50for.body:
51  %i.011 = phi i64 [ %add4, %for.body ], [ 0, %entry ]
52  %arrayidx = getelementptr inbounds float, float* %src1, i64 %i.011
53  %0 = load float, float* %arrayidx, align 4
54  %arrayidx2 = getelementptr inbounds float, float* %src2, i64 %i.011
55  %1 = load float, float* %arrayidx2, align 4
56  %add = fadd float %0, %1
57  %arrayidx3 = getelementptr inbounds float, float* %result, i64 %i.011
58  store float %add, float* %arrayidx3, align 4
59  %add4 = add nuw nsw i64 %i.011, 1
60  %exitcond.not = icmp eq i64 %add4, %conv
61  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
62}
63