1; RUN: opt -mtriple aarch64-linux-gnu -mattr=+sve -loop-vectorize -scalable-vectorization=on -dce -instcombine -S < %s | FileCheck %s 2 3; Ensure that we can vectorize loops such as: 4; int *ptr = c; 5; for (long long i = 0; i < n; i++) { 6; int X1 = *ptr++; 7; int X2 = *ptr++; 8; a[i] = X1 + 1; 9; b[i] = X2 + 1; 10; } 11; with scalable vectors, including unrolling. The test below makes sure 12; that we can use gather instructions with the correct offsets, taking 13; vscale into account. 14 15define void @widen_ptr_phi_unrolled(i32* noalias nocapture %a, i32* noalias nocapture %b, i32* nocapture readonly %c, i64 %n) #0 { 16; CHECK-LABEL: @widen_ptr_phi_unrolled( 17; CHECK: vector.body: 18; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi i32* [ %c, %vector.ph ], [ %[[PTR_IND:.*]], %vector.body ] 19; CHECK: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() 20; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[TMP5]], 2 21; CHECK-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 4 22; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() 23; CHECK-NEXT: [[VECTOR_GEP:%.*]] = shl <vscale x 4 x i64> [[TMP8]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer) 24; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, i32* [[POINTER_PHI]], <vscale x 4 x i64> [[VECTOR_GEP]] 25; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP6]], i32 0 26; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <vscale x 4 x i64> [[DOTSPLATINSERT2]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 27; CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() 28; CHECK-NEXT: [[TMP11:%.*]] = add <vscale x 4 x i64> [[DOTSPLAT3]], [[TMP10]] 29; CHECK-NEXT: [[VECTOR_GEP4:%.*]] = shl <vscale x 4 x i64> [[TMP11]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer) 30; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[POINTER_PHI]], <vscale x 4 x i64> [[VECTOR_GEP4]] 31; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, <vscale x 4 x i32*> [[TMP9]], i64 1 32; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, <vscale x 4 x i32*> [[TMP12]], i64 1 33; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP9]], 34; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP12]], 35; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP13]], 36; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP14]], 37; CHECK: [[PTR_IND]] = getelementptr i32, i32* [[POINTER_PHI]], i64 [[TMP7]] 38entry: 39 br label %for.body 40 41for.body: ; preds = %entry, %for.body 42 %ptr.014 = phi i32* [ %incdec.ptr1, %for.body ], [ %c, %entry ] 43 %i.013 = phi i64 [ %inc, %for.body ], [ 0, %entry ] 44 %incdec.ptr = getelementptr inbounds i32, i32* %ptr.014, i64 1 45 %0 = load i32, i32* %ptr.014, align 4 46 %incdec.ptr1 = getelementptr inbounds i32, i32* %ptr.014, i64 2 47 %1 = load i32, i32* %incdec.ptr, align 4 48 %add = add nsw i32 %0, 1 49 %arrayidx = getelementptr inbounds i32, i32* %a, i64 %i.013 50 store i32 %add, i32* %arrayidx, align 4 51 %add2 = add nsw i32 %1, 1 52 %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %i.013 53 store i32 %add2, i32* %arrayidx3, align 4 54 %inc = add nuw nsw i64 %i.013, 1 55 %exitcond.not = icmp eq i64 %inc, %n 56 br i1 %exitcond.not, label %for.exit, label %for.body, !llvm.loop !0 57 58for.exit: ; preds = %for.body 59 ret void 60} 61 62 63; Ensure we can vectorise loops without interleaving, e.g.: 64; int *D = dst; 65; int *S = src; 66; for (long long i = 0; i < n; i++) { 67; *D = *S * 2; 68; D++; 69; S++; 70; } 71; This takes us down a different codepath to the test above, where 72; here we treat the PHIs as being uniform. 73 74define void @widen_2ptrs_phi_unrolled(i32* noalias nocapture %dst, i32* noalias nocapture readonly %src, i64 %n) #0 { 75; CHECK-LABEL: @widen_2ptrs_phi_unrolled( 76; CHECK: vector.body: 77; CHECK-NEXT: %[[IDX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ] 78; CHECK-NEXT: %[[LGEP1:.*]] = getelementptr i32, i32* %src, i64 %[[IDX]] 79; CHECK-NEXT: %[[SGEP1:.*]] = getelementptr i32, i32* %dst, i64 %[[IDX]] 80; CHECK-NEXT: %[[LPTR1:.*]] = bitcast i32* %[[LGEP1]] to <vscale x 4 x i32>* 81; CHECK-NEXT: %{{.*}} = load <vscale x 4 x i32>, <vscale x 4 x i32>* %[[LPTR1]], align 4 82; CHECK-NEXT: %[[VSCALE1:.*]] = call i32 @llvm.vscale.i32() 83; CHECK-NEXT: %[[TMP1:.*]] = shl nuw nsw i32 %[[VSCALE1]], 2 84; CHECK-NEXT: %[[TMP2:.*]] = zext i32 %[[TMP1]] to i64 85; CHECK-NEXT: %[[LGEP2:.*]] = getelementptr i32, i32* %[[LGEP1]], i64 %[[TMP2]] 86; CHECK-NEXT: %[[LPTR2:.*]] = bitcast i32* %[[LGEP2]] to <vscale x 4 x i32>* 87; CHECK-NEXT: %{{.*}} = load <vscale x 4 x i32>, <vscale x 4 x i32>* %[[LPTR2]], align 4 88; CHECK: %[[SPTR1:.*]] = bitcast i32* %[[SGEP1]] to <vscale x 4 x i32>* 89; CHECK-NEXT: store <vscale x 4 x i32> %{{.*}}, <vscale x 4 x i32>* %[[SPTR1]], align 4 90; CHECK-NEXT: %[[VSCALE2:.*]] = call i32 @llvm.vscale.i32() 91; CHECK-NEXT: %[[TMP3:.*]] = shl nuw nsw i32 %[[VSCALE2]], 2 92; CHECK-NEXT: %[[TMP4:.*]] = zext i32 %[[TMP3]] to i64 93; CHECK-NEXT: %[[SGEP2:.*]] = getelementptr i32, i32* %[[SGEP1]], i64 %[[TMP4]] 94; CHECK-NEXT: %[[SPTR2:.*]] = bitcast i32* %[[SGEP2]] to <vscale x 4 x i32>* 95; CHECK-NEXT: store <vscale x 4 x i32> %{{.*}}, <vscale x 4 x i32>* %[[SPTR2]], align 4 96 97entry: 98 br label %for.body 99 100for.body: ; preds = %entry, %for.body 101 %i.011 = phi i64 [ %inc, %for.body ], [ 0, %entry ] 102 %S.010 = phi i32* [ %incdec.ptr1, %for.body ], [ %src, %entry ] 103 %D.09 = phi i32* [ %incdec.ptr, %for.body ], [ %dst, %entry ] 104 %0 = load i32, i32* %S.010, align 4 105 %mul = shl nsw i32 %0, 1 106 store i32 %mul, i32* %D.09, align 4 107 %incdec.ptr = getelementptr inbounds i32, i32* %D.09, i64 1 108 %incdec.ptr1 = getelementptr inbounds i32, i32* %S.010, i64 1 109 %inc = add nuw nsw i64 %i.011, 1 110 %exitcond.not = icmp eq i64 %inc, %n 111 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !0 112 113for.cond.cleanup: ; preds = %for.body 114 ret void 115} 116 117 118; 119; Check multiple pointer induction variables where only one is recognized as 120; uniform and remains uniform after vectorization. The other pointer induction 121; variable is not recognized as uniform and is not uniform after vectorization 122; because it is stored to memory. 123; 124 125define i32 @pointer_iv_mixed(i32* noalias %a, i32** noalias %b, i64 %n) #0 { 126; CHECK-LABEL: @pointer_iv_mixed( 127; CHECK: vector.body 128; CHECK: %[[IDX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ] 129; CHECK: %[[STEPVEC:.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64() 130; CHECK-NEXT: %[[TMP1:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[IDX]], i32 0 131; CHECK-NEXT: %[[TMP2:.*]] = shufflevector <vscale x 2 x i64> %[[TMP1]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 132; CHECK-NEXT: %[[VECIND1:.*]] = add <vscale x 2 x i64> %[[TMP2]], %[[STEPVEC]] 133; CHECK-NEXT: %[[APTRS1:.*]] = getelementptr i32, i32* %a, <vscale x 2 x i64> %[[VECIND1]] 134; CHECK-NEXT: %[[GEPA1:.*]] = getelementptr i32, i32* %a, i64 %[[IDX]] 135; CHECK-NEXT: %[[VSCALE64:.*]] = call i64 @llvm.vscale.i64() 136; CHECK-NEXT: %[[VSCALE64X2:.*]] = shl nuw nsw i64 %[[VSCALE64]], 1 137; CHECK-NEXT: %[[TMP3:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[VSCALE64X2]], i32 0 138; CHECK-NEXT: %[[TMP4:.*]] = shufflevector <vscale x 2 x i64> %[[TMP3]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 139; CHECK-NEXT: %[[TMP5:.*]] = add <vscale x 2 x i64> %[[TMP4]], %[[STEPVEC]] 140; CHECK-NEXT: %[[VECIND2:.*]] = add <vscale x 2 x i64> %[[TMP2]], %[[TMP5]] 141; CHECK-NEXT: %[[APTRS2:.*]] = getelementptr i32, i32* %a, <vscale x 2 x i64> %[[VECIND2]] 142; CHECK-NEXT: %[[GEPB1:.*]] = getelementptr i32*, i32** %b, i64 %[[IDX]] 143; The following checks that there is no extractelement after 144; vectorization when the stepvector has multiple uses, which demonstrates 145; the removal of a redundant fmov instruction in the generated asm code. 146; CHECK-NOT: %[[EXTRACT:.*]] = extractelement <vscale x 2 x i32*> [[APTRS1]], i32 0 147; CHECK: %[[BPTR1:.*]] = bitcast i32** %[[GEPB1]] to <vscale x 2 x i32*>* 148; CHECK-NEXT: store <vscale x 2 x i32*> %[[APTRS1]], <vscale x 2 x i32*>* %[[BPTR1]], align 8 149; CHECK: %[[VSCALE32:.*]] = call i32 @llvm.vscale.i32() 150; CHECK-NEXT: %[[VSCALE32X2:.*]] = shl nuw nsw i32 %[[VSCALE32]], 1 151; CHECK-NEXT: %[[TMP6:.*]] = zext i32 %[[VSCALE32X2]] to i64 152; CHECK-NEXT: %[[GEPB2:.*]] = getelementptr i32*, i32** %[[GEPB1]], i64 %[[TMP6]] 153; CHECK-NEXT: %[[BPTR2:.*]] = bitcast i32** %[[GEPB2]] to <vscale x 2 x i32*>* 154; CHECK-NEXT store <vscale x 2 x i32*> %[[APTRS2]], <vscale x 2 x i32*>* %[[BPTR2]], align 8 155 156entry: 157 br label %for.body 158 159for.body: 160 %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] 161 %p = phi i32* [ %tmp3, %for.body ], [ %a, %entry ] 162 %q = phi i32** [ %tmp4, %for.body ], [ %b, %entry ] 163 %tmp0 = phi i32 [ %tmp2, %for.body ], [ 0, %entry ] 164 %tmp1 = load i32, i32* %p, align 8 165 %tmp2 = add i32 %tmp1, %tmp0 166 store i32* %p, i32** %q, align 8 167 %tmp3 = getelementptr inbounds i32, i32* %p, i32 1 168 %tmp4 = getelementptr inbounds i32*, i32** %q, i32 1 169 %i.next = add nuw nsw i64 %i, 1 170 %cond = icmp slt i64 %i.next, %n 171 br i1 %cond, label %for.body, label %for.end, !llvm.loop !6 172 173for.end: 174 %tmp5 = phi i32 [ %tmp2, %for.body ] 175 ret i32 %tmp5 176} 177 178attributes #0 = { vscale_range(0, 16) } 179!0 = distinct !{!0, !1, !2, !3, !4, !5} 180!1 = !{!"llvm.loop.mustprogress"} 181!2 = !{!"llvm.loop.vectorize.width", i32 4} 182!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true} 183!4 = !{!"llvm.loop.vectorize.enable", i1 true} 184!5 = !{!"llvm.loop.interleave.count", i32 2} 185!6 = distinct !{!6, !1, !7, !3, !4, !5} 186!7 = !{!"llvm.loop.vectorize.width", i32 2} 187