1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; REQUIRES: asserts 3; RUN: opt -S -loop-vectorize -debug-only=loop-vectorize < %s 2>%t | FileCheck %s 4; RUN: cat %t | FileCheck %s --check-prefix=VPLANS 5 6; These tests ensure that tail-folding is enabled when the predicate.enable 7; loop attribute is set to true. 8 9target triple = "aarch64-unknown-linux-gnu" 10 11; VPLANS-LABEL: Checking a loop in 'simple_memset' 12; VPLANS: VPlan 'Initial VPlan for VF={vscale x 1,vscale x 2,vscale x 4},UF>=1' { 13; VPLANS-NEXT: vector.ph: 14; VPLANS-NEXT: EMIT vp<%2> = VF * Part + ir<0> 15; VPLANS-NEXT: EMIT vp<%3> = active lane mask vp<%2> <badref> 16; VPLANS-NEXT: Successor(s): vector loop 17; VPLANS-EMPTY: 18; VPLANS-NEXT: <x1> vector loop: { 19; VPLANS-NEXT: vector.body: 20; VPLANS-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION 21; VPLANS-NEXT: ACTIVE-LANE-MASK-PHI vp<%5> = phi vp<%3>, vp<%10> 22; VPLANS-NEXT: vp<%6> = SCALAR-STEPS vp<%4>, ir<0>, ir<1> 23; VPLANS-NEXT: CLONE ir<%gep> = getelementptr ir<%ptr>, vp<%6> 24; VPLANS-NEXT: WIDEN store ir<%gep>, ir<%val>, vp<%5> 25; VPLANS-NEXT: EMIT vp<%8> = VF * UF + vp<%4> 26; VPLANS-NEXT: EMIT vp<%9> = VF * Part + vp<%8> 27; VPLANS-NEXT: EMIT vp<%10> = active lane mask vp<%9> <badref> 28; VPLANS-NEXT: EMIT vp<%11> = not vp<%10> 29; VPLANS-NEXT: EMIT branch-on-cond vp<%11> 30; VPLANS-NEXT: No successors 31; VPLANS-NEXT: } 32 33define void @simple_memset(i32 %val, i32* %ptr, i64 %n) #0 { 34; CHECK-LABEL: @simple_memset( 35; CHECK-NEXT: entry: 36; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1) 37; CHECK-NEXT: [[TMP2:%.*]] = sub i64 -1, [[UMAX]] 38; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 39; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 40; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], [[TMP1]] 41; CHECK-NEXT: br i1 [[TMP3]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 42; CHECK: vector.ph: 43; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() 44; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4 45; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() 46; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 4 47; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP7]], 1 48; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], [[TMP8]] 49; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]] 50; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] 51; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[UMAX]]) 52; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i32 0 53; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 54; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 55; CHECK: vector.body: 56; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VECTOR_BODY]] ] 57; CHECK-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK4:%.*]], [[VECTOR_BODY]] ] 58; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX1]], 0 59; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, i32* [[PTR:%.*]], i64 [[TMP9]] 60; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[TMP10]], i32 0 61; CHECK-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP11]] to <vscale x 4 x i32>* 62; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> [[BROADCAST_SPLAT]], <vscale x 4 x i32>* [[TMP12]], i32 4, <vscale x 4 x i1> [[ACTIVE_LANE_MASK2]]) 63; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64() 64; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 4 65; CHECK-NEXT: [[INDEX_NEXT3]] = add i64 [[INDEX1]], [[TMP14]] 66; CHECK-NEXT: [[ACTIVE_LANE_MASK4]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX_NEXT3]], i64 [[UMAX]]) 67; CHECK-NEXT: [[TMP15:%.*]] = xor <vscale x 4 x i1> [[ACTIVE_LANE_MASK4]], shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i32 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer) 68; CHECK-NEXT: [[TMP16:%.*]] = extractelement <vscale x 4 x i1> [[TMP15]], i32 0 69; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 70; CHECK: middle.block: 71; CHECK-NEXT: br i1 true, label [[WHILE_END_LOOPEXIT:%.*]], label [[SCALAR_PH]] 72; 73entry: 74 br label %while.body 75 76while.body: ; preds = %while.body, %entry 77 %index = phi i64 [ %index.next, %while.body ], [ 0, %entry ] 78 %gep = getelementptr i32, i32* %ptr, i64 %index 79 store i32 %val, i32* %gep 80 %index.next = add nsw i64 %index, 1 81 %cmp10 = icmp ult i64 %index.next, %n 82 br i1 %cmp10, label %while.body, label %while.end.loopexit, !llvm.loop !0 83 84while.end.loopexit: ; preds = %while.body 85 ret void 86} 87 88 89attributes #0 = { "target-features"="+sve" } 90 91!0 = distinct !{!0, !1} 92!1 = !{!"llvm.loop.vectorize.predicate.enable", i1 true} 93