1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes=loop-vectorize -mattr=+sve -S %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6; Test case where the minimum profitable trip count due to runtime checks
7; exceeds VF.getKnownMinValue() * UF.
8; FIXME: The code currently incorrectly is missing a umax(VF * UF, 28).
9define void @min_trip_count_due_to_runtime_checks_1(ptr %dst.1, ptr %dst.2, ptr %src.1, ptr %src.2, i64 %n) {
10; CHECK-LABEL: @min_trip_count_due_to_runtime_checks_1(
11; CHECK-NEXT:  entry:
12; CHECK-NEXT:    [[SRC_25:%.*]] = ptrtoint ptr [[SRC_2:%.*]] to i64
13; CHECK-NEXT:    [[SRC_13:%.*]] = ptrtoint ptr [[SRC_1:%.*]] to i64
14; CHECK-NEXT:    [[DST_12:%.*]] = ptrtoint ptr [[DST_1:%.*]] to i64
15; CHECK-NEXT:    [[DST_21:%.*]] = ptrtoint ptr [[DST_2:%.*]] to i64
16; CHECK-NEXT:    [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 1)
17; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
18; CHECK-NEXT:    [[TMP1:%.*]] = mul i64 [[TMP0]], 4
19; CHECK-NEXT:    [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 28, i64 [[TMP1]])
20; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], [[TMP2]]
21; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
22; CHECK:       vector.memcheck:
23; CHECK-NEXT:    [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
24; CHECK-NEXT:    [[TMP4:%.*]] = mul i64 [[TMP3]], 2
25; CHECK-NEXT:    [[TMP5:%.*]] = mul i64 [[TMP4]], 16
26; CHECK-NEXT:    [[TMP6:%.*]] = sub i64 [[DST_21]], [[DST_12]]
27; CHECK-NEXT:    [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
28; CHECK-NEXT:    [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
29; CHECK-NEXT:    [[TMP8:%.*]] = mul i64 [[TMP7]], 2
30; CHECK-NEXT:    [[TMP9:%.*]] = mul i64 [[TMP8]], 16
31; CHECK-NEXT:    [[TMP10:%.*]] = sub i64 [[DST_12]], [[SRC_13]]
32; CHECK-NEXT:    [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP10]], [[TMP9]]
33; CHECK-NEXT:    [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
34; CHECK-NEXT:    [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
35; CHECK-NEXT:    [[TMP12:%.*]] = mul i64 [[TMP11]], 2
36; CHECK-NEXT:    [[TMP13:%.*]] = mul i64 [[TMP12]], 16
37; CHECK-NEXT:    [[TMP14:%.*]] = sub i64 [[DST_12]], [[SRC_25]]
38; CHECK-NEXT:    [[DIFF_CHECK6:%.*]] = icmp ult i64 [[TMP14]], [[TMP13]]
39; CHECK-NEXT:    [[CONFLICT_RDX7:%.*]] = or i1 [[CONFLICT_RDX]], [[DIFF_CHECK6]]
40; CHECK-NEXT:    [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
41; CHECK-NEXT:    [[TMP16:%.*]] = mul i64 [[TMP15]], 2
42; CHECK-NEXT:    [[TMP17:%.*]] = mul i64 [[TMP16]], 16
43; CHECK-NEXT:    [[TMP18:%.*]] = sub i64 [[DST_21]], [[SRC_13]]
44; CHECK-NEXT:    [[DIFF_CHECK8:%.*]] = icmp ult i64 [[TMP18]], [[TMP17]]
45; CHECK-NEXT:    [[CONFLICT_RDX9:%.*]] = or i1 [[CONFLICT_RDX7]], [[DIFF_CHECK8]]
46; CHECK-NEXT:    [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
47; CHECK-NEXT:    [[TMP20:%.*]] = mul i64 [[TMP19]], 2
48; CHECK-NEXT:    [[TMP21:%.*]] = mul i64 [[TMP20]], 16
49; CHECK-NEXT:    [[TMP22:%.*]] = sub i64 [[DST_21]], [[SRC_25]]
50; CHECK-NEXT:    [[DIFF_CHECK10:%.*]] = icmp ult i64 [[TMP22]], [[TMP21]]
51; CHECK-NEXT:    [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX9]], [[DIFF_CHECK10]]
52; CHECK-NEXT:    br i1 [[CONFLICT_RDX11]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
53; CHECK:       vector.ph:
54; CHECK-NEXT:    [[TMP23:%.*]] = call i64 @llvm.vscale.i64()
55; CHECK-NEXT:    [[TMP24:%.*]] = mul i64 [[TMP23]], 4
56; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], [[TMP24]]
57; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
58; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
59; CHECK:       vector.body:
60; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
61; CHECK-NEXT:    [[TMP25:%.*]] = add i64 [[INDEX]], 0
62; CHECK-NEXT:    [[TMP26:%.*]] = call i64 @llvm.vscale.i64()
63; CHECK-NEXT:    [[TMP27:%.*]] = mul i64 [[TMP26]], 2
64; CHECK-NEXT:    [[TMP28:%.*]] = add i64 [[TMP27]], 0
65; CHECK-NEXT:    [[TMP29:%.*]] = mul i64 [[TMP28]], 1
66; CHECK-NEXT:    [[TMP30:%.*]] = add i64 [[INDEX]], [[TMP29]]
67; CHECK-NEXT:    [[TMP31:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[TMP25]]
68; CHECK-NEXT:    [[TMP32:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[TMP30]]
69; CHECK-NEXT:    [[TMP33:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP25]]
70; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP30]]
71; CHECK-NEXT:    [[TMP35:%.*]] = getelementptr i64, ptr [[TMP31]], i32 0
72; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP35]], align 4
73; CHECK-NEXT:    [[TMP36:%.*]] = call i32 @llvm.vscale.i32()
74; CHECK-NEXT:    [[TMP37:%.*]] = mul i32 [[TMP36]], 2
75; CHECK-NEXT:    [[TMP38:%.*]] = getelementptr i64, ptr [[TMP31]], i32 [[TMP37]]
76; CHECK-NEXT:    [[WIDE_LOAD12:%.*]] = load <vscale x 2 x i64>, ptr [[TMP38]], align 4
77; CHECK-NEXT:    [[TMP39:%.*]] = getelementptr i64, ptr [[TMP33]], i32 0
78; CHECK-NEXT:    [[WIDE_LOAD13:%.*]] = load <vscale x 2 x i64>, ptr [[TMP39]], align 4
79; CHECK-NEXT:    [[TMP40:%.*]] = call i32 @llvm.vscale.i32()
80; CHECK-NEXT:    [[TMP41:%.*]] = mul i32 [[TMP40]], 2
81; CHECK-NEXT:    [[TMP42:%.*]] = getelementptr i64, ptr [[TMP33]], i32 [[TMP41]]
82; CHECK-NEXT:    [[WIDE_LOAD14:%.*]] = load <vscale x 2 x i64>, ptr [[TMP42]], align 4
83; CHECK-NEXT:    [[TMP43:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD]], [[WIDE_LOAD13]]
84; CHECK-NEXT:    [[TMP44:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD12]], [[WIDE_LOAD14]]
85; CHECK-NEXT:    [[TMP45:%.*]] = getelementptr i64, ptr [[DST_1]], i64 [[TMP25]]
86; CHECK-NEXT:    [[TMP46:%.*]] = getelementptr i64, ptr [[DST_1]], i64 [[TMP30]]
87; CHECK-NEXT:    [[TMP47:%.*]] = getelementptr i64, ptr [[DST_2]], i64 [[TMP25]]
88; CHECK-NEXT:    [[TMP48:%.*]] = getelementptr i64, ptr [[DST_2]], i64 [[TMP30]]
89; CHECK-NEXT:    [[TMP49:%.*]] = getelementptr i64, ptr [[TMP45]], i32 0
90; CHECK-NEXT:    store <vscale x 2 x i64> [[TMP43]], ptr [[TMP49]], align 4
91; CHECK-NEXT:    [[TMP50:%.*]] = call i32 @llvm.vscale.i32()
92; CHECK-NEXT:    [[TMP51:%.*]] = mul i32 [[TMP50]], 2
93; CHECK-NEXT:    [[TMP52:%.*]] = getelementptr i64, ptr [[TMP45]], i32 [[TMP51]]
94; CHECK-NEXT:    store <vscale x 2 x i64> [[TMP44]], ptr [[TMP52]], align 4
95; CHECK-NEXT:    [[TMP53:%.*]] = getelementptr i64, ptr [[TMP47]], i32 0
96; CHECK-NEXT:    store <vscale x 2 x i64> [[TMP43]], ptr [[TMP53]], align 4
97; CHECK-NEXT:    [[TMP54:%.*]] = call i32 @llvm.vscale.i32()
98; CHECK-NEXT:    [[TMP55:%.*]] = mul i32 [[TMP54]], 2
99; CHECK-NEXT:    [[TMP56:%.*]] = getelementptr i64, ptr [[TMP47]], i32 [[TMP55]]
100; CHECK-NEXT:    store <vscale x 2 x i64> [[TMP44]], ptr [[TMP56]], align 4
101; CHECK-NEXT:    [[TMP57:%.*]] = call i64 @llvm.vscale.i64()
102; CHECK-NEXT:    [[TMP58:%.*]] = mul i64 [[TMP57]], 4
103; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP58]]
104; CHECK-NEXT:    [[TMP59:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
105; CHECK-NEXT:    br i1 [[TMP59]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
106; CHECK:       middle.block:
107; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
108; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
109; CHECK:       scalar.ph:
110; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ]
111; CHECK-NEXT:    br label [[LOOP:%.*]]
112; CHECK:       loop:
113; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
114; CHECK-NEXT:    [[GEP_SRC_1:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[IV]]
115; CHECK-NEXT:    [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
116; CHECK-NEXT:    [[L_1:%.*]] = load i64, ptr [[GEP_SRC_1]], align 4
117; CHECK-NEXT:    [[L_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
118; CHECK-NEXT:    [[ADD:%.*]] = add i64 [[L_1]], [[L_2]]
119; CHECK-NEXT:    [[GEP_DST_1:%.*]] = getelementptr i64, ptr [[DST_1]], i64 [[IV]]
120; CHECK-NEXT:    [[GEP_DST_2:%.*]] = getelementptr i64, ptr [[DST_2]], i64 [[IV]]
121; CHECK-NEXT:    store i64 [[ADD]], ptr [[GEP_DST_1]], align 4
122; CHECK-NEXT:    store i64 [[ADD]], ptr [[GEP_DST_2]], align 4
123; CHECK-NEXT:    [[IV_NEXT]] = add nsw i64 [[IV]], 1
124; CHECK-NEXT:    [[CMP10:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
125; CHECK-NEXT:    br i1 [[CMP10]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP2:![0-9]+]]
126; CHECK:       exit:
127; CHECK-NEXT:    ret void
128;
129entry:
130  br label %loop
131
132loop:
133  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
134  %gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv
135  %gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
136  %l.1 = load i64, ptr %gep.src.1
137  %l.2 = load i64, ptr %gep.src.2
138  %add = add i64 %l.1, %l.2
139  %gep.dst.1 = getelementptr i64, ptr %dst.1, i64 %iv
140  %gep.dst.2 = getelementptr i64, ptr %dst.2, i64 %iv
141  store i64 %add, ptr %gep.dst.1
142  store i64 %add, ptr %gep.dst.2
143  %iv.next = add nsw i64 %iv, 1
144  %cmp10 = icmp ult i64 %iv.next, %n
145  br i1 %cmp10, label %loop, label %exit
146
147exit:
148  ret void
149}
150