1; RUN: opt -loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S -o - < %s | FileCheck %s
2; RUN: opt -mattr=+sve -loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S -o - < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6; This test is defending against a bug that appeared when we have a target
7; configuration where masked loads/stores are legal -- e.g. AArch64 with SVE.
8; Predication would not be applied during interleaving, enabling the
9; possibility of superfluous loads/stores which could result in miscompiles.
10; This test checks that, when we disable vectorisation and force interleaving,
11; stores are predicated properly.
12;
13; This is _not_ an SVE-specific test. The same bug could manifest on any
14; architecture with masked loads/stores, but we use SVE for testing purposes
15; here.
16
17define void @foo(i32* %data1, i32* %data2) {
18; CHECK-LABEL: @foo(
19; CHECK:       vector.body:
20; CHECK:         br i1 {{%.*}}, label %pred.store.if, label %pred.store.continue
21; CHECK:       pred.store.if:
22; CHECK-NEXT:    store i32 {{%.*}}, i32* {{%.*}}
23; CHECK-NEXT:    br label %pred.store.continue
24; CHECK:       pred.store.continue:
25; CHECK-NEXT:    br i1 {{%.*}}, label %pred.store.if2, label %pred.store.continue3
26; CHECK:       pred.store.if2:
27; CHECK-NEXT:    store i32 {{%.*}}, i32* {{%.*}}
28; CHECK-NEXT:    br label %pred.store.continue3
29; CHECK:       pred.store.continue3:
30
31entry:
32  br label %while.body
33
34while.body:
35  %i = phi i64 [ 1023, %entry ], [ %i.next, %if.end ]
36  %arrayidx = getelementptr inbounds i32, i32* %data1, i64 %i
37  %ld = load i32, i32* %arrayidx, align 4
38  %cmp = icmp sgt i32 %ld, %ld
39  br i1 %cmp, label %if.then, label %if.end
40
41if.then:
42  store i32 %ld, i32* %arrayidx, align 4
43  br label %if.end
44
45if.end:
46  %i.next = add nsw i64 %i, -1
47  %tobool.not = icmp eq i64 %i, 0
48  br i1 %tobool.not, label %while.end, label %while.body
49
50while.end:
51  ret void
52}
53