1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -unroll-runtime-other-exit-predictable=false -loop-unroll -unroll-runtime=true -verify-dom-info -verify-loop-info -instcombine -S | FileCheck %s 3; RUN: opt < %s -unroll-runtime-other-exit-predictable=false -loop-unroll -unroll-runtime=true -verify-dom-info -unroll-runtime-multi-exit=false -verify-loop-info -S | FileCheck %s -check-prefix=NOUNROLL 4; RUN: opt < %s -unroll-runtime-other-exit-predictable=false -loop-unroll -unroll-runtime=true -verify-dom-info -unroll-runtime-multi-exit=true -verify-loop-info -S | FileCheck %s -check-prefix=ENABLED 5 6; The purpose of these tests is to exercise the heuristics which decide whether 7; to unroll multiple exit loops - specifically, the multiple exit reasoning. 8; Currently, we have heuristics both at the pass level, and controlled by a 9; flag in the implementation, so we need to test all three states of the flag 10; to cover all the logic completely. Note that the unroll factor is not 11; manually specified in these tests - see runtime-loop-multiple-exits.ll for 12; functional tests with forced unroll factors. 13 14; the second exit block is a deopt block. The loop has one exiting block other than the latch. 15define i32 @test1(i32* nocapture %a, i64 %n) { 16; CHECK-LABEL: @test1( 17; CHECK-NEXT: entry: 18; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], -1 19; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 7 20; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 7 21; CHECK-NEXT: br i1 [[TMP1]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]] 22; CHECK: entry.new: 23; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[N]], -8 24; CHECK-NEXT: br label [[HEADER:%.*]] 25; CHECK: header: 26; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[LATCH_7:%.*]] ] 27; CHECK-NEXT: [[SUM_02:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[ADD_7:%.*]], [[LATCH_7]] ] 28; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LATCH_7]] ] 29; CHECK-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 30; CHECK: for.exiting_block: 31; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 32; CHECK-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]] 33; CHECK: latch: 34; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 35; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 36; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[SUM_02]] 37; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or i64 [[INDVARS_IV]], 1 38; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]] 39; CHECK: for.exiting_block.1: 40; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 41; CHECK-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]] 42; CHECK: latch.1: 43; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT]] 44; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4 45; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP3]], [[ADD]] 46; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = or i64 [[INDVARS_IV]], 2 47; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]] 48; CHECK: for.exiting_block.2: 49; CHECK-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 50; CHECK-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]] 51; CHECK: latch.2: 52; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_1]] 53; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4 54; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP4]], [[ADD_1]] 55; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = or i64 [[INDVARS_IV]], 3 56; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]] 57; CHECK: for.exiting_block.3: 58; CHECK-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 59; CHECK-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]] 60; CHECK: latch.3: 61; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_2]] 62; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4 63; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP5]], [[ADD_2]] 64; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = or i64 [[INDVARS_IV]], 4 65; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]] 66; CHECK: for.exiting_block.4: 67; CHECK-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 68; CHECK-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]] 69; CHECK: latch.4: 70; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_3]] 71; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4 72; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP6]], [[ADD_3]] 73; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = or i64 [[INDVARS_IV]], 5 74; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]] 75; CHECK: for.exiting_block.5: 76; CHECK-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 77; CHECK-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]] 78; CHECK: latch.5: 79; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_4]] 80; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4 81; CHECK-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP7]], [[ADD_4]] 82; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = or i64 [[INDVARS_IV]], 6 83; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]] 84; CHECK: for.exiting_block.6: 85; CHECK-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 86; CHECK-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]] 87; CHECK: latch.6: 88; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_5]] 89; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4 90; CHECK-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP8]], [[ADD_5]] 91; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = or i64 [[INDVARS_IV]], 7 92; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]] 93; CHECK: for.exiting_block.7: 94; CHECK-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 95; CHECK-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]] 96; CHECK: latch.7: 97; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_6]] 98; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4 99; CHECK-NEXT: [[ADD_7]] = add nsw i32 [[TMP9]], [[ADD_6]] 100; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV]], 8 101; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER]], 8 102; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] 103; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] 104; CHECK: latchexit.unr-lcssa.loopexit: 105; CHECK-NEXT: br label [[LATCHEXIT_UNR_LCSSA]] 106; CHECK: latchexit.unr-lcssa: 107; CHECK-NEXT: [[SUM_0_LCSSA_PH:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[ADD_7]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 108; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_NEXT_7]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 109; CHECK-NEXT: [[SUM_02_UNR:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[ADD_7]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 110; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0 111; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[LATCHEXIT:%.*]], label [[HEADER_EPIL_PREHEADER:%.*]] 112; CHECK: header.epil.preheader: 113; CHECK-NEXT: br label [[HEADER_EPIL:%.*]] 114; CHECK: header.epil: 115; CHECK-NEXT: [[INDVARS_IV_EPIL:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_EPIL:%.*]], [[LATCH_EPIL:%.*]] ], [ [[INDVARS_IV_UNR]], [[HEADER_EPIL_PREHEADER]] ] 116; CHECK-NEXT: [[SUM_02_EPIL:%.*]] = phi i32 [ [[ADD_EPIL:%.*]], [[LATCH_EPIL]] ], [ [[SUM_02_UNR]], [[HEADER_EPIL_PREHEADER]] ] 117; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ [[EPIL_ITER_NEXT:%.*]], [[LATCH_EPIL]] ], [ 0, [[HEADER_EPIL_PREHEADER]] ] 118; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_EPIL:%.*]] 119; CHECK: for.exiting_block.epil: 120; CHECK-NEXT: [[CMP_EPIL:%.*]] = icmp eq i64 [[N]], 42 121; CHECK-NEXT: br i1 [[CMP_EPIL]], label [[OTHEREXIT_LOOPEXIT3:%.*]], label [[LATCH_EPIL]] 122; CHECK: latch.epil: 123; CHECK-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_EPIL]] 124; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX_EPIL]], align 4 125; CHECK-NEXT: [[ADD_EPIL]] = add nsw i32 [[TMP10]], [[SUM_02_EPIL]] 126; CHECK-NEXT: [[INDVARS_IV_NEXT_EPIL]] = add i64 [[INDVARS_IV_EPIL]], 1 127; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1 128; CHECK-NEXT: [[EPIL_ITER_CMP_NOT:%.*]] = icmp eq i64 [[EPIL_ITER_NEXT]], [[XTRAITER]] 129; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_NOT]], label [[LATCHEXIT_EPILOG_LCSSA:%.*]], label [[HEADER_EPIL]], !llvm.loop [[LOOP0:![0-9]+]] 130; CHECK: latchexit.epilog-lcssa: 131; CHECK-NEXT: br label [[LATCHEXIT]] 132; CHECK: latchexit: 133; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA_PH]], [[LATCHEXIT_UNR_LCSSA]] ], [ [[ADD_EPIL]], [[LATCHEXIT_EPILOG_LCSSA]] ] 134; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]] 135; CHECK: otherexit.loopexit: 136; CHECK-NEXT: [[SUM_02_LCSSA_PH:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ], [ [[ADD]], [[FOR_EXITING_BLOCK_1]] ], [ [[ADD_1]], [[FOR_EXITING_BLOCK_2]] ], [ [[ADD_2]], [[FOR_EXITING_BLOCK_3]] ], [ [[ADD_3]], [[FOR_EXITING_BLOCK_4]] ], [ [[ADD_4]], [[FOR_EXITING_BLOCK_5]] ], [ [[ADD_5]], [[FOR_EXITING_BLOCK_6]] ], [ [[ADD_6]], [[FOR_EXITING_BLOCK_7]] ] 137; CHECK-NEXT: br label [[OTHEREXIT:%.*]] 138; CHECK: otherexit.loopexit3: 139; CHECK-NEXT: br label [[OTHEREXIT]] 140; CHECK: otherexit: 141; CHECK-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[SUM_02_LCSSA_PH]], [[OTHEREXIT_LOOPEXIT]] ], [ [[SUM_02_EPIL]], [[OTHEREXIT_LOOPEXIT3]] ] 142; CHECK-NEXT: [[RVAL:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 [[SUM_02_LCSSA]]) ] 143; CHECK-NEXT: ret i32 [[RVAL]] 144; 145; NOUNROLL-LABEL: @test1( 146; NOUNROLL-NEXT: entry: 147; NOUNROLL-NEXT: br label [[HEADER:%.*]] 148; NOUNROLL: header: 149; NOUNROLL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 150; NOUNROLL-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 151; NOUNROLL-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 152; NOUNROLL: for.exiting_block: 153; NOUNROLL-NEXT: [[CMP:%.*]] = icmp eq i64 [[N:%.*]], 42 154; NOUNROLL-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 155; NOUNROLL: latch: 156; NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 157; NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 158; NOUNROLL-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 159; NOUNROLL-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 160; NOUNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 161; NOUNROLL-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]] 162; NOUNROLL: latchexit: 163; NOUNROLL-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[LATCH]] ] 164; NOUNROLL-NEXT: ret i32 [[SUM_0_LCSSA]] 165; NOUNROLL: otherexit: 166; NOUNROLL-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ] 167; NOUNROLL-NEXT: [[RVAL:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 [[SUM_02_LCSSA]]) ] 168; NOUNROLL-NEXT: ret i32 [[RVAL]] 169; 170; ENABLED-LABEL: @test1( 171; ENABLED-NEXT: entry: 172; ENABLED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], -1 173; ENABLED-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 7 174; ENABLED-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 7 175; ENABLED-NEXT: br i1 [[TMP1]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]] 176; ENABLED: entry.new: 177; ENABLED-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]] 178; ENABLED-NEXT: br label [[HEADER:%.*]] 179; ENABLED: header: 180; ENABLED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[LATCH_7:%.*]] ] 181; ENABLED-NEXT: [[SUM_02:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[ADD_7:%.*]], [[LATCH_7]] ] 182; ENABLED-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LATCH_7]] ] 183; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 184; ENABLED: for.exiting_block: 185; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 186; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]] 187; ENABLED: latch: 188; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 189; ENABLED-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 190; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[SUM_02]] 191; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 192; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 193; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]] 194; ENABLED: for.exiting_block.1: 195; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 196; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]] 197; ENABLED: latch.1: 198; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT]] 199; ENABLED-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4 200; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP3]], [[ADD]] 201; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 202; ENABLED-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1 203; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]] 204; ENABLED: for.exiting_block.2: 205; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 206; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]] 207; ENABLED: latch.2: 208; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_1]] 209; ENABLED-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4 210; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP4]], [[ADD_1]] 211; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 212; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1 213; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]] 214; ENABLED: for.exiting_block.3: 215; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 216; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]] 217; ENABLED: latch.3: 218; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_2]] 219; ENABLED-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4 220; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP5]], [[ADD_2]] 221; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 222; ENABLED-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1 223; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]] 224; ENABLED: for.exiting_block.4: 225; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 226; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]] 227; ENABLED: latch.4: 228; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_3]] 229; ENABLED-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4 230; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP6]], [[ADD_3]] 231; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 232; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1 233; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]] 234; ENABLED: for.exiting_block.5: 235; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 236; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]] 237; ENABLED: latch.5: 238; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_4]] 239; ENABLED-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4 240; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP7]], [[ADD_4]] 241; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 242; ENABLED-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1 243; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]] 244; ENABLED: for.exiting_block.6: 245; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 246; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]] 247; ENABLED: latch.6: 248; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_5]] 249; ENABLED-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4 250; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP8]], [[ADD_5]] 251; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 252; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1 253; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]] 254; ENABLED: for.exiting_block.7: 255; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 256; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]] 257; ENABLED: latch.7: 258; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_6]] 259; ENABLED-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4 260; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP9]], [[ADD_6]] 261; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV_NEXT_6]], 1 262; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 263; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] 264; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] 265; ENABLED: latchexit.unr-lcssa.loopexit: 266; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] 267; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ] 268; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] 269; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]] 270; ENABLED: latchexit.unr-lcssa: 271; ENABLED-NEXT: [[SUM_0_LCSSA_PH:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[SUM_0_LCSSA_PH_PH]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 272; ENABLED-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_UNR_PH]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 273; ENABLED-NEXT: [[SUM_02_UNR:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[SUM_02_UNR_PH]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 274; ENABLED-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 275; ENABLED-NEXT: br i1 [[LCMP_MOD]], label [[HEADER_EPIL_PREHEADER:%.*]], label [[LATCHEXIT:%.*]] 276; ENABLED: header.epil.preheader: 277; ENABLED-NEXT: br label [[HEADER_EPIL:%.*]] 278; ENABLED: header.epil: 279; ENABLED-NEXT: [[INDVARS_IV_EPIL:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_EPIL:%.*]], [[LATCH_EPIL:%.*]] ], [ [[INDVARS_IV_UNR]], [[HEADER_EPIL_PREHEADER]] ] 280; ENABLED-NEXT: [[SUM_02_EPIL:%.*]] = phi i32 [ [[ADD_EPIL:%.*]], [[LATCH_EPIL]] ], [ [[SUM_02_UNR]], [[HEADER_EPIL_PREHEADER]] ] 281; ENABLED-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, [[HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[LATCH_EPIL]] ] 282; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_EPIL:%.*]] 283; ENABLED: for.exiting_block.epil: 284; ENABLED-NEXT: [[CMP_EPIL:%.*]] = icmp eq i64 [[N]], 42 285; ENABLED-NEXT: br i1 [[CMP_EPIL]], label [[OTHEREXIT_LOOPEXIT3:%.*]], label [[LATCH_EPIL]] 286; ENABLED: latch.epil: 287; ENABLED-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_EPIL]] 288; ENABLED-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX_EPIL]], align 4 289; ENABLED-NEXT: [[ADD_EPIL]] = add nsw i32 [[TMP10]], [[SUM_02_EPIL]] 290; ENABLED-NEXT: [[INDVARS_IV_NEXT_EPIL]] = add i64 [[INDVARS_IV_EPIL]], 1 291; ENABLED-NEXT: [[EXITCOND_EPIL:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_EPIL]], [[N]] 292; ENABLED-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1 293; ENABLED-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]] 294; ENABLED-NEXT: br i1 [[EPIL_ITER_CMP]], label [[HEADER_EPIL]], label [[LATCHEXIT_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP0:![0-9]+]] 295; ENABLED: latchexit.epilog-lcssa: 296; ENABLED-NEXT: [[SUM_0_LCSSA_PH2:%.*]] = phi i32 [ [[ADD_EPIL]], [[LATCH_EPIL]] ] 297; ENABLED-NEXT: br label [[LATCHEXIT]] 298; ENABLED: latchexit: 299; ENABLED-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA_PH]], [[LATCHEXIT_UNR_LCSSA]] ], [ [[SUM_0_LCSSA_PH2]], [[LATCHEXIT_EPILOG_LCSSA]] ] 300; ENABLED-NEXT: ret i32 [[SUM_0_LCSSA]] 301; ENABLED: otherexit.loopexit: 302; ENABLED-NEXT: [[SUM_02_LCSSA_PH:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ], [ [[ADD]], [[FOR_EXITING_BLOCK_1]] ], [ [[ADD_1]], [[FOR_EXITING_BLOCK_2]] ], [ [[ADD_2]], [[FOR_EXITING_BLOCK_3]] ], [ [[ADD_3]], [[FOR_EXITING_BLOCK_4]] ], [ [[ADD_4]], [[FOR_EXITING_BLOCK_5]] ], [ [[ADD_5]], [[FOR_EXITING_BLOCK_6]] ], [ [[ADD_6]], [[FOR_EXITING_BLOCK_7]] ] 303; ENABLED-NEXT: br label [[OTHEREXIT:%.*]] 304; ENABLED: otherexit.loopexit3: 305; ENABLED-NEXT: [[SUM_02_LCSSA_PH4:%.*]] = phi i32 [ [[SUM_02_EPIL]], [[FOR_EXITING_BLOCK_EPIL]] ] 306; ENABLED-NEXT: br label [[OTHEREXIT]] 307; ENABLED: otherexit: 308; ENABLED-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[SUM_02_LCSSA_PH]], [[OTHEREXIT_LOOPEXIT]] ], [ [[SUM_02_LCSSA_PH4]], [[OTHEREXIT_LOOPEXIT3]] ] 309; ENABLED-NEXT: [[RVAL:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 [[SUM_02_LCSSA]]) ] 310; ENABLED-NEXT: ret i32 [[RVAL]] 311; 312entry: 313 br label %header 314 315header: 316 %indvars.iv = phi i64 [ %indvars.iv.next, %latch ], [ 0, %entry ] 317 %sum.02 = phi i32 [ %add, %latch ], [ 0, %entry ] 318 br label %for.exiting_block 319 320for.exiting_block: 321 %cmp = icmp eq i64 %n, 42 322 br i1 %cmp, label %otherexit, label %latch 323 324latch: 325 %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv 326 %0 = load i32, i32* %arrayidx, align 4 327 %add = add nsw i32 %0, %sum.02 328 %indvars.iv.next = add i64 %indvars.iv, 1 329 %exitcond = icmp eq i64 %indvars.iv.next, %n 330 br i1 %exitcond, label %latchexit, label %header 331 332latchexit: ; preds = %latch 333 %sum.0.lcssa = phi i32 [ %add, %latch ] 334 ret i32 %sum.0.lcssa 335 336otherexit: 337 %rval = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 %sum.02) ] 338 ret i32 %rval 339} 340 341; the exit block is not a deopt block. 342define i32 @test2(i32* nocapture %a, i64 %n) { 343; 344; CHECK-LABEL: @test2( 345; CHECK-NEXT: entry: 346; CHECK-NEXT: br label [[HEADER:%.*]] 347; CHECK: header: 348; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 349; CHECK-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 350; CHECK-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 351; CHECK: for.exiting_block: 352; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[N:%.*]], 42 353; CHECK-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 354; CHECK: latch: 355; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 356; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 357; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 358; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 359; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 360; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]] 361; CHECK: latchexit: 362; CHECK-NEXT: ret i32 [[ADD]] 363; CHECK: otherexit: 364; CHECK-NEXT: ret i32 [[SUM_02]] 365; 366; NOUNROLL-LABEL: @test2( 367; NOUNROLL-NEXT: entry: 368; NOUNROLL-NEXT: br label [[HEADER:%.*]] 369; NOUNROLL: header: 370; NOUNROLL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 371; NOUNROLL-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 372; NOUNROLL-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 373; NOUNROLL: for.exiting_block: 374; NOUNROLL-NEXT: [[CMP:%.*]] = icmp eq i64 [[N:%.*]], 42 375; NOUNROLL-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 376; NOUNROLL: latch: 377; NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 378; NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 379; NOUNROLL-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 380; NOUNROLL-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 381; NOUNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 382; NOUNROLL-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]] 383; NOUNROLL: latchexit: 384; NOUNROLL-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[LATCH]] ] 385; NOUNROLL-NEXT: ret i32 [[SUM_0_LCSSA]] 386; NOUNROLL: otherexit: 387; NOUNROLL-NEXT: [[RVAL:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ] 388; NOUNROLL-NEXT: ret i32 [[RVAL]] 389; 390; ENABLED-LABEL: @test2( 391; ENABLED-NEXT: entry: 392; ENABLED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], -1 393; ENABLED-NEXT: [[XTRAITER:%.*]] = and i64 [[N]], 7 394; ENABLED-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 7 395; ENABLED-NEXT: br i1 [[TMP1]], label [[LATCHEXIT_UNR_LCSSA:%.*]], label [[ENTRY_NEW:%.*]] 396; ENABLED: entry.new: 397; ENABLED-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[N]], [[XTRAITER]] 398; ENABLED-NEXT: br label [[HEADER:%.*]] 399; ENABLED: header: 400; ENABLED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[LATCH_7:%.*]] ] 401; ENABLED-NEXT: [[SUM_02:%.*]] = phi i32 [ 0, [[ENTRY_NEW]] ], [ [[ADD_7:%.*]], [[LATCH_7]] ] 402; ENABLED-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[ENTRY_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[LATCH_7]] ] 403; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 404; ENABLED: for.exiting_block: 405; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 42 406; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT_LOOPEXIT:%.*]], label [[LATCH:%.*]] 407; ENABLED: latch: 408; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 409; ENABLED-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 410; ENABLED-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[SUM_02]] 411; ENABLED-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 412; ENABLED-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 413; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]] 414; ENABLED: for.exiting_block.1: 415; ENABLED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[N]], 42 416; ENABLED-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]] 417; ENABLED: latch.1: 418; ENABLED-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT]] 419; ENABLED-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4 420; ENABLED-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP3]], [[ADD]] 421; ENABLED-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 422; ENABLED-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1 423; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]] 424; ENABLED: for.exiting_block.2: 425; ENABLED-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[N]], 42 426; ENABLED-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]] 427; ENABLED: latch.2: 428; ENABLED-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_1]] 429; ENABLED-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4 430; ENABLED-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP4]], [[ADD_1]] 431; ENABLED-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 432; ENABLED-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1 433; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]] 434; ENABLED: for.exiting_block.3: 435; ENABLED-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[N]], 42 436; ENABLED-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]] 437; ENABLED: latch.3: 438; ENABLED-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_2]] 439; ENABLED-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4 440; ENABLED-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP5]], [[ADD_2]] 441; ENABLED-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 442; ENABLED-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1 443; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]] 444; ENABLED: for.exiting_block.4: 445; ENABLED-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[N]], 42 446; ENABLED-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]] 447; ENABLED: latch.4: 448; ENABLED-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_3]] 449; ENABLED-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4 450; ENABLED-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP6]], [[ADD_3]] 451; ENABLED-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1 452; ENABLED-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1 453; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]] 454; ENABLED: for.exiting_block.5: 455; ENABLED-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[N]], 42 456; ENABLED-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]] 457; ENABLED: latch.5: 458; ENABLED-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_4]] 459; ENABLED-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4 460; ENABLED-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP7]], [[ADD_4]] 461; ENABLED-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1 462; ENABLED-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1 463; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]] 464; ENABLED: for.exiting_block.6: 465; ENABLED-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[N]], 42 466; ENABLED-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]] 467; ENABLED: latch.6: 468; ENABLED-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_5]] 469; ENABLED-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4 470; ENABLED-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP8]], [[ADD_5]] 471; ENABLED-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1 472; ENABLED-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1 473; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]] 474; ENABLED: for.exiting_block.7: 475; ENABLED-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[N]], 42 476; ENABLED-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]] 477; ENABLED: latch.7: 478; ENABLED-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_NEXT_6]] 479; ENABLED-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4 480; ENABLED-NEXT: [[ADD_7]] = add nsw i32 [[TMP9]], [[ADD_6]] 481; ENABLED-NEXT: [[INDVARS_IV_NEXT_7]] = add i64 [[INDVARS_IV_NEXT_6]], 1 482; ENABLED-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 483; ENABLED-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] 484; ENABLED-NEXT: br i1 [[NITER_NCMP_7]], label [[LATCHEXIT_UNR_LCSSA_LOOPEXIT:%.*]], label [[HEADER]] 485; ENABLED: latchexit.unr-lcssa.loopexit: 486; ENABLED-NEXT: [[SUM_0_LCSSA_PH_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] 487; ENABLED-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_7]], [[LATCH_7]] ] 488; ENABLED-NEXT: [[SUM_02_UNR_PH:%.*]] = phi i32 [ [[ADD_7]], [[LATCH_7]] ] 489; ENABLED-NEXT: br label [[LATCHEXIT_UNR_LCSSA]] 490; ENABLED: latchexit.unr-lcssa: 491; ENABLED-NEXT: [[SUM_0_LCSSA_PH:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[SUM_0_LCSSA_PH_PH]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 492; ENABLED-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDVARS_IV_UNR_PH]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 493; ENABLED-NEXT: [[SUM_02_UNR:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[SUM_02_UNR_PH]], [[LATCHEXIT_UNR_LCSSA_LOOPEXIT]] ] 494; ENABLED-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 495; ENABLED-NEXT: br i1 [[LCMP_MOD]], label [[HEADER_EPIL_PREHEADER:%.*]], label [[LATCHEXIT:%.*]] 496; ENABLED: header.epil.preheader: 497; ENABLED-NEXT: br label [[HEADER_EPIL:%.*]] 498; ENABLED: header.epil: 499; ENABLED-NEXT: [[INDVARS_IV_EPIL:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_EPIL:%.*]], [[LATCH_EPIL:%.*]] ], [ [[INDVARS_IV_UNR]], [[HEADER_EPIL_PREHEADER]] ] 500; ENABLED-NEXT: [[SUM_02_EPIL:%.*]] = phi i32 [ [[ADD_EPIL:%.*]], [[LATCH_EPIL]] ], [ [[SUM_02_UNR]], [[HEADER_EPIL_PREHEADER]] ] 501; ENABLED-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, [[HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[LATCH_EPIL]] ] 502; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK_EPIL:%.*]] 503; ENABLED: for.exiting_block.epil: 504; ENABLED-NEXT: [[CMP_EPIL:%.*]] = icmp eq i64 [[N]], 42 505; ENABLED-NEXT: br i1 [[CMP_EPIL]], label [[OTHEREXIT_LOOPEXIT2:%.*]], label [[LATCH_EPIL]] 506; ENABLED: latch.epil: 507; ENABLED-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 [[INDVARS_IV_EPIL]] 508; ENABLED-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX_EPIL]], align 4 509; ENABLED-NEXT: [[ADD_EPIL]] = add nsw i32 [[TMP10]], [[SUM_02_EPIL]] 510; ENABLED-NEXT: [[INDVARS_IV_NEXT_EPIL]] = add i64 [[INDVARS_IV_EPIL]], 1 511; ENABLED-NEXT: [[EXITCOND_EPIL:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_EPIL]], [[N]] 512; ENABLED-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1 513; ENABLED-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]] 514; ENABLED-NEXT: br i1 [[EPIL_ITER_CMP]], label [[HEADER_EPIL]], label [[LATCHEXIT_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP2:![0-9]+]] 515; ENABLED: latchexit.epilog-lcssa: 516; ENABLED-NEXT: [[SUM_0_LCSSA_PH1:%.*]] = phi i32 [ [[ADD_EPIL]], [[LATCH_EPIL]] ] 517; ENABLED-NEXT: br label [[LATCHEXIT]] 518; ENABLED: latchexit: 519; ENABLED-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA_PH]], [[LATCHEXIT_UNR_LCSSA]] ], [ [[SUM_0_LCSSA_PH1]], [[LATCHEXIT_EPILOG_LCSSA]] ] 520; ENABLED-NEXT: ret i32 [[SUM_0_LCSSA]] 521; ENABLED: otherexit.loopexit: 522; ENABLED-NEXT: [[RVAL_PH:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ], [ [[ADD]], [[FOR_EXITING_BLOCK_1]] ], [ [[ADD_1]], [[FOR_EXITING_BLOCK_2]] ], [ [[ADD_2]], [[FOR_EXITING_BLOCK_3]] ], [ [[ADD_3]], [[FOR_EXITING_BLOCK_4]] ], [ [[ADD_4]], [[FOR_EXITING_BLOCK_5]] ], [ [[ADD_5]], [[FOR_EXITING_BLOCK_6]] ], [ [[ADD_6]], [[FOR_EXITING_BLOCK_7]] ] 523; ENABLED-NEXT: br label [[OTHEREXIT:%.*]] 524; ENABLED: otherexit.loopexit2: 525; ENABLED-NEXT: [[RVAL_PH3:%.*]] = phi i32 [ [[SUM_02_EPIL]], [[FOR_EXITING_BLOCK_EPIL]] ] 526; ENABLED-NEXT: br label [[OTHEREXIT]] 527; ENABLED: otherexit: 528; ENABLED-NEXT: [[RVAL:%.*]] = phi i32 [ [[RVAL_PH]], [[OTHEREXIT_LOOPEXIT]] ], [ [[RVAL_PH3]], [[OTHEREXIT_LOOPEXIT2]] ] 529; ENABLED-NEXT: ret i32 [[RVAL]] 530; 531entry: 532 br label %header 533 534header: 535 %indvars.iv = phi i64 [ %indvars.iv.next, %latch ], [ 0, %entry ] 536 %sum.02 = phi i32 [ %add, %latch ], [ 0, %entry ] 537 br label %for.exiting_block 538 539for.exiting_block: 540 %cmp = icmp eq i64 %n, 42 541 br i1 %cmp, label %otherexit, label %latch 542 543latch: 544 %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv 545 %0 = load i32, i32* %arrayidx, align 4 546 %add = add nsw i32 %0, %sum.02 547 %indvars.iv.next = add i64 %indvars.iv, 1 548 %exitcond = icmp eq i64 %indvars.iv.next, %n 549 br i1 %exitcond, label %latchexit, label %header 550 551latchexit: ; preds = %latch 552 %sum.0.lcssa = phi i32 [ %add, %latch ] 553 ret i32 %sum.0.lcssa 554 555otherexit: 556 %rval = phi i32 [%sum.02, %for.exiting_block ] 557 ret i32 %rval 558} 559 560; A multiple exit loop with an estimated trip count which is small, and thus 561; the loop is not worth unrolling. We probably should peel said loop, but 562; currently don't. 563define i32 @test3(i32* nocapture %a, i64 %n) !prof !{!"function_entry_count", i64 2048} { 564; CHECK-LABEL: @test3( 565; CHECK-NEXT: entry: 566; CHECK-NEXT: br label [[HEADER:%.*]] 567; CHECK: header: 568; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 569; CHECK-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 570; CHECK-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 571; CHECK: for.exiting_block: 572; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[N:%.*]], 42 573; CHECK-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 574; CHECK: latch: 575; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 576; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 577; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 578; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 579; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 580; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]], !prof [[PROF3:![0-9]+]] 581; CHECK: latchexit: 582; CHECK-NEXT: ret i32 [[ADD]] 583; CHECK: otherexit: 584; CHECK-NEXT: ret i32 57 585; 586; NOUNROLL-LABEL: @test3( 587; NOUNROLL-NEXT: entry: 588; NOUNROLL-NEXT: br label [[HEADER:%.*]] 589; NOUNROLL: header: 590; NOUNROLL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 591; NOUNROLL-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 592; NOUNROLL-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 593; NOUNROLL: for.exiting_block: 594; NOUNROLL-NEXT: [[CMP:%.*]] = icmp eq i64 [[N:%.*]], 42 595; NOUNROLL-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 596; NOUNROLL: latch: 597; NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 598; NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 599; NOUNROLL-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 600; NOUNROLL-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 601; NOUNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 602; NOUNROLL-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]], !prof [[PROF1:![0-9]+]] 603; NOUNROLL: latchexit: 604; NOUNROLL-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[LATCH]] ] 605; NOUNROLL-NEXT: ret i32 [[SUM_0_LCSSA]] 606; NOUNROLL: otherexit: 607; NOUNROLL-NEXT: ret i32 57 608; 609; ENABLED-LABEL: @test3( 610; ENABLED-NEXT: entry: 611; ENABLED-NEXT: br label [[HEADER:%.*]] 612; ENABLED: header: 613; ENABLED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 614; ENABLED-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 615; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 616; ENABLED: for.exiting_block: 617; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N:%.*]], 42 618; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 619; ENABLED: latch: 620; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 621; ENABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 622; ENABLED-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 623; ENABLED-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 624; ENABLED-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 625; ENABLED-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]], !prof [[PROF4:![0-9]+]] 626; ENABLED: latchexit: 627; ENABLED-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[LATCH]] ] 628; ENABLED-NEXT: ret i32 [[SUM_0_LCSSA]] 629; ENABLED: otherexit: 630; ENABLED-NEXT: ret i32 57 631; 632entry: 633 br label %header 634 635header: 636 %indvars.iv = phi i64 [ %indvars.iv.next, %latch ], [ 0, %entry ] 637 %sum.02 = phi i32 [ %add, %latch ], [ 0, %entry ] 638 br label %for.exiting_block 639 640for.exiting_block: 641 %cmp = icmp eq i64 %n, 42 642 br i1 %cmp, label %otherexit, label %latch 643 644latch: 645 %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv 646 %0 = load i32, i32* %arrayidx, align 4 647 %add = add nsw i32 %0, %sum.02 648 %indvars.iv.next = add i64 %indvars.iv, 1 649 %exitcond = icmp eq i64 %indvars.iv.next, %n 650 br i1 %exitcond, label %latchexit, label %header, !prof !{!"branch_weights", i64 1, i64 2} 651 652latchexit: ; preds = %latch 653 %sum.0.lcssa = phi i32 [ %add, %latch ] 654 ret i32 %sum.0.lcssa 655 656otherexit: 657 ret i32 57 658} 659 660; A case noticed while writing test3 where changing the early exit condition 661; seems to inhibit unrolling for some unclear reason. 662define i32 @test4(i32* nocapture %a, i64 %n) !prof !{!"function_entry_count", i64 2048} { 663; 664; CHECK-LABEL: @test4( 665; CHECK-NEXT: entry: 666; CHECK-NEXT: br label [[HEADER:%.*]] 667; CHECK: header: 668; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 669; CHECK-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 670; CHECK-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 671; CHECK: for.exiting_block: 672; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDVARS_IV]], 4096 673; CHECK-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 674; CHECK: latch: 675; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 676; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 677; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 678; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 679; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N:%.*]] 680; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]] 681; CHECK: latchexit: 682; CHECK-NEXT: ret i32 [[ADD]] 683; CHECK: otherexit: 684; CHECK-NEXT: ret i32 57 685; 686; NOUNROLL-LABEL: @test4( 687; NOUNROLL-NEXT: entry: 688; NOUNROLL-NEXT: br label [[HEADER:%.*]] 689; NOUNROLL: header: 690; NOUNROLL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 691; NOUNROLL-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 692; NOUNROLL-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 693; NOUNROLL: for.exiting_block: 694; NOUNROLL-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDVARS_IV]], 4096 695; NOUNROLL-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 696; NOUNROLL: latch: 697; NOUNROLL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 698; NOUNROLL-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 699; NOUNROLL-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 700; NOUNROLL-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 701; NOUNROLL-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N:%.*]] 702; NOUNROLL-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]] 703; NOUNROLL: latchexit: 704; NOUNROLL-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[LATCH]] ] 705; NOUNROLL-NEXT: ret i32 [[SUM_0_LCSSA]] 706; NOUNROLL: otherexit: 707; NOUNROLL-NEXT: ret i32 57 708; 709; ENABLED-LABEL: @test4( 710; ENABLED-NEXT: entry: 711; ENABLED-NEXT: br label [[HEADER:%.*]] 712; ENABLED: header: 713; ENABLED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 714; ENABLED-NEXT: [[SUM_02:%.*]] = phi i32 [ [[ADD:%.*]], [[LATCH]] ], [ 0, [[ENTRY]] ] 715; ENABLED-NEXT: br label [[FOR_EXITING_BLOCK:%.*]] 716; ENABLED: for.exiting_block: 717; ENABLED-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDVARS_IV]], 4096 718; ENABLED-NEXT: br i1 [[CMP]], label [[OTHEREXIT:%.*]], label [[LATCH]] 719; ENABLED: latch: 720; ENABLED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 721; ENABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 722; ENABLED-NEXT: [[ADD]] = add nsw i32 [[TMP0]], [[SUM_02]] 723; ENABLED-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 724; ENABLED-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N:%.*]] 725; ENABLED-NEXT: br i1 [[EXITCOND]], label [[LATCHEXIT:%.*]], label [[HEADER]] 726; ENABLED: latchexit: 727; ENABLED-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[LATCH]] ] 728; ENABLED-NEXT: ret i32 [[SUM_0_LCSSA]] 729; ENABLED: otherexit: 730; ENABLED-NEXT: ret i32 57 731; 732entry: 733 br label %header 734 735header: 736 %indvars.iv = phi i64 [ %indvars.iv.next, %latch ], [ 0, %entry ] 737 %sum.02 = phi i32 [ %add, %latch ], [ 0, %entry ] 738 br label %for.exiting_block 739 740for.exiting_block: 741 %cmp = icmp eq i64 %indvars.iv, 4096 742 br i1 %cmp, label %otherexit, label %latch 743 744latch: 745 %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv 746 %0 = load i32, i32* %arrayidx, align 4 747 %add = add nsw i32 %0, %sum.02 748 %indvars.iv.next = add i64 %indvars.iv, 1 749 %exitcond = icmp eq i64 %indvars.iv.next, %n 750 br i1 %exitcond, label %latchexit, label %header 751 752latchexit: ; preds = %latch 753 %sum.0.lcssa = phi i32 [ %add, %latch ] 754 ret i32 %sum.0.lcssa 755 756otherexit: 757 ret i32 57 758} 759 760 761 762declare i32 @llvm.experimental.deoptimize.i32(...) 763