1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=false -unroll-runtime-multi-exit=true -unroll-count=4 -verify-dom-info -S | FileCheck %s 3 4; REQUIRES: asserts 5; The tests below are for verifying dom tree after runtime unrolling 6; with multiple exit/exiting blocks. 7 8; We explicitly set the unroll count so that expensiveTripCount computation is allowed. 9 10declare i1 @unknown(i32) readonly nounwind willreturn 11 12; mergedexit block has edges from loop exit blocks. 13define i64 @test1() { 14; CHECK-LABEL: @test1( 15; CHECK-NEXT: entry: 16; CHECK-NEXT: br label [[PREHEADER:%.*]] 17; CHECK: preheader: 18; CHECK-NEXT: [[TRIP:%.*]] = zext i32 undef to i64 19; CHECK-NEXT: br label [[HEADER:%.*]] 20; CHECK: header: 21; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ] 22; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2 23; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]] 24; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]] 25; CHECK: latch: 26; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1 27; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]] 28; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]] 29; CHECK: header.1: 30; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2 31; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]] 32; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]] 33; CHECK: latch.1: 34; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1 35; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]] 36; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]] 37; CHECK: header.2: 38; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2 39; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]] 40; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]] 41; CHECK: latch.2: 42; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1 43; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]] 44; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]] 45; CHECK: header.3: 46; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2 47; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]] 48; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]] 49; CHECK: latch.3: 50; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1 51; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]] 52; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP0:![0-9]+]] 53; CHECK: headerexit: 54; CHECK-NEXT: [[ADDPHI:%.*]] = phi i64 [ [[ADD_IV]], [[HEADER]] ], [ [[ADD_IV_1]], [[HEADER_1]] ], [ [[ADD_IV_2]], [[HEADER_2]] ], [ [[ADD_IV_3]], [[HEADER_3]] ] 55; CHECK-NEXT: br label [[MERGEDEXIT:%.*]] 56; CHECK: latchexit: 57; CHECK-NEXT: [[SHFTPHI:%.*]] = phi i64 [ [[SHFT]], [[LATCH]] ], [ [[SHFT_1]], [[LATCH_1]] ], [ [[SHFT_2]], [[LATCH_2]] ], [ [[SHFT_3]], [[LATCH_3]] ] 58; CHECK-NEXT: br label [[MERGEDEXIT]] 59; CHECK: mergedexit: 60; CHECK-NEXT: [[RETVAL:%.*]] = phi i64 [ [[ADDPHI]], [[HEADEREXIT]] ], [ [[SHFTPHI]], [[LATCHEXIT]] ] 61; CHECK-NEXT: ret i64 [[RETVAL]] 62; 63entry: 64 br label %preheader 65 66preheader: ; preds = %bb 67 %trip = zext i32 undef to i64 68 br label %header 69 70header: ; preds = %latch, %preheader 71 %iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ] 72 %add.iv = add nuw nsw i64 %iv, 2 73 %cmp1 = icmp ult i64 %add.iv, %trip 74 br i1 %cmp1, label %latch, label %headerexit 75 76latch: ; preds = %header 77 %shft = ashr i64 %add.iv, 1 78 %cmp2 = icmp ult i64 %shft, %trip 79 br i1 %cmp2, label %header, label %latchexit 80 81headerexit: ; preds = %header 82 %addphi = phi i64 [ %add.iv, %header ] 83 br label %mergedexit 84 85latchexit: ; preds = %latch 86 %shftphi = phi i64 [ %shft, %latch ] 87 br label %mergedexit 88 89mergedexit: ; preds = %latchexit, %headerexit 90 %retval = phi i64 [ %addphi, %headerexit ], [ %shftphi, %latchexit ] 91 ret i64 %retval 92} 93 94; mergedexit has edges from loop exit blocks and a block outside the loop. 95define void @test2(i1 %cond, i32 %n) { 96; CHECK-LABEL: @test2( 97; CHECK-NEXT: entry: 98; CHECK-NEXT: br i1 [[COND:%.*]], label [[PREHEADER:%.*]], label [[MERGEDEXIT:%.*]] 99; CHECK: preheader: 100; CHECK-NEXT: [[TRIP:%.*]] = zext i32 [[N:%.*]] to i64 101; CHECK-NEXT: br label [[HEADER:%.*]] 102; CHECK: header: 103; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ] 104; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2 105; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]] 106; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]] 107; CHECK: latch: 108; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1 109; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]] 110; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]] 111; CHECK: header.1: 112; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2 113; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]] 114; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]] 115; CHECK: latch.1: 116; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1 117; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]] 118; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]] 119; CHECK: header.2: 120; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2 121; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]] 122; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]] 123; CHECK: latch.2: 124; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1 125; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]] 126; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]] 127; CHECK: header.3: 128; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2 129; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]] 130; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]] 131; CHECK: latch.3: 132; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1 133; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]] 134; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP2:![0-9]+]] 135; CHECK: headerexit: 136; CHECK-NEXT: br label [[MERGEDEXIT]] 137; CHECK: latchexit: 138; CHECK-NEXT: br label [[MERGEDEXIT]] 139; CHECK: mergedexit: 140; CHECK-NEXT: ret void 141; 142entry: 143 br i1 %cond, label %preheader, label %mergedexit 144 145preheader: ; preds = %entry 146 %trip = zext i32 %n to i64 147 br label %header 148 149header: ; preds = %latch, %preheader 150 %iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ] 151 %add.iv = add nuw nsw i64 %iv, 2 152 %cmp1 = icmp ult i64 %add.iv, %trip 153 br i1 %cmp1, label %latch, label %headerexit 154 155latch: ; preds = %header 156 %shft = ashr i64 %add.iv, 1 157 %cmp2 = icmp ult i64 %shft, %trip 158 br i1 %cmp2, label %header, label %latchexit 159 160headerexit: ; preds = %header 161 br label %mergedexit 162 163latchexit: ; preds = %latch 164 br label %mergedexit 165 166mergedexit: ; preds = %latchexit, %headerexit, %entry 167 ret void 168} 169 170 171; exitsucc is from loop exit block only. 172define i64 @test3(i32 %n) { 173; CHECK-LABEL: @test3( 174; CHECK-NEXT: entry: 175; CHECK-NEXT: br label [[PREHEADER:%.*]] 176; CHECK: preheader: 177; CHECK-NEXT: [[TRIP:%.*]] = zext i32 [[N:%.*]] to i64 178; CHECK-NEXT: br label [[HEADER:%.*]] 179; CHECK: header: 180; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ] 181; CHECK-NEXT: [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2 182; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]] 183; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]] 184; CHECK: latch: 185; CHECK-NEXT: [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1 186; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]] 187; CHECK-NEXT: br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]] 188; CHECK: header.1: 189; CHECK-NEXT: [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2 190; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]] 191; CHECK-NEXT: br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]] 192; CHECK: latch.1: 193; CHECK-NEXT: [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1 194; CHECK-NEXT: [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]] 195; CHECK-NEXT: br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]] 196; CHECK: header.2: 197; CHECK-NEXT: [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2 198; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]] 199; CHECK-NEXT: br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]] 200; CHECK: latch.2: 201; CHECK-NEXT: [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1 202; CHECK-NEXT: [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]] 203; CHECK-NEXT: br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]] 204; CHECK: header.3: 205; CHECK-NEXT: [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2 206; CHECK-NEXT: [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]] 207; CHECK-NEXT: br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]] 208; CHECK: latch.3: 209; CHECK-NEXT: [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1 210; CHECK-NEXT: [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]] 211; CHECK-NEXT: br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP3:![0-9]+]] 212; CHECK: headerexit: 213; CHECK-NEXT: br label [[EXITSUCC:%.*]] 214; CHECK: latchexit: 215; CHECK-NEXT: [[SHFTPHI:%.*]] = phi i64 [ [[SHFT]], [[LATCH]] ], [ [[SHFT_1]], [[LATCH_1]] ], [ [[SHFT_2]], [[LATCH_2]] ], [ [[SHFT_3]], [[LATCH_3]] ] 216; CHECK-NEXT: ret i64 [[SHFTPHI]] 217; CHECK: exitsucc: 218; CHECK-NEXT: ret i64 96 219; 220entry: 221 br label %preheader 222 223preheader: ; preds = %bb 224 %trip = zext i32 %n to i64 225 br label %header 226 227header: ; preds = %latch, %preheader 228 %iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ] 229 %add.iv = add nuw nsw i64 %iv, 2 230 %cmp1 = icmp ult i64 %add.iv, %trip 231 br i1 %cmp1, label %latch, label %headerexit 232 233latch: ; preds = %header 234 %shft = ashr i64 %add.iv, 1 235 %cmp2 = icmp ult i64 %shft, %trip 236 br i1 %cmp2, label %header, label %latchexit 237 238headerexit: ; preds = %header 239 br label %exitsucc 240 241latchexit: ; preds = %latch 242 %shftphi = phi i64 [ %shft, %latch ] 243 ret i64 %shftphi 244 245exitsucc: ; preds = %headerexit 246 ret i64 96 247} 248 249; exit block (%default) has an exiting block and another exit block as predecessors. 250define void @test4(i16 %c3) { 251; CHECK-LABEL: @test4( 252; CHECK-NEXT: preheader: 253; CHECK-NEXT: [[C1:%.*]] = zext i32 undef to i64 254; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[C1]], i64 1) 255; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[UMAX]], -1 256; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[UMAX]], 3 257; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 258; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[HEADER_PROL_PREHEADER:%.*]], label [[HEADER_PROL_LOOPEXIT:%.*]] 259; CHECK: header.prol.preheader: 260; CHECK-NEXT: br label [[HEADER_PROL:%.*]] 261; CHECK: header.prol: 262; CHECK-NEXT: [[INDVARS_IV_PROL:%.*]] = phi i64 [ 0, [[HEADER_PROL_PREHEADER]] ], [ [[INDVARS_IV_NEXT_PROL:%.*]], [[LATCH_PROL:%.*]] ] 263; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ 0, [[HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], [[LATCH_PROL]] ] 264; CHECK-NEXT: br label [[EXITING_PROL:%.*]] 265; CHECK: exiting.prol: 266; CHECK-NEXT: switch i16 [[C3:%.*]], label [[DEFAULT_LOOPEXIT_LOOPEXIT1:%.*]] [ 267; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT2:%.*]] 268; CHECK-NEXT: i16 95, label [[LATCH_PROL]] 269; CHECK-NEXT: ] 270; CHECK: latch.prol: 271; CHECK-NEXT: [[INDVARS_IV_NEXT_PROL]] = add nuw nsw i64 [[INDVARS_IV_PROL]], 1 272; CHECK-NEXT: [[C2_PROL:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_PROL]], [[C1]] 273; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1 274; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]] 275; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[HEADER_PROL]], label [[HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP4:![0-9]+]] 276; CHECK: header.prol.loopexit.unr-lcssa: 277; CHECK-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[LATCH_PROL]] ] 278; CHECK-NEXT: br label [[HEADER_PROL_LOOPEXIT]] 279; CHECK: header.prol.loopexit: 280; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[PREHEADER:%.*]] ], [ [[INDVARS_IV_UNR_PH]], [[HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ] 281; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 3 282; CHECK-NEXT: br i1 [[TMP1]], label [[LATCHEXIT:%.*]], label [[PREHEADER_NEW:%.*]] 283; CHECK: preheader.new: 284; CHECK-NEXT: br label [[HEADER:%.*]] 285; CHECK: header: 286; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ] 287; CHECK-NEXT: br label [[EXITING:%.*]] 288; CHECK: exiting: 289; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT:%.*]] [ 290; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT:%.*]] 291; CHECK-NEXT: i16 95, label [[LATCH:%.*]] 292; CHECK-NEXT: ] 293; CHECK: latch: 294; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1 295; CHECK-NEXT: br label [[EXITING_1:%.*]] 296; CHECK: exiting.1: 297; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [ 298; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]] 299; CHECK-NEXT: i16 95, label [[LATCH_1:%.*]] 300; CHECK-NEXT: ] 301; CHECK: latch.1: 302; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1 303; CHECK-NEXT: br label [[EXITING_2:%.*]] 304; CHECK: exiting.2: 305; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [ 306; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]] 307; CHECK-NEXT: i16 95, label [[LATCH_2:%.*]] 308; CHECK-NEXT: ] 309; CHECK: latch.2: 310; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1 311; CHECK-NEXT: br label [[EXITING_3:%.*]] 312; CHECK: exiting.3: 313; CHECK-NEXT: switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [ 314; CHECK-NEXT: i16 45, label [[OTHEREXIT_LOOPEXIT]] 315; CHECK-NEXT: i16 95, label [[LATCH_3]] 316; CHECK-NEXT: ] 317; CHECK: latch.3: 318; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1 319; CHECK-NEXT: [[C2_3:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_3]], [[C1]] 320; CHECK-NEXT: br i1 [[C2_3]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP5:![0-9]+]] 321; CHECK: latchexit.unr-lcssa: 322; CHECK-NEXT: br label [[LATCHEXIT]] 323; CHECK: latchexit: 324; CHECK-NEXT: ret void 325; CHECK: default.loopexit.loopexit: 326; CHECK-NEXT: br label [[DEFAULT_LOOPEXIT:%.*]] 327; CHECK: default.loopexit.loopexit1: 328; CHECK-NEXT: br label [[DEFAULT_LOOPEXIT]] 329; CHECK: default.loopexit: 330; CHECK-NEXT: br label [[DEFAULT:%.*]] 331; CHECK: default: 332; CHECK-NEXT: ret void 333; CHECK: otherexit.loopexit: 334; CHECK-NEXT: br label [[OTHEREXIT:%.*]] 335; CHECK: otherexit.loopexit2: 336; CHECK-NEXT: br label [[OTHEREXIT]] 337; CHECK: otherexit: 338; CHECK-NEXT: br label [[DEFAULT]] 339; 340preheader: 341 %c1 = zext i32 undef to i64 342 br label %header 343 344header: ; preds = %latch, %preheader 345 %indvars.iv = phi i64 [ 0, %preheader ], [ %indvars.iv.next, %latch ] 346 br label %exiting 347 348exiting: ; preds = %header 349 switch i16 %c3, label %default [ 350 i16 45, label %otherexit 351 i16 95, label %latch 352 ] 353 354latch: ; preds = %exiting 355 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 356 %c2 = icmp ult i64 %indvars.iv.next, %c1 357 br i1 %c2, label %header, label %latchexit 358 359latchexit: ; preds = %latch 360 ret void 361 362default: ; preds = %otherexit, %exiting 363 ret void 364 365otherexit: ; preds = %exiting 366 br label %default 367} 368 369; exit block (%exitB) has an exiting block and another exit block as predecessors. 370; exiting block comes from inner loop. 371define void @test5() { 372; CHECK-LABEL: @test5( 373; CHECK-NEXT: bb: 374; CHECK-NEXT: [[TMP:%.*]] = icmp sgt i32 undef, 79 375; CHECK-NEXT: br i1 [[TMP]], label [[OUTERLATCHEXIT:%.*]], label [[BB1:%.*]] 376; CHECK: bb1: 377; CHECK-NEXT: br i1 false, label [[OUTERH_PROL_PREHEADER:%.*]], label [[OUTERH_PROL_LOOPEXIT:%.*]] 378; CHECK: outerH.prol.preheader: 379; CHECK-NEXT: br label [[OUTERH_PROL:%.*]] 380; CHECK: outerH.prol: 381; CHECK-NEXT: [[TMP4_PROL:%.*]] = phi i32 [ [[TMP6_PROL:%.*]], [[OUTERLATCH_PROL:%.*]] ], [ undef, [[OUTERH_PROL_PREHEADER]] ] 382; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i32 [ 0, [[OUTERH_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], [[OUTERLATCH_PROL]] ] 383; CHECK-NEXT: br label [[INNERH_PROL:%.*]] 384; CHECK: innerH.prol: 385; CHECK-NEXT: [[C1_PROL:%.*]] = call i1 @unknown(i32 0) 386; CHECK-NEXT: br i1 [[C1_PROL]], label [[INNEREXITING_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1:%.*]] 387; CHECK: innerexiting.prol: 388; CHECK-NEXT: [[C2_PROL:%.*]] = call i1 @unknown(i32 0) 389; CHECK-NEXT: br i1 [[C2_PROL]], label [[INNERLATCH_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2:%.*]] 390; CHECK: innerLatch.prol: 391; CHECK-NEXT: br i1 false, label [[INNERH_1_PROL:%.*]], label [[OUTERLATCH_PROL]] 392; CHECK: innerH.1.prol: 393; CHECK-NEXT: [[C1_1_PROL:%.*]] = call i1 @unknown(i32 0) 394; CHECK-NEXT: br i1 [[C1_1_PROL]], label [[INNEREXITING_1_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]] 395; CHECK: innerexiting.1.prol: 396; CHECK-NEXT: [[C2_1_PROL:%.*]] = call i1 @unknown(i32 0) 397; CHECK-NEXT: br i1 [[C2_1_PROL]], label [[INNERLATCH_1_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]] 398; CHECK: innerLatch.1.prol: 399; CHECK-NEXT: br i1 false, label [[INNERH_2_PROL:%.*]], label [[OUTERLATCH_PROL]] 400; CHECK: innerH.2.prol: 401; CHECK-NEXT: [[C1_2_PROL:%.*]] = call i1 @unknown(i32 0) 402; CHECK-NEXT: br i1 [[C1_2_PROL]], label [[INNEREXITING_2_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]] 403; CHECK: innerexiting.2.prol: 404; CHECK-NEXT: [[C2_2_PROL:%.*]] = call i1 @unknown(i32 0) 405; CHECK-NEXT: br i1 [[C2_2_PROL]], label [[INNERLATCH_2_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]] 406; CHECK: innerLatch.2.prol: 407; CHECK-NEXT: br i1 false, label [[INNERH_3_PROL:%.*]], label [[OUTERLATCH_PROL]] 408; CHECK: innerH.3.prol: 409; CHECK-NEXT: [[C1_3_PROL:%.*]] = call i1 @unknown(i32 0) 410; CHECK-NEXT: br i1 [[C1_3_PROL]], label [[INNEREXITING_3_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]] 411; CHECK: innerexiting.3.prol: 412; CHECK-NEXT: [[C2_3_PROL:%.*]] = call i1 @unknown(i32 0) 413; CHECK-NEXT: br i1 [[C2_3_PROL]], label [[INNERLATCH_3_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]] 414; CHECK: innerLatch.3.prol: 415; CHECK-NEXT: br i1 false, label [[INNERH_PROL]], label [[OUTERLATCH_PROL]], !llvm.loop [[LOOP6:![0-9]+]] 416; CHECK: outerLatch.prol: 417; CHECK-NEXT: [[TMP6_PROL]] = add i32 [[TMP4_PROL]], 1 418; CHECK-NEXT: [[TMP7_PROL:%.*]] = icmp sgt i32 [[TMP6_PROL]], 79 419; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i32 [[PROL_ITER]], 1 420; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i32 [[PROL_ITER_NEXT]], 0 421; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[OUTERH_PROL]], label [[OUTERH_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP7:![0-9]+]] 422; CHECK: outerH.prol.loopexit.unr-lcssa: 423; CHECK-NEXT: [[TMP4_UNR_PH:%.*]] = phi i32 [ [[TMP6_PROL]], [[OUTERLATCH_PROL]] ] 424; CHECK-NEXT: br label [[OUTERH_PROL_LOOPEXIT]] 425; CHECK: outerH.prol.loopexit: 426; CHECK-NEXT: [[TMP4_UNR:%.*]] = phi i32 [ undef, [[BB1]] ], [ [[TMP4_UNR_PH]], [[OUTERH_PROL_LOOPEXIT_UNR_LCSSA]] ] 427; CHECK-NEXT: br i1 false, label [[OUTERLATCHEXIT_LOOPEXIT:%.*]], label [[BB1_NEW:%.*]] 428; CHECK: bb1.new: 429; CHECK-NEXT: br label [[OUTERH:%.*]] 430; CHECK: outerH: 431; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP4_UNR]], [[BB1_NEW]] ], [ [[TMP6_3:%.*]], [[OUTERLATCH_3:%.*]] ] 432; CHECK-NEXT: br label [[INNERH:%.*]] 433; CHECK: innerH: 434; CHECK-NEXT: [[C1:%.*]] = call i1 @unknown(i32 0) 435; CHECK-NEXT: br i1 [[C1]], label [[INNEREXITING:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT:%.*]] 436; CHECK: innerexiting: 437; CHECK-NEXT: [[C2:%.*]] = call i1 @unknown(i32 0) 438; CHECK-NEXT: br i1 [[C2]], label [[INNERLATCH:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT:%.*]] 439; CHECK: innerLatch: 440; CHECK-NEXT: br i1 false, label [[INNERH_1:%.*]], label [[OUTERLATCH:%.*]] 441; CHECK: innerH.1: 442; CHECK-NEXT: [[C1_1:%.*]] = call i1 @unknown(i32 0) 443; CHECK-NEXT: br i1 [[C1_1]], label [[INNEREXITING_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]] 444; CHECK: innerexiting.1: 445; CHECK-NEXT: [[C2_1:%.*]] = call i1 @unknown(i32 0) 446; CHECK-NEXT: br i1 [[C2_1]], label [[INNERLATCH_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]] 447; CHECK: innerLatch.1: 448; CHECK-NEXT: br i1 false, label [[INNERH_2:%.*]], label [[OUTERLATCH]] 449; CHECK: innerH.2: 450; CHECK-NEXT: [[C1_2:%.*]] = call i1 @unknown(i32 0) 451; CHECK-NEXT: br i1 [[C1_2]], label [[INNEREXITING_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]] 452; CHECK: innerexiting.2: 453; CHECK-NEXT: [[C2_2:%.*]] = call i1 @unknown(i32 0) 454; CHECK-NEXT: br i1 [[C2_2]], label [[INNERLATCH_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]] 455; CHECK: innerLatch.2: 456; CHECK-NEXT: br i1 false, label [[INNERH_3:%.*]], label [[OUTERLATCH]] 457; CHECK: innerH.3: 458; CHECK-NEXT: [[C1_3:%.*]] = call i1 @unknown(i32 0) 459; CHECK-NEXT: br i1 [[C1_3]], label [[INNEREXITING_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]] 460; CHECK: innerexiting.3: 461; CHECK-NEXT: [[C2_3:%.*]] = call i1 @unknown(i32 0) 462; CHECK-NEXT: br i1 [[C2_3]], label [[INNERLATCH_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]] 463; CHECK: innerLatch.3: 464; CHECK-NEXT: br i1 false, label [[INNERH]], label [[OUTERLATCH]], !llvm.loop [[LOOP6]] 465; CHECK: outerLatch: 466; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1 467; CHECK-NEXT: br label [[INNERH_14:%.*]] 468; CHECK: innerH.14: 469; CHECK-NEXT: [[C1_13:%.*]] = call i1 @unknown(i32 0) 470; CHECK-NEXT: br i1 [[C1_13]], label [[INNEREXITING_16:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18:%.*]] 471; CHECK: innerexiting.16: 472; CHECK-NEXT: [[C2_15:%.*]] = call i1 @unknown(i32 0) 473; CHECK-NEXT: br i1 [[C2_15]], label [[INNERLATCH_17:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19:%.*]] 474; CHECK: innerLatch.17: 475; CHECK-NEXT: br i1 false, label [[INNERH_1_1:%.*]], label [[OUTERLATCH_1:%.*]] 476; CHECK: innerH.1.1: 477; CHECK-NEXT: [[C1_1_1:%.*]] = call i1 @unknown(i32 0) 478; CHECK-NEXT: br i1 [[C1_1_1]], label [[INNEREXITING_1_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18]] 479; CHECK: innerexiting.1.1: 480; CHECK-NEXT: [[C2_1_1:%.*]] = call i1 @unknown(i32 0) 481; CHECK-NEXT: br i1 [[C2_1_1]], label [[INNERLATCH_1_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19]] 482; CHECK: innerLatch.1.1: 483; CHECK-NEXT: br i1 false, label [[INNERH_2_1:%.*]], label [[OUTERLATCH_1]] 484; CHECK: innerH.2.1: 485; CHECK-NEXT: [[C1_2_1:%.*]] = call i1 @unknown(i32 0) 486; CHECK-NEXT: br i1 [[C1_2_1]], label [[INNEREXITING_2_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18]] 487; CHECK: innerexiting.2.1: 488; CHECK-NEXT: [[C2_2_1:%.*]] = call i1 @unknown(i32 0) 489; CHECK-NEXT: br i1 [[C2_2_1]], label [[INNERLATCH_2_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19]] 490; CHECK: innerLatch.2.1: 491; CHECK-NEXT: br i1 false, label [[INNERH_3_1:%.*]], label [[OUTERLATCH_1]] 492; CHECK: innerH.3.1: 493; CHECK-NEXT: [[C1_3_1:%.*]] = call i1 @unknown(i32 0) 494; CHECK-NEXT: br i1 [[C1_3_1]], label [[INNEREXITING_3_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT18]] 495; CHECK: innerexiting.3.1: 496; CHECK-NEXT: [[C2_3_1:%.*]] = call i1 @unknown(i32 0) 497; CHECK-NEXT: br i1 [[C2_3_1]], label [[INNERLATCH_3_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT19]] 498; CHECK: innerLatch.3.1: 499; CHECK-NEXT: br i1 false, label [[INNERH_14]], label [[OUTERLATCH_1]], !llvm.loop [[LOOP6]] 500; CHECK: outerLatch.1: 501; CHECK-NEXT: [[TMP6_1:%.*]] = add i32 [[TMP6]], 1 502; CHECK-NEXT: br label [[INNERH_29:%.*]] 503; CHECK: innerH.29: 504; CHECK-NEXT: [[C1_28:%.*]] = call i1 @unknown(i32 0) 505; CHECK-NEXT: br i1 [[C1_28]], label [[INNEREXITING_211:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20:%.*]] 506; CHECK: innerexiting.211: 507; CHECK-NEXT: [[C2_210:%.*]] = call i1 @unknown(i32 0) 508; CHECK-NEXT: br i1 [[C2_210]], label [[INNERLATCH_212:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21:%.*]] 509; CHECK: innerLatch.212: 510; CHECK-NEXT: br i1 false, label [[INNERH_1_2:%.*]], label [[OUTERLATCH_2:%.*]] 511; CHECK: innerH.1.2: 512; CHECK-NEXT: [[C1_1_2:%.*]] = call i1 @unknown(i32 0) 513; CHECK-NEXT: br i1 [[C1_1_2]], label [[INNEREXITING_1_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20]] 514; CHECK: innerexiting.1.2: 515; CHECK-NEXT: [[C2_1_2:%.*]] = call i1 @unknown(i32 0) 516; CHECK-NEXT: br i1 [[C2_1_2]], label [[INNERLATCH_1_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21]] 517; CHECK: innerLatch.1.2: 518; CHECK-NEXT: br i1 false, label [[INNERH_2_2:%.*]], label [[OUTERLATCH_2]] 519; CHECK: innerH.2.2: 520; CHECK-NEXT: [[C1_2_2:%.*]] = call i1 @unknown(i32 0) 521; CHECK-NEXT: br i1 [[C1_2_2]], label [[INNEREXITING_2_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20]] 522; CHECK: innerexiting.2.2: 523; CHECK-NEXT: [[C2_2_2:%.*]] = call i1 @unknown(i32 0) 524; CHECK-NEXT: br i1 [[C2_2_2]], label [[INNERLATCH_2_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21]] 525; CHECK: innerLatch.2.2: 526; CHECK-NEXT: br i1 false, label [[INNERH_3_2:%.*]], label [[OUTERLATCH_2]] 527; CHECK: innerH.3.2: 528; CHECK-NEXT: [[C1_3_2:%.*]] = call i1 @unknown(i32 0) 529; CHECK-NEXT: br i1 [[C1_3_2]], label [[INNEREXITING_3_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT20]] 530; CHECK: innerexiting.3.2: 531; CHECK-NEXT: [[C2_3_2:%.*]] = call i1 @unknown(i32 0) 532; CHECK-NEXT: br i1 [[C2_3_2]], label [[INNERLATCH_3_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT21]] 533; CHECK: innerLatch.3.2: 534; CHECK-NEXT: br i1 false, label [[INNERH_29]], label [[OUTERLATCH_2]], !llvm.loop [[LOOP6]] 535; CHECK: outerLatch.2: 536; CHECK-NEXT: [[TMP6_2:%.*]] = add i32 [[TMP6_1]], 1 537; CHECK-NEXT: br label [[INNERH_314:%.*]] 538; CHECK: innerH.314: 539; CHECK-NEXT: [[C1_313:%.*]] = call i1 @unknown(i32 0) 540; CHECK-NEXT: br i1 [[C1_313]], label [[INNEREXITING_316:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22:%.*]] 541; CHECK: innerexiting.316: 542; CHECK-NEXT: [[C2_315:%.*]] = call i1 @unknown(i32 0) 543; CHECK-NEXT: br i1 [[C2_315]], label [[INNERLATCH_317:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23:%.*]] 544; CHECK: innerLatch.317: 545; CHECK-NEXT: br i1 false, label [[INNERH_1_3:%.*]], label [[OUTERLATCH_3]] 546; CHECK: innerH.1.3: 547; CHECK-NEXT: [[C1_1_3:%.*]] = call i1 @unknown(i32 0) 548; CHECK-NEXT: br i1 [[C1_1_3]], label [[INNEREXITING_1_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22]] 549; CHECK: innerexiting.1.3: 550; CHECK-NEXT: [[C2_1_3:%.*]] = call i1 @unknown(i32 0) 551; CHECK-NEXT: br i1 [[C2_1_3]], label [[INNERLATCH_1_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23]] 552; CHECK: innerLatch.1.3: 553; CHECK-NEXT: br i1 false, label [[INNERH_2_3:%.*]], label [[OUTERLATCH_3]] 554; CHECK: innerH.2.3: 555; CHECK-NEXT: [[C1_2_3:%.*]] = call i1 @unknown(i32 0) 556; CHECK-NEXT: br i1 [[C1_2_3]], label [[INNEREXITING_2_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22]] 557; CHECK: innerexiting.2.3: 558; CHECK-NEXT: [[C2_2_3:%.*]] = call i1 @unknown(i32 0) 559; CHECK-NEXT: br i1 [[C2_2_3]], label [[INNERLATCH_2_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23]] 560; CHECK: innerLatch.2.3: 561; CHECK-NEXT: br i1 false, label [[INNERH_3_3:%.*]], label [[OUTERLATCH_3]] 562; CHECK: innerH.3.3: 563; CHECK-NEXT: [[C1_3_3:%.*]] = call i1 @unknown(i32 0) 564; CHECK-NEXT: br i1 [[C1_3_3]], label [[INNEREXITING_3_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT22]] 565; CHECK: innerexiting.3.3: 566; CHECK-NEXT: [[C2_3_3:%.*]] = call i1 @unknown(i32 0) 567; CHECK-NEXT: br i1 [[C2_3_3]], label [[INNERLATCH_3_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT23]] 568; CHECK: innerLatch.3.3: 569; CHECK-NEXT: br i1 false, label [[INNERH_314]], label [[OUTERLATCH_3]], !llvm.loop [[LOOP6]] 570; CHECK: outerLatch.3: 571; CHECK-NEXT: [[TMP6_3]] = add i32 [[TMP6_2]], 1 572; CHECK-NEXT: [[TMP7_3:%.*]] = icmp sgt i32 [[TMP6_3]], 79 573; CHECK-NEXT: br i1 [[TMP7_3]], label [[OUTERLATCHEXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[OUTERH]], !llvm.loop [[LOOP8:![0-9]+]] 574; CHECK: outerLatchExit.loopexit.unr-lcssa: 575; CHECK-NEXT: br label [[OUTERLATCHEXIT_LOOPEXIT]] 576; CHECK: outerLatchExit.loopexit: 577; CHECK-NEXT: br label [[OUTERLATCHEXIT]] 578; CHECK: outerLatchExit: 579; CHECK-NEXT: ret void 580; CHECK: exitB.loopexit.loopexit.loopexit: 581; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT:%.*]] 582; CHECK: exitB.loopexit.loopexit.loopexit19: 583; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT]] 584; CHECK: exitB.loopexit.loopexit.loopexit21: 585; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT]] 586; CHECK: exitB.loopexit.loopexit.loopexit23: 587; CHECK-NEXT: br label [[EXITB_LOOPEXIT_LOOPEXIT]] 588; CHECK: exitB.loopexit.loopexit: 589; CHECK-NEXT: br label [[EXITB_LOOPEXIT:%.*]] 590; CHECK: exitB.loopexit.loopexit2: 591; CHECK-NEXT: br label [[EXITB_LOOPEXIT]] 592; CHECK: exitB.loopexit: 593; CHECK-NEXT: br label [[EXITB:%.*]] 594; CHECK: exitB: 595; CHECK-NEXT: ret void 596; CHECK: otherexitB.loopexit.loopexit: 597; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT:%.*]] 598; CHECK: otherexitB.loopexit.loopexit18: 599; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT]] 600; CHECK: otherexitB.loopexit.loopexit20: 601; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT]] 602; CHECK: otherexitB.loopexit.loopexit22: 603; CHECK-NEXT: br label [[OTHEREXITB_LOOPEXIT]] 604; CHECK: otherexitB.loopexit: 605; CHECK-NEXT: br label [[OTHEREXITB:%.*]] 606; CHECK: otherexitB.loopexit1: 607; CHECK-NEXT: br label [[OTHEREXITB]] 608; CHECK: otherexitB: 609; CHECK-NEXT: br label [[EXITB]] 610; 611bb: 612 %tmp = icmp sgt i32 undef, 79 613 br i1 %tmp, label %outerLatchExit, label %bb1 614 615bb1: ; preds = %bb 616 br label %outerH 617 618outerH: ; preds = %outerLatch, %bb1 619 %tmp4 = phi i32 [ %tmp6, %outerLatch ], [ undef, %bb1 ] 620 br label %innerH 621 622innerH: ; preds = %innerLatch, %outerH 623 %c1 = call i1 @unknown(i32 0) 624 br i1 %c1, label %innerexiting, label %otherexitB 625 626innerexiting: ; preds = %innerH 627 %c2 = call i1 @unknown(i32 0) 628 br i1 %c2, label %innerLatch, label %exitB 629 630innerLatch: ; preds = %innerexiting 631 %tmp13 = fcmp olt double undef, 2.000000e+00 632 br i1 %tmp13, label %innerH, label %outerLatch 633 634outerLatch: ; preds = %innerLatch 635 %tmp6 = add i32 %tmp4, 1 636 %tmp7 = icmp sgt i32 %tmp6, 79 637 br i1 %tmp7, label %outerLatchExit, label %outerH 638 639outerLatchExit: ; preds = %outerLatch, %bb 640 ret void 641 642exitB: ; preds = %innerexiting, %otherexitB 643 ret void 644 645otherexitB: ; preds = %innerH 646 br label %exitB 647 648} 649 650; Blocks reachable from exits (not_zero44) have the IDom as the block within the loop (Header). 651; Update the IDom to the preheader. 652define void @test6(i64 %start) { 653; CHECK-LABEL: @test6( 654; CHECK-NEXT: entry: 655; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[START:%.*]], 2 656; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP0]], i64 616) 657; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[SMAX]], -1 658; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START]] 659; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 1 660; CHECK-NEXT: [[TMP4:%.*]] = add nuw i64 [[TMP3]], 1 661; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP4]], 3 662; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 663; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[HEADER_PROL_PREHEADER:%.*]], label [[HEADER_PROL_LOOPEXIT:%.*]] 664; CHECK: header.prol.preheader: 665; CHECK-NEXT: br label [[HEADER_PROL:%.*]] 666; CHECK: header.prol: 667; CHECK-NEXT: [[INDVARS_IV_PROL:%.*]] = phi i64 [ [[START]], [[HEADER_PROL_PREHEADER]] ], [ [[INDVARS_IV_NEXT_PROL:%.*]], [[LATCH_PROL:%.*]] ] 668; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ 0, [[HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], [[LATCH_PROL]] ] 669; CHECK-NEXT: [[IV_I32_PROL:%.*]] = trunc i64 [[INDVARS_IV_PROL]] to i32 670; CHECK-NEXT: [[C1_PROL:%.*]] = call i1 @unknown(i32 [[IV_I32_PROL]]) 671; CHECK-NEXT: br i1 [[C1_PROL]], label [[LATCH_PROL]], label [[OTHEREXIT_LOOPEXIT1:%.*]] 672; CHECK: latch.prol: 673; CHECK-NEXT: [[INDVARS_IV_NEXT_PROL]] = add nsw i64 [[INDVARS_IV_PROL]], 2 674; CHECK-NEXT: [[TMP5:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_PROL]], 616 675; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1 676; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]] 677; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[HEADER_PROL]], label [[HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP9:![0-9]+]] 678; CHECK: header.prol.loopexit.unr-lcssa: 679; CHECK-NEXT: [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[LATCH_PROL]] ] 680; CHECK-NEXT: br label [[HEADER_PROL_LOOPEXIT]] 681; CHECK: header.prol.loopexit: 682; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ [[START]], [[ENTRY:%.*]] ], [ [[INDVARS_IV_UNR_PH]], [[HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ] 683; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i64 [[TMP3]], 3 684; CHECK-NEXT: br i1 [[TMP6]], label [[LATCHEXIT:%.*]], label [[ENTRY_NEW:%.*]] 685; CHECK: entry.new: 686; CHECK-NEXT: br label [[HEADER:%.*]] 687; CHECK: header: 688; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[ENTRY_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ] 689; CHECK-NEXT: [[IV_I32:%.*]] = trunc i64 [[INDVARS_IV]] to i32 690; CHECK-NEXT: [[C1:%.*]] = call i1 @unknown(i32 [[IV_I32]]) 691; CHECK-NEXT: br i1 [[C1]], label [[LATCH:%.*]], label [[OTHEREXIT_LOOPEXIT:%.*]] 692; CHECK: latch: 693; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nsw i64 [[INDVARS_IV]], 2 694; CHECK-NEXT: [[IV_I32_1:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 695; CHECK-NEXT: [[C1_1:%.*]] = call i1 @unknown(i32 [[IV_I32_1]]) 696; CHECK-NEXT: br i1 [[C1_1]], label [[LATCH_1:%.*]], label [[OTHEREXIT_LOOPEXIT]] 697; CHECK: latch.1: 698; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nsw i64 [[INDVARS_IV_NEXT]], 2 699; CHECK-NEXT: [[IV_I32_2:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32 700; CHECK-NEXT: [[C1_2:%.*]] = call i1 @unknown(i32 [[IV_I32_2]]) 701; CHECK-NEXT: br i1 [[C1_2]], label [[LATCH_2:%.*]], label [[OTHEREXIT_LOOPEXIT]] 702; CHECK: latch.2: 703; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nsw i64 [[INDVARS_IV_NEXT_1]], 2 704; CHECK-NEXT: [[IV_I32_3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32 705; CHECK-NEXT: [[C1_3:%.*]] = call i1 @unknown(i32 [[IV_I32_3]]) 706; CHECK-NEXT: br i1 [[C1_3]], label [[LATCH_3]], label [[OTHEREXIT_LOOPEXIT]] 707; CHECK: latch.3: 708; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nsw i64 [[INDVARS_IV_NEXT_2]], 2 709; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_3]], 616 710; CHECK-NEXT: br i1 [[TMP7]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP10:![0-9]+]] 711; CHECK: latchexit.unr-lcssa: 712; CHECK-NEXT: br label [[LATCHEXIT]] 713; CHECK: latchexit: 714; CHECK-NEXT: br label [[LATCHEXITSUCC:%.*]] 715; CHECK: otherexit.loopexit: 716; CHECK-NEXT: br label [[OTHEREXIT:%.*]] 717; CHECK: otherexit.loopexit1: 718; CHECK-NEXT: br label [[OTHEREXIT]] 719; CHECK: otherexit: 720; CHECK-NEXT: br label [[OTHEREXITSUCC:%.*]] 721; CHECK: otherexitsucc: 722; CHECK-NEXT: br label [[NOT_ZERO44:%.*]] 723; CHECK: not_zero44: 724; CHECK-NEXT: unreachable 725; CHECK: latchexitsucc: 726; CHECK-NEXT: br label [[NOT_ZERO44]] 727; 728entry: 729 br label %header 730 731header: ; preds = %latch, %entry 732 %indvars.iv = phi i64 [ %start, %entry ], [ %indvars.iv.next, %latch ] 733 %iv.i32 = trunc i64 %indvars.iv to i32 734 %c1 = call i1 @unknown(i32 %iv.i32) 735 br i1 %c1, label %latch, label %otherexit 736 737latch: ; preds = %header 738 %indvars.iv.next = add nsw i64 %indvars.iv, 2 739 %0 = icmp slt i64 %indvars.iv.next, 616 740 br i1 %0, label %header, label %latchexit 741 742latchexit: ; preds = %latch 743 br label %latchexitsucc 744 745otherexit: ; preds = %header 746 br label %otherexitsucc 747 748otherexitsucc: ; preds = %otherexit 749 br label %not_zero44 750 751not_zero44: ; preds = %latchexitsucc, %otherexitsucc 752 unreachable 753 754latchexitsucc: ; preds = %latchexit 755 br label %not_zero44 756} 757 758