1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -march=amdgcn -mcpu=bonaire -loop-reduce -S < %s | FileCheck %s 3 4; Test various conditions where OptimizeLoopTermCond doesn't look at a 5; memory instruction use and fails to find the address space. 6 7target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" 8 9define amdgpu_kernel void @local_cmp_user(i32 %arg0) nounwind { 10; CHECK-LABEL: @local_cmp_user( 11; CHECK-NEXT: entry: 12; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1 13; CHECK-NEXT: br label [[BB11:%.*]] 14; CHECK: bb11: 15; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i32 [ [[LSR_IV_NEXT3:%.*]], [[BB:%.*]] ], [ -2, [[ENTRY:%.*]] ] 16; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ] 17; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1 18; CHECK-NEXT: [[LSR_IV_NEXT3]] = add i32 [[LSR_IV2]], 2 19; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0 20; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]] 21; CHECK: bb: 22; CHECK-NEXT: [[T:%.*]] = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(3)* undef, align 4 23; CHECK-NEXT: [[T1:%.*]] = ptrtoint i8 addrspace(3)* [[T]] to i32 24; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[T1]] 25; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to i8 addrspace(3)* 26; CHECK-NEXT: [[TMP:%.*]] = inttoptr i32 [[LSR_IV_NEXT3]] to i8 addrspace(3)* 27; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 addrspace(3)* [[TMP2]], [[TMP]] 28; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]] 29; CHECK: bb13: 30; CHECK-NEXT: unreachable 31; 32entry: 33 br label %bb11 34 35bb11: ; preds = %bb, %entry 36 %i = phi i32 [ 0, %entry ], [ %i.next, %bb ] 37 %ii = shl i32 %i, 1 38 %c0 = icmp eq i32 %i, %arg0 39 br i1 %c0, label %bb13, label %bb 40 41bb: ; preds = %bb11 42 %t = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(3)* undef, align 4 43 %p = getelementptr i8, i8 addrspace(3)* %t, i32 %ii 44 %c1 = icmp ne i8 addrspace(3)* %p, null 45 %i.next = add i32 %i, 1 46 br i1 %c1, label %bb11, label %bb13 47 48bb13: ; preds = %bb, %bb11 49 unreachable 50} 51 52define amdgpu_kernel void @global_cmp_user(i64 %arg0) nounwind { 53; CHECK-LABEL: @global_cmp_user( 54; CHECK-NEXT: entry: 55; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[ARG0:%.*]], 1 56; CHECK-NEXT: br label [[BB11:%.*]] 57; CHECK: bb11: 58; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i64 [ [[LSR_IV_NEXT3:%.*]], [[BB:%.*]] ], [ -2, [[ENTRY:%.*]] ] 59; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ] 60; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1 61; CHECK-NEXT: [[LSR_IV_NEXT3]] = add i64 [[LSR_IV2]], 2 62; CHECK-NEXT: [[C0:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0 63; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]] 64; CHECK: bb: 65; CHECK-NEXT: [[T:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8 66; CHECK-NEXT: [[T1:%.*]] = ptrtoint i8 addrspace(1)* [[T]] to i64 67; CHECK-NEXT: [[TMP1:%.*]] = sub i64 0, [[T1]] 68; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to i8 addrspace(1)* 69; CHECK-NEXT: [[TMP:%.*]] = inttoptr i64 [[LSR_IV_NEXT3]] to i8 addrspace(1)* 70; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 addrspace(1)* [[TMP2]], [[TMP]] 71; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]] 72; CHECK: bb13: 73; CHECK-NEXT: unreachable 74; 75entry: 76 br label %bb11 77 78bb11: ; preds = %bb, %entry 79 %i = phi i64 [ 0, %entry ], [ %i.next, %bb ] 80 %ii = shl i64 %i, 1 81 %c0 = icmp eq i64 %i, %arg0 82 br i1 %c0, label %bb13, label %bb 83 84bb: ; preds = %bb11 85 %t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8 86 %p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii 87 %c1 = icmp ne i8 addrspace(1)* %p, null 88 %i.next = add i64 %i, 1 89 br i1 %c1, label %bb11, label %bb13 90 91bb13: ; preds = %bb, %bb11 92 unreachable 93} 94 95define amdgpu_kernel void @global_gep_user(i32 %arg0) nounwind { 96; CHECK-LABEL: @global_gep_user( 97; CHECK-NEXT: entry: 98; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1 99; CHECK-NEXT: br label [[BB11:%.*]] 100; CHECK: bb11: 101; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ 0, [[ENTRY:%.*]] ] 102; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ] 103; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1 104; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 2 105; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0 106; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]] 107; CHECK: bb: 108; CHECK-NEXT: [[T:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8 109; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[LSR_IV1]] to i64 110; CHECK-NEXT: [[P:%.*]] = getelementptr i8, i8 addrspace(1)* [[T]], i64 [[IDXPROM]] 111; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 addrspace(1)* [[P]], null 112; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]] 113; CHECK: bb13: 114; CHECK-NEXT: unreachable 115; 116entry: 117 br label %bb11 118 119bb11: ; preds = %bb, %entry 120 %i = phi i32 [ 0, %entry ], [ %i.next, %bb ] 121 %ii = shl i32 %i, 1 122 %c0 = icmp eq i32 %i, %arg0 123 br i1 %c0, label %bb13, label %bb 124 125bb: ; preds = %bb11 126 %t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8 127 %idxprom = sext i32 %ii to i64 128 %p = getelementptr i8, i8 addrspace(1)* %t, i64 %idxprom 129 %c1 = icmp ne i8 addrspace(1)* %p, null 130 %i.next = add i32 %i, 1 131 br i1 %c1, label %bb11, label %bb13 132 133bb13: ; preds = %bb, %bb11 134 unreachable 135} 136 137define amdgpu_kernel void @global_sext_scale_user(i32 %arg0) nounwind { 138; CHECK-LABEL: @global_sext_scale_user( 139; CHECK-NEXT: entry: 140; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1 141; CHECK-NEXT: br label [[BB11:%.*]] 142; CHECK: bb11: 143; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ 0, [[ENTRY:%.*]] ] 144; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ] 145; CHECK-NEXT: [[II_EXT:%.*]] = sext i32 [[LSR_IV1]] to i64 146; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1 147; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 2 148; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0 149; CHECK-NEXT: br i1 [[C0]], label [[BB13:%.*]], label [[BB]] 150; CHECK: bb: 151; CHECK-NEXT: [[T:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8 152; CHECK-NEXT: [[P:%.*]] = getelementptr i8, i8 addrspace(1)* [[T]], i64 [[II_EXT]] 153; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 addrspace(1)* [[P]], null 154; CHECK-NEXT: br i1 [[C1]], label [[BB11]], label [[BB13]] 155; CHECK: bb13: 156; CHECK-NEXT: unreachable 157; 158entry: 159 br label %bb11 160 161bb11: ; preds = %bb, %entry 162 %i = phi i32 [ 0, %entry ], [ %i.next, %bb ] 163 %ii = shl i32 %i, 1 164 %ii.ext = sext i32 %ii to i64 165 %c0 = icmp eq i32 %i, %arg0 166 br i1 %c0, label %bb13, label %bb 167 168bb: ; preds = %bb11 169 %t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8 170 %p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii.ext 171 %c1 = icmp ne i8 addrspace(1)* %p, null 172 %i.next = add i32 %i, 1 173 br i1 %c1, label %bb11, label %bb13 174 175bb13: ; preds = %bb, %bb11 176 unreachable 177} 178