1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; REQUIRES: asserts 3; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s 4; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s 5; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s 6 7target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1" 8 9; Make sure that we can eliminate a provably dead backedge. 10define i32 @dead_backedge_test_branch_loop(i32 %end) { 11; CHECK-LABEL: @dead_backedge_test_branch_loop( 12; CHECK-NEXT: preheader: 13; CHECK-NEXT: br label [[HEADER:%.*]] 14; CHECK: header: 15; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_BE:%.*]], [[HEADER_BACKEDGE:%.*]] ] 16; CHECK-NEXT: [[I_1:%.*]] = add i32 [[I]], 1 17; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[I_1]], 100 18; CHECK-NEXT: br i1 [[CMP1]], label [[HEADER_BACKEDGE]], label [[DEAD_BACKEDGE:%.*]] 19; CHECK: header.backedge: 20; CHECK-NEXT: [[I_BE]] = phi i32 [ [[I_1]], [[HEADER]] ], [ [[I_2:%.*]], [[DEAD_BACKEDGE]] ] 21; CHECK-NEXT: br label [[HEADER]] 22; CHECK: dead_backedge: 23; CHECK-NEXT: [[I_2]] = add i32 [[I_1]], 10 24; CHECK-NEXT: br i1 false, label [[HEADER_BACKEDGE]], label [[EXIT:%.*]] 25; CHECK: exit: 26; CHECK-NEXT: [[I_2_LCSSA:%.*]] = phi i32 [ [[I_2]], [[DEAD_BACKEDGE]] ] 27; CHECK-NEXT: ret i32 [[I_2_LCSSA]] 28; 29preheader: 30 br label %header 31 32header: 33 %i = phi i32 [0, %preheader], [%i.1, %header], [%i.2, %dead_backedge] 34 %i.1 = add i32 %i, 1 35 %cmp1 = icmp slt i32 %i.1, 100 36 br i1 %cmp1, label %header, label %dead_backedge 37 38dead_backedge: 39 %i.2 = add i32 %i.1, 10 40 br i1 false, label %header, label %exit 41 42exit: 43 ret i32 %i.2 44} 45 46; Make sure that we can eliminate a provably dead backedge with switch. 47define i32 @dead_backedge_test_switch_loop(i32 %end) { 48; CHECK-LABEL: @dead_backedge_test_switch_loop( 49; CHECK-NEXT: preheader: 50; CHECK-NEXT: br label [[HEADER:%.*]] 51; CHECK: header: 52; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_BE:%.*]], [[HEADER_BACKEDGE:%.*]] ] 53; CHECK-NEXT: [[I_1:%.*]] = add i32 [[I]], 1 54; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[I_1]], 100 55; CHECK-NEXT: br i1 [[CMP1]], label [[HEADER_BACKEDGE]], label [[DEAD_BACKEDGE:%.*]] 56; CHECK: header.backedge: 57; CHECK-NEXT: [[I_BE]] = phi i32 [ [[I_1]], [[HEADER]] ], [ [[I_2:%.*]], [[DEAD_BACKEDGE]] ] 58; CHECK-NEXT: br label [[HEADER]] 59; CHECK: dead_backedge: 60; CHECK-NEXT: [[I_2]] = add i32 [[I_1]], 10 61; CHECK-NEXT: switch i32 1, label [[EXIT:%.*]] [ 62; CHECK-NEXT: i32 0, label [[HEADER_BACKEDGE]] 63; CHECK-NEXT: ] 64; CHECK: exit: 65; CHECK-NEXT: [[I_2_LCSSA:%.*]] = phi i32 [ [[I_2]], [[DEAD_BACKEDGE]] ] 66; CHECK-NEXT: ret i32 [[I_2_LCSSA]] 67; 68preheader: 69 br label %header 70 71header: 72 %i = phi i32 [0, %preheader], [%i.1, %header], [%i.2, %dead_backedge] 73 %i.1 = add i32 %i, 1 74 %cmp1 = icmp slt i32 %i.1, 100 75 br i1 %cmp1, label %header, label %dead_backedge 76 77dead_backedge: 78 %i.2 = add i32 %i.1, 10 79 switch i32 1, label %exit [i32 0, label %header] 80 81exit: 82 ret i32 %i.2 83} 84 85; Check that we can eliminate a triangle. 86define i32 @dead_block_test_branch_loop(i32 %end) { 87; CHECK-LABEL: @dead_block_test_branch_loop( 88; CHECK-NEXT: preheader: 89; CHECK-NEXT: br label [[HEADER:%.*]] 90; CHECK: header: 91; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 92; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 93; CHECK: dead: 94; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 95; CHECK-NEXT: br label [[BACKEDGE]] 96; CHECK: backedge: 97; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 98; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 99; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 100; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 101; CHECK: exit: 102; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 103; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 104; 105preheader: 106 br label %header 107 108header: 109 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 110 br i1 true, label %backedge, label %dead 111 112dead: 113 %i.2 = add i32 %i, 1 114 br label %backedge 115 116backedge: 117 %i.1 = phi i32 [%i, %header], [%i.2, %dead] 118 %i.inc = add i32 %i.1, 1 119 %cmp = icmp slt i32 %i.inc, %end 120 br i1 %cmp, label %header, label %exit 121 122exit: 123 ret i32 %i.inc 124} 125 126; Check that we can eliminate dead branches of a switch. 127define i32 @dead_block_test_switch_loop(i32 %end) { 128; CHECK-LABEL: @dead_block_test_switch_loop( 129; CHECK-NEXT: preheader: 130; CHECK-NEXT: br label [[HEADER:%.*]] 131; CHECK: header: 132; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 133; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 134; CHECK-NEXT: i32 0, label [[DEAD]] 135; CHECK-NEXT: i32 1, label [[BACKEDGE]] 136; CHECK-NEXT: i32 2, label [[DEAD]] 137; CHECK-NEXT: ] 138; CHECK: dead: 139; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 140; CHECK-NEXT: br label [[BACKEDGE]] 141; CHECK: backedge: 142; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 143; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 144; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 145; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 146; CHECK: exit: 147; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 148; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 149; 150preheader: 151 br label %header 152 153header: 154 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 155 switch i32 1, label %dead [i32 0, label %dead 156 i32 1, label %backedge 157 i32 2, label %dead] 158 159dead: 160 %i.2 = add i32 %i, 1 161 br label %backedge 162 163backedge: 164 %i.1 = phi i32 [%i, %header], [%i.2, %dead] 165 %i.inc = add i32 %i.1, 1 166 %cmp = icmp slt i32 %i.inc, %end 167 br i1 %cmp, label %header, label %exit 168exit: 169 ret i32 %i.inc 170} 171 172; Check that we can eliminate several dead blocks. 173define i32 @dead_block_propogate_test_branch_loop(i32 %end) { 174; CHECK-LABEL: @dead_block_propogate_test_branch_loop( 175; CHECK-NEXT: preheader: 176; CHECK-NEXT: br label [[HEADER:%.*]] 177; CHECK: header: 178; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 179; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 180; CHECK: dead: 181; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 182; CHECK-NEXT: br label [[BACKEDGE]] 183; CHECK: backedge: 184; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 185; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 186; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 187; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 188; CHECK: exit: 189; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 190; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 191; 192preheader: 193 br label %header 194 195header: 196 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 197 br i1 true, label %backedge, label %dead 198 199dead: 200 %i.2 = add i32 %i, 1 201 br label %dummy 202 203dummy: 204 br label %backedge 205 206backedge: 207 %i.1 = phi i32 [%i, %header], [%i.2, %dummy] 208 %i.inc = add i32 %i.1, 1 209 %cmp = icmp slt i32 %i.inc, %end 210 br i1 %cmp, label %header, label %exit 211 212exit: 213 ret i32 %i.inc 214} 215 216; Check that we can eliminate several blocks while removing a switch. 217define i32 @dead_block_propogate_test_switch_loop(i32 %end) { 218; CHECK-LABEL: @dead_block_propogate_test_switch_loop( 219; CHECK-NEXT: preheader: 220; CHECK-NEXT: br label [[HEADER:%.*]] 221; CHECK: header: 222; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 223; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 224; CHECK-NEXT: i32 0, label [[DEAD]] 225; CHECK-NEXT: i32 1, label [[BACKEDGE]] 226; CHECK-NEXT: i32 2, label [[DEAD]] 227; CHECK-NEXT: ] 228; CHECK: dead: 229; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 230; CHECK-NEXT: br label [[BACKEDGE]] 231; CHECK: backedge: 232; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 233; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 234; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 235; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 236; CHECK: exit: 237; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 238; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 239; 240preheader: 241 br label %header 242 243header: 244 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 245 switch i32 1, label %dead [i32 0, label %dead 246 i32 1, label %backedge 247 i32 2, label %dead] 248 249dead: 250 %i.2 = add i32 %i, 1 251 br label %dummy 252 253dummy: 254 br label %backedge 255 256backedge: 257 %i.1 = phi i32 [%i, %header], [%i.2, %dummy] 258 %i.inc = add i32 %i.1, 1 259 %cmp = icmp slt i32 %i.inc, %end 260 br i1 %cmp, label %header, label %exit 261 262exit: 263 ret i32 %i.inc 264} 265 266; Check that we preserve static reachibility of a dead exit block while deleting 267; a branch. 268define i32 @dead_exit_test_branch_loop(i32 %end) { 269; CHECK-LABEL: @dead_exit_test_branch_loop( 270; CHECK-NEXT: preheader: 271; CHECK-NEXT: br label [[HEADER:%.*]] 272; CHECK: header: 273; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 274; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 275; CHECK: dead: 276; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[HEADER]] ] 277; CHECK-NEXT: br label [[DUMMY:%.*]] 278; CHECK: dummy: 279; CHECK-NEXT: br label [[EXIT:%.*]] 280; CHECK: backedge: 281; CHECK-NEXT: [[I_INC]] = add i32 [[I]], 1 282; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 283; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT_LOOPEXIT:%.*]] 284; CHECK: exit.loopexit: 285; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 286; CHECK-NEXT: br label [[EXIT]] 287; CHECK: exit: 288; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I_LCSSA]], [[DUMMY]] ], [ [[I_INC_LCSSA]], [[EXIT_LOOPEXIT]] ] 289; CHECK-NEXT: ret i32 [[I_1]] 290; 291preheader: 292 br label %header 293 294header: 295 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 296 br i1 true, label %backedge, label %dead 297 298dead: 299 br label %dummy 300 301dummy: 302 br label %exit 303 304backedge: 305 %i.inc = add i32 %i, 1 306 %cmp = icmp slt i32 %i.inc, %end 307 br i1 %cmp, label %header, label %exit 308 309exit: 310 %i.1 = phi i32 [%i.inc, %backedge], [%i, %dummy] 311 ret i32 %i.1 312} 313 314; Check that we preserve static reachibility of a dead exit block while deleting 315; a switch. 316define i32 @dead_exit_test_switch_loop(i32 %end) { 317; CHECK-LABEL: @dead_exit_test_switch_loop( 318; CHECK-NEXT: preheader: 319; CHECK-NEXT: br label [[HEADER:%.*]] 320; CHECK: header: 321; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 322; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 323; CHECK-NEXT: i32 0, label [[DEAD]] 324; CHECK-NEXT: i32 1, label [[BACKEDGE]] 325; CHECK-NEXT: i32 2, label [[DEAD]] 326; CHECK-NEXT: ] 327; CHECK: dead: 328; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I]], [[HEADER]] ], [ [[I]], [[HEADER]] ] 329; CHECK-NEXT: br label [[DUMMY:%.*]] 330; CHECK: dummy: 331; CHECK-NEXT: br label [[EXIT:%.*]] 332; CHECK: backedge: 333; CHECK-NEXT: [[I_INC]] = add i32 [[I]], 1 334; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 335; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT_LOOPEXIT:%.*]] 336; CHECK: exit.loopexit: 337; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 338; CHECK-NEXT: br label [[EXIT]] 339; CHECK: exit: 340; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I_LCSSA]], [[DUMMY]] ], [ [[I_INC_LCSSA]], [[EXIT_LOOPEXIT]] ] 341; CHECK-NEXT: ret i32 [[I_1]] 342; 343preheader: 344 br label %header 345 346header: 347 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 348 switch i32 1, label %dead [i32 0, label %dead 349 i32 1, label %backedge 350 i32 2, label %dead] 351 352dead: 353 br label %dummy 354 355dummy: 356 br label %exit 357 358backedge: 359 %i.inc = add i32 %i, 1 360 %cmp = icmp slt i32 %i.inc, %end 361 br i1 %cmp, label %header, label %exit 362 363exit: 364 %i.1 = phi i32 [%i.inc, %backedge], [%i, %dummy] 365 ret i32 %i.1 366} 367 368; Check that we can completely eliminate the current loop, branch case. 369define i32 @dead_loop_test_branch_loop(i32 %end) { 370; CHECK-LABEL: @dead_loop_test_branch_loop( 371; CHECK-NEXT: preheader: 372; CHECK-NEXT: br label [[HEADER:%.*]] 373; CHECK: header: 374; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 375; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 376; CHECK: dead: 377; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 378; CHECK-NEXT: br label [[BACKEDGE]] 379; CHECK: backedge: 380; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 381; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 382; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 383; CHECK-NEXT: br i1 false, label [[HEADER]], label [[EXIT:%.*]] 384; CHECK: exit: 385; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 386; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 387; 388preheader: 389 br label %header 390 391header: 392 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 393 br i1 true, label %backedge, label %dead 394 395dead: 396 %i.2 = add i32 %i, 1 397 br label %dummy 398 399dummy: 400 br label %backedge 401 402backedge: 403 %i.1 = phi i32 [%i, %header], [%i.2, %dummy] 404 %i.inc = add i32 %i.1, 1 405 %cmp = icmp slt i32 %i.inc, %end 406 br i1 false, label %header, label %exit 407 408exit: 409 ret i32 %i.inc 410} 411 412; Check that we can completely eliminate the current loop, switch case. 413define i32 @dead_loop_test_switch_loop(i32 %end) { 414; CHECK-LABEL: @dead_loop_test_switch_loop( 415; CHECK-NEXT: preheader: 416; CHECK-NEXT: br label [[HEADER:%.*]] 417; CHECK: header: 418; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 419; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 420; CHECK-NEXT: i32 0, label [[DEAD]] 421; CHECK-NEXT: i32 1, label [[BACKEDGE]] 422; CHECK-NEXT: i32 2, label [[DEAD]] 423; CHECK-NEXT: ] 424; CHECK: dead: 425; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 426; CHECK-NEXT: br label [[BACKEDGE]] 427; CHECK: backedge: 428; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 429; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 430; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 431; CHECK-NEXT: br i1 false, label [[HEADER]], label [[EXIT:%.*]] 432; CHECK: exit: 433; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 434; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 435; 436preheader: 437 br label %header 438header: 439 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 440 switch i32 1, label %dead [i32 0, label %dead 441 i32 1, label %backedge 442 i32 2, label %dead] 443dead: 444 %i.2 = add i32 %i, 1 445 br label %dummy 446 447dummy: 448 br label %backedge 449 450backedge: 451 %i.1 = phi i32 [%i, %header], [%i.2, %dummy] 452 %i.inc = add i32 %i.1, 1 453 %cmp = icmp slt i32 %i.inc, %end 454 br i1 false, label %header, label %exit 455 456exit: 457 ret i32 %i.inc 458} 459 460; Check that we can delete a dead inner loop entirely. 461define i32 @dead_sub_loop_test_branch_loop(i32 %end) { 462; CHECK-LABEL: @dead_sub_loop_test_branch_loop( 463; CHECK-NEXT: preheader: 464; CHECK-NEXT: br label [[HEADER:%.*]] 465; CHECK: header: 466; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 467; CHECK-NEXT: br i1 true, label [[LIVE_PREHEADER:%.*]], label [[DEAD_PREHEADER:%.*]] 468; CHECK: live_preheader: 469; CHECK-NEXT: br label [[LIVE_LOOP:%.*]] 470; CHECK: live_loop: 471; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[LIVE_PREHEADER]] ], [ [[A_INC:%.*]], [[LIVE_LOOP]] ] 472; CHECK-NEXT: [[A_INC]] = add i32 [[A]], 1 473; CHECK-NEXT: [[CMP_A:%.*]] = icmp slt i32 [[A_INC]], [[END:%.*]] 474; CHECK-NEXT: br i1 [[CMP_A]], label [[LIVE_LOOP]], label [[EXIT_A:%.*]] 475; CHECK: exit.a: 476; CHECK-NEXT: br label [[BACKEDGE]] 477; CHECK: dead_preheader: 478; CHECK-NEXT: br label [[DEAD_LOOP:%.*]] 479; CHECK: dead_loop: 480; CHECK-NEXT: [[B:%.*]] = phi i32 [ 0, [[DEAD_PREHEADER]] ], [ [[B_INC:%.*]], [[DEAD_LOOP]] ] 481; CHECK-NEXT: [[B_INC]] = add i32 [[B]], 1 482; CHECK-NEXT: [[CMP_B:%.*]] = icmp slt i32 [[B_INC]], [[END]] 483; CHECK-NEXT: br i1 [[CMP_B]], label [[DEAD_LOOP]], label [[EXIT_B:%.*]] 484; CHECK: exit.b: 485; CHECK-NEXT: br label [[BACKEDGE]] 486; CHECK: backedge: 487; CHECK-NEXT: [[I_INC]] = add i32 [[I]], 1 488; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END]] 489; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 490; CHECK: exit: 491; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 492; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 493; 494preheader: 495 br label %header 496 497header: 498 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 499 br i1 true, label %live_preheader, label %dead_preheader 500 501live_preheader: 502 br label %live_loop 503 504live_loop: 505 %a = phi i32 [0, %live_preheader], [%a.inc, %live_loop] 506 %a.inc = add i32 %a, 1 507 %cmp.a = icmp slt i32 %a.inc, %end 508 br i1 %cmp.a, label %live_loop, label %exit.a 509 510exit.a: 511 br label %backedge 512 513dead_preheader: 514 br label %dead_loop 515 516dead_loop: 517 %b = phi i32 [0, %dead_preheader], [%b.inc, %dead_loop] 518 %b.inc = add i32 %b, 1 519 %cmp.b = icmp slt i32 %b.inc, %end 520 br i1 %cmp.b, label %dead_loop, label %exit.b 521 522exit.b: 523 br label %backedge 524 525backedge: 526 %i.inc = add i32 %i, 1 527 %cmp = icmp slt i32 %i.inc, %end 528 br i1 %cmp, label %header, label %exit 529 530exit: 531 ret i32 %i.inc 532} 533 534define i32 @dead_sub_loop_test_switch_loop(i32 %end) { 535; CHECK-LABEL: @dead_sub_loop_test_switch_loop( 536; CHECK-NEXT: preheader: 537; CHECK-NEXT: br label [[HEADER:%.*]] 538; CHECK: header: 539; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 540; CHECK-NEXT: switch i32 1, label [[DEAD_PREHEADER:%.*]] [ 541; CHECK-NEXT: i32 0, label [[DEAD_PREHEADER]] 542; CHECK-NEXT: i32 1, label [[LIVE_PREHEADER:%.*]] 543; CHECK-NEXT: i32 2, label [[DEAD_PREHEADER]] 544; CHECK-NEXT: ] 545; CHECK: live_preheader: 546; CHECK-NEXT: br label [[LIVE_LOOP:%.*]] 547; CHECK: live_loop: 548; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[LIVE_PREHEADER]] ], [ [[A_INC:%.*]], [[LIVE_LOOP]] ] 549; CHECK-NEXT: [[A_INC]] = add i32 [[A]], 1 550; CHECK-NEXT: [[CMP_A:%.*]] = icmp slt i32 [[A_INC]], [[END:%.*]] 551; CHECK-NEXT: br i1 [[CMP_A]], label [[LIVE_LOOP]], label [[EXIT_A:%.*]] 552; CHECK: exit.a: 553; CHECK-NEXT: br label [[BACKEDGE]] 554; CHECK: dead_preheader: 555; CHECK-NEXT: br label [[DEAD_LOOP:%.*]] 556; CHECK: dead_loop: 557; CHECK-NEXT: [[B:%.*]] = phi i32 [ 0, [[DEAD_PREHEADER]] ], [ [[B_INC:%.*]], [[DEAD_LOOP]] ] 558; CHECK-NEXT: [[B_INC]] = add i32 [[B]], 1 559; CHECK-NEXT: [[CMP_B:%.*]] = icmp slt i32 [[B_INC]], [[END]] 560; CHECK-NEXT: br i1 [[CMP_B]], label [[DEAD_LOOP]], label [[EXIT_B:%.*]] 561; CHECK: exit.b: 562; CHECK-NEXT: br label [[BACKEDGE]] 563; CHECK: backedge: 564; CHECK-NEXT: [[I_INC]] = add i32 [[I]], 1 565; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END]] 566; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 567; CHECK: exit: 568; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 569; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 570; 571preheader: 572 br label %header 573 574header: 575 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 576 switch i32 1, label %dead_preheader [i32 0, label %dead_preheader 577 i32 1, label %live_preheader 578 i32 2, label %dead_preheader] 579 580live_preheader: 581 br label %live_loop 582 583live_loop: 584 %a = phi i32 [0, %live_preheader], [%a.inc, %live_loop] 585 %a.inc = add i32 %a, 1 586 %cmp.a = icmp slt i32 %a.inc, %end 587 br i1 %cmp.a, label %live_loop, label %exit.a 588 589exit.a: 590 br label %backedge 591 592dead_preheader: 593 br label %dead_loop 594 595dead_loop: 596 %b = phi i32 [0, %dead_preheader], [%b.inc, %dead_loop] 597 %b.inc = add i32 %b, 1 598 %cmp.b = icmp slt i32 %b.inc, %end 599 br i1 %cmp.b, label %dead_loop, label %exit.b 600 601exit.b: 602 br label %backedge 603 604backedge: 605 %i.inc = add i32 %i, 1 606 %cmp = icmp slt i32 %i.inc, %end 607 br i1 %cmp, label %header, label %exit 608 609exit: 610 ret i32 %i.inc 611} 612 613; Check that we preserve static reachability of an exit block even if we prove 614; that the loop is infinite. Branch case. 615define i32 @inf_loop_test_branch_loop(i32 %end) { 616; CHECK-LABEL: @inf_loop_test_branch_loop( 617; CHECK-NEXT: preheader: 618; CHECK-NEXT: br label [[HEADER:%.*]] 619; CHECK: header: 620; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 621; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 622; CHECK: dead: 623; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 624; CHECK-NEXT: br label [[BACKEDGE]] 625; CHECK: backedge: 626; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 627; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 628; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 629; CHECK-NEXT: br i1 true, label [[HEADER]], label [[EXIT:%.*]] 630; CHECK: exit: 631; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 632; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 633; 634preheader: 635 br label %header 636 637header: 638 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 639 br i1 true, label %backedge, label %dead 640 641dead: 642 %i.2 = add i32 %i, 1 643 br label %dummy 644 645dummy: 646 br label %backedge 647 648backedge: 649 %i.1 = phi i32 [%i, %header], [%i.2, %dummy] 650 %i.inc = add i32 %i.1, 1 651 %cmp = icmp slt i32 %i.inc, %end 652 br i1 true, label %header, label %exit 653 654exit: 655 ret i32 %i.inc 656} 657 658define i32 @inf_loop_test_switch_loop(i32 %end) { 659; CHECK-LABEL: @inf_loop_test_switch_loop( 660; CHECK-NEXT: preheader: 661; CHECK-NEXT: br label [[HEADER:%.*]] 662; CHECK: header: 663; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 664; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 665; CHECK-NEXT: i32 0, label [[DEAD]] 666; CHECK-NEXT: i32 1, label [[BACKEDGE]] 667; CHECK-NEXT: i32 2, label [[DEAD]] 668; CHECK-NEXT: ] 669; CHECK: dead: 670; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 671; CHECK-NEXT: br label [[BACKEDGE]] 672; CHECK: backedge: 673; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 674; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 675; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 676; CHECK-NEXT: br i1 true, label [[HEADER]], label [[EXIT:%.*]] 677; CHECK: exit: 678; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 679; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 680; 681preheader: 682 br label %header 683header: 684 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 685 switch i32 1, label %dead [i32 0, label %dead 686 i32 1, label %backedge 687 i32 2, label %dead] 688dead: 689 %i.2 = add i32 %i, 1 690 br label %dummy 691dummy: 692 br label %backedge 693backedge: 694 %i.1 = phi i32 [%i, %header], [%i.2, %dummy] 695 %i.inc = add i32 %i.1, 1 696 %cmp = icmp slt i32 %i.inc, %end 697 br i1 true, label %header, label %exit 698exit: 699 ret i32 %i.inc 700} 701 702; Check that when the block is not actually dead, we don't remove it. 703define i32 @live_block_test_branch_loop(i1 %c, i32 %end) { 704; CHECK-LABEL: @live_block_test_branch_loop( 705; CHECK-NEXT: preheader: 706; CHECK-NEXT: br label [[HEADER:%.*]] 707; CHECK: header: 708; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 709; CHECK-NEXT: br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]] 710; CHECK: check: 711; CHECK-NEXT: br label [[BACKEDGE]] 712; CHECK: live: 713; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 714; CHECK-NEXT: br label [[BACKEDGE]] 715; CHECK: backedge: 716; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ] 717; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 718; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 719; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 720; CHECK: exit: 721; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 722; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 723; 724preheader: 725 br label %header 726 727header: 728 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 729 br i1 %c, label %check, label %live 730 731check: 732 br i1 true, label %backedge, label %live 733 734live: 735 %i.2 = add i32 %i, 1 736 br label %backedge 737 738backedge: 739 %i.1 = phi i32 [%i, %check], [%i.2, %live] 740 %i.inc = add i32 %i.1, 1 741 %cmp = icmp slt i32 %i.inc, %end 742 br i1 %cmp, label %header, label %exit 743 744exit: 745 ret i32 %i.inc 746} 747 748; Check that when the block is not actually dead, we don't remove it. Version 749; with Phi node. 750define i32 @live_block_test_branch_loop_phis(i1 %c, i32 %end) { 751; CHECK-LABEL: @live_block_test_branch_loop_phis( 752; CHECK-NEXT: preheader: 753; CHECK-NEXT: br label [[HEADER:%.*]] 754; CHECK: header: 755; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 756; CHECK-NEXT: br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]] 757; CHECK: check: 758; CHECK-NEXT: br label [[BACKEDGE]] 759; CHECK: live: 760; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 761; CHECK-NEXT: br label [[BACKEDGE]] 762; CHECK: backedge: 763; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ] 764; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 765; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 766; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 767; CHECK: exit: 768; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 769; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 770; 771preheader: 772 br label %header 773 774header: 775 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 776 br i1 %c, label %check, label %live 777 778check: 779 br i1 true, label %backedge, label %live 780 781live: 782 %phi = phi i32 [ 1, %header ], [ -1, %check ] 783 %i.2 = add i32 %i, %phi 784 br label %backedge 785 786backedge: 787 %i.1 = phi i32 [%i, %check], [%i.2, %live] 788 %i.inc = add i32 %i.1, 1 789 %cmp = icmp slt i32 %i.inc, %end 790 br i1 %cmp, label %header, label %exit 791 792exit: 793 ret i32 %i.inc 794} 795 796define i32 @live_block_test_switch_loop(i1 %c, i32 %end) { 797; CHECK-LABEL: @live_block_test_switch_loop( 798; CHECK-NEXT: preheader: 799; CHECK-NEXT: br label [[HEADER:%.*]] 800; CHECK: header: 801; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 802; CHECK-NEXT: br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]] 803; CHECK: check: 804; CHECK-NEXT: br label [[BACKEDGE]] 805; CHECK: live: 806; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 807; CHECK-NEXT: br label [[BACKEDGE]] 808; CHECK: backedge: 809; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ] 810; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 811; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 812; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 813; CHECK: exit: 814; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 815; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 816; 817preheader: 818 br label %header 819 820header: 821 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 822 br i1 %c, label %check, label %live 823 824check: 825 switch i32 1, label %live [i32 0, label %live 826 i32 1, label %backedge 827 i32 2, label %live] 828 829live: 830 %i.2 = add i32 %i, 1 831 br label %backedge 832 833backedge: 834 %i.1 = phi i32 [%i, %check], [%i.2, %live] 835 %i.inc = add i32 %i.1, 1 836 %cmp = icmp slt i32 %i.inc, %end 837 br i1 %cmp, label %header, label %exit 838 839exit: 840 ret i32 %i.inc 841} 842 843define i32 @live_block_test_switch_loop_phis(i1 %c, i32 %end) { 844; CHECK-LABEL: @live_block_test_switch_loop_phis( 845; CHECK-NEXT: preheader: 846; CHECK-NEXT: br label [[HEADER:%.*]] 847; CHECK: header: 848; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 849; CHECK-NEXT: br i1 [[C:%.*]], label [[CHECK:%.*]], label [[LIVE:%.*]] 850; CHECK: check: 851; CHECK-NEXT: br label [[BACKEDGE]] 852; CHECK: live: 853; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 854; CHECK-NEXT: br label [[BACKEDGE]] 855; CHECK: backedge: 856; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[CHECK]] ], [ [[I_2]], [[LIVE]] ] 857; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 858; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 859; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[EXIT:%.*]] 860; CHECK: exit: 861; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 862; CHECK-NEXT: ret i32 [[I_INC_LCSSA]] 863; 864preheader: 865 br label %header 866 867header: 868 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 869 br i1 %c, label %check, label %live 870 871check: 872 switch i32 1, label %live [i32 0, label %live 873 i32 1, label %backedge 874 i32 2, label %live] 875 876live: 877 %phi = phi i32 [ 1, %header ], [ -1, %check ], [ -1, %check ], [ -1, %check ] 878 %i.2 = add i32 %i, %phi 879 br label %backedge 880 881backedge: 882 %i.1 = phi i32 [%i, %check], [%i.2, %live] 883 %i.inc = add i32 %i.1, 1 884 %cmp = icmp slt i32 %i.inc, %end 885 br i1 %cmp, label %header, label %exit 886 887exit: 888 ret i32 %i.inc 889} 890 891; Check that we can remove part of blocks of inner loop while the loop still 892; preserves, in presence of outer loop. 893define i32 @partial_sub_loop_test_branch_loop(i32 %end) { 894; CHECK-LABEL: @partial_sub_loop_test_branch_loop( 895; CHECK-NEXT: entry: 896; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 897; CHECK: outer_header: 898; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 899; CHECK-NEXT: br label [[HEADER:%.*]] 900; CHECK: header: 901; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 902; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 903; CHECK: dead: 904; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 905; CHECK-NEXT: br label [[BACKEDGE]] 906; CHECK: backedge: 907; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 908; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 909; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 910; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[OUTER_BACKEDGE]] 911; CHECK: outer_backedge: 912; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 913; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 914; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END]] 915; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 916; CHECK: exit: 917; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 918; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 919; 920entry: 921 br label %outer_header 922 923outer_header: 924 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 925 br label %preheader 926 927preheader: 928 br label %header 929 930header: 931 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 932 br i1 true, label %backedge, label %dead 933 934dead: 935 %i.2 = add i32 %i, 1 936 br label %backedge 937 938backedge: 939 %i.1 = phi i32 [%i, %header], [%i.2, %dead] 940 %i.inc = add i32 %i.1, 1 941 %cmp = icmp slt i32 %i.inc, %end 942 br i1 %cmp, label %header, label %outer_backedge 943 944outer_backedge: 945 %j.inc = add i32 %j, 1 946 %cmp.j = icmp slt i32 %j.inc, %end 947 br i1 %cmp.j, label %outer_header, label %exit 948 949exit: 950 ret i32 %i.inc 951} 952 953define i32 @partial_sub_loop_test_switch_loop(i32 %end) { 954; CHECK-LABEL: @partial_sub_loop_test_switch_loop( 955; CHECK-NEXT: entry: 956; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 957; CHECK: outer_header: 958; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 959; CHECK-NEXT: br label [[HEADER:%.*]] 960; CHECK: header: 961; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 962; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 963; CHECK-NEXT: i32 0, label [[DEAD]] 964; CHECK-NEXT: i32 1, label [[BACKEDGE]] 965; CHECK-NEXT: i32 2, label [[DEAD]] 966; CHECK-NEXT: ] 967; CHECK: dead: 968; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 969; CHECK-NEXT: br label [[BACKEDGE]] 970; CHECK: backedge: 971; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 972; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 973; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_INC]], [[END:%.*]] 974; CHECK-NEXT: br i1 [[CMP]], label [[HEADER]], label [[OUTER_BACKEDGE]] 975; CHECK: outer_backedge: 976; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 977; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 978; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END]] 979; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 980; CHECK: exit: 981; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 982; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 983; 984entry: 985 br label %outer_header 986 987outer_header: 988 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 989 br label %preheader 990 991preheader: 992 br label %header 993 994header: 995 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 996 switch i32 1, label %dead [i32 0, label %dead 997 i32 1, label %backedge 998 i32 2, label %dead] 999 1000dead: 1001 %i.2 = add i32 %i, 1 1002 br label %backedge 1003 1004backedge: 1005 %i.1 = phi i32 [%i, %header], [%i.2, %dead] 1006 %i.inc = add i32 %i.1, 1 1007 %cmp = icmp slt i32 %i.inc, %end 1008 br i1 %cmp, label %header, label %outer_backedge 1009 1010outer_backedge: 1011 %j.inc = add i32 %j, 1 1012 %cmp.j = icmp slt i32 %j.inc, %end 1013 br i1 %cmp.j, label %outer_header, label %exit 1014 1015exit: 1016 ret i32 %i.inc 1017} 1018 1019; Check that we can completely delete inner loop and preserve the outer loop. 1020define i32 @full_sub_loop_test_branch_loop(i32 %end) { 1021; CHECK-LABEL: @full_sub_loop_test_branch_loop( 1022; CHECK-NEXT: entry: 1023; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1024; CHECK: outer_header: 1025; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1026; CHECK-NEXT: br label [[HEADER:%.*]] 1027; CHECK: header: 1028; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1029; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1030; CHECK-NEXT: br i1 false, label [[BACKEDGE]], label [[DEAD:%.*]] 1031; CHECK: dead: 1032; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1033; CHECK-NEXT: br label [[BACKEDGE]] 1034; CHECK: backedge: 1035; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1036; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1037; CHECK-NEXT: br i1 false, label [[HEADER]], label [[OUTER_BACKEDGE]] 1038; CHECK: outer_backedge: 1039; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1040; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1041; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1042; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1043; CHECK: exit: 1044; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1045; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1046; 1047entry: 1048 br label %outer_header 1049 1050outer_header: 1051 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1052 br label %preheader 1053 1054preheader: 1055 br label %header 1056 1057header: 1058 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1059 br label %live_part 1060 1061live_part: 1062 %mul = mul i32 %i, %i 1063 br i1 false, label %backedge, label %dead 1064 1065dead: 1066 %i.2 = add i32 %i, 1 1067 br label %backedge 1068 1069backedge: 1070 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1071 %i.inc = add i32 %i.1, 1 1072 br i1 false, label %header, label %outer_backedge 1073 1074outer_backedge: 1075 %j.inc = add i32 %j, 1 1076 %cmp.j = icmp slt i32 %j.inc, %end 1077 br i1 %cmp.j, label %outer_header, label %exit 1078 1079exit: 1080 ret i32 %i.inc 1081} 1082 1083define i32 @full_sub_loop_test_switch_loop(i32 %end) { 1084; CHECK-LABEL: @full_sub_loop_test_switch_loop( 1085; CHECK-NEXT: entry: 1086; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1087; CHECK: outer_header: 1088; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1089; CHECK-NEXT: br label [[HEADER:%.*]] 1090; CHECK: header: 1091; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1092; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1093; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 1094; CHECK-NEXT: i32 0, label [[BACKEDGE]] 1095; CHECK-NEXT: ] 1096; CHECK: dead: 1097; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1098; CHECK-NEXT: br label [[BACKEDGE]] 1099; CHECK: backedge: 1100; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1101; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1102; CHECK-NEXT: switch i32 1, label [[OUTER_BACKEDGE]] [ 1103; CHECK-NEXT: i32 0, label [[HEADER]] 1104; CHECK-NEXT: ] 1105; CHECK: outer_backedge: 1106; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1107; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1108; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1109; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1110; CHECK: exit: 1111; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1112; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1113; 1114entry: 1115 br label %outer_header 1116 1117outer_header: 1118 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1119 br label %preheader 1120 1121preheader: 1122 br label %header 1123 1124header: 1125 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1126 br label %live_part 1127 1128live_part: 1129 %mul = mul i32 %i, %i 1130 switch i32 1, label %dead [i32 0, label %backedge] 1131 1132dead: 1133 %i.2 = add i32 %i, 1 1134 br label %backedge 1135 1136backedge: 1137 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1138 %i.inc = add i32 %i.1, 1 1139 switch i32 1, label %outer_backedge [i32 0, label %header] 1140 1141outer_backedge: 1142 %j.inc = add i32 %j, 1 1143 %cmp.j = icmp slt i32 %j.inc, %end 1144 br i1 %cmp.j, label %outer_header, label %exit 1145 1146exit: 1147 ret i32 %i.inc 1148} 1149 1150; Inverted condition in live_part. 1151define i32 @full_sub_loop_test_branch_loop_inverse_1(i32 %end) { 1152; CHECK-LABEL: @full_sub_loop_test_branch_loop_inverse_1( 1153; CHECK-NEXT: entry: 1154; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1155; CHECK: outer_header: 1156; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1157; CHECK-NEXT: br label [[HEADER:%.*]] 1158; CHECK: header: 1159; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1160; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1161; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 1162; CHECK: dead: 1163; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1164; CHECK-NEXT: br label [[BACKEDGE]] 1165; CHECK: backedge: 1166; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1167; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1168; CHECK-NEXT: br i1 false, label [[HEADER]], label [[OUTER_BACKEDGE]] 1169; CHECK: outer_backedge: 1170; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1171; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1172; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1173; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1174; CHECK: exit: 1175; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1176; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1177; 1178entry: 1179 br label %outer_header 1180 1181outer_header: 1182 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1183 br label %preheader 1184 1185preheader: 1186 br label %header 1187 1188header: 1189 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1190 br label %live_part 1191 1192live_part: 1193 %mul = mul i32 %i, %i 1194 br i1 true, label %backedge, label %dead 1195 1196dead: 1197 %i.2 = add i32 %i, 1 1198 br label %backedge 1199 1200backedge: 1201 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1202 %i.inc = add i32 %i.1, 1 1203 br i1 false, label %header, label %outer_backedge 1204 1205outer_backedge: 1206 %j.inc = add i32 %j, 1 1207 %cmp.j = icmp slt i32 %j.inc, %end 1208 br i1 %cmp.j, label %outer_header, label %exit 1209 1210exit: 1211 ret i32 %i.inc 1212} 1213 1214define i32 @full_sub_loop_test_switch_loop_inverse_1(i32 %end) { 1215; CHECK-LABEL: @full_sub_loop_test_switch_loop_inverse_1( 1216; CHECK-NEXT: entry: 1217; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1218; CHECK: outer_header: 1219; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1220; CHECK-NEXT: br label [[HEADER:%.*]] 1221; CHECK: header: 1222; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1223; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1224; CHECK-NEXT: switch i32 1, label [[BACKEDGE]] [ 1225; CHECK-NEXT: i32 0, label [[DEAD:%.*]] 1226; CHECK-NEXT: ] 1227; CHECK: dead: 1228; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1229; CHECK-NEXT: br label [[BACKEDGE]] 1230; CHECK: backedge: 1231; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1232; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1233; CHECK-NEXT: switch i32 1, label [[OUTER_BACKEDGE]] [ 1234; CHECK-NEXT: i32 0, label [[HEADER]] 1235; CHECK-NEXT: ] 1236; CHECK: outer_backedge: 1237; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1238; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1239; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1240; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1241; CHECK: exit: 1242; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1243; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1244; 1245entry: 1246 br label %outer_header 1247 1248outer_header: 1249 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1250 br label %preheader 1251 1252preheader: 1253 br label %header 1254 1255header: 1256 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1257 br label %live_part 1258 1259live_part: 1260 %mul = mul i32 %i, %i 1261 switch i32 1, label %backedge [i32 0, label %dead] 1262 1263dead: 1264 %i.2 = add i32 %i, 1 1265 br label %backedge 1266 1267backedge: 1268 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1269 %i.inc = add i32 %i.1, 1 1270 switch i32 1, label %outer_backedge [i32 0, label %header] 1271 1272outer_backedge: 1273 %j.inc = add i32 %j, 1 1274 %cmp.j = icmp slt i32 %j.inc, %end 1275 br i1 %cmp.j, label %outer_header, label %exit 1276 1277exit: 1278 ret i32 %i.inc 1279} 1280 1281define i32 @full_sub_loop_test_branch_loop_inverse_2(i32 %end) { 1282; CHECK-LABEL: @full_sub_loop_test_branch_loop_inverse_2( 1283; CHECK-NEXT: entry: 1284; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1285; CHECK: outer_header: 1286; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1287; CHECK-NEXT: br label [[HEADER:%.*]] 1288; CHECK: header: 1289; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1290; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1291; CHECK-NEXT: br i1 false, label [[BACKEDGE]], label [[DEAD:%.*]] 1292; CHECK: dead: 1293; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1294; CHECK-NEXT: br label [[BACKEDGE]] 1295; CHECK: backedge: 1296; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1297; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1298; CHECK-NEXT: br i1 true, label [[HEADER]], label [[OUTER_BACKEDGE]] 1299; CHECK: outer_backedge: 1300; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1301; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1302; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1303; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1304; CHECK: exit: 1305; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1306; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1307; 1308entry: 1309 br label %outer_header 1310 1311outer_header: 1312 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1313 br label %preheader 1314 1315preheader: 1316 br label %header 1317 1318header: 1319 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1320 br label %live_part 1321 1322live_part: 1323 %mul = mul i32 %i, %i 1324 br i1 false, label %backedge, label %dead 1325 1326dead: 1327 %i.2 = add i32 %i, 1 1328 br label %backedge 1329 1330backedge: 1331 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1332 %i.inc = add i32 %i.1, 1 1333 br i1 true, label %header, label %outer_backedge 1334 1335outer_backedge: 1336 %j.inc = add i32 %j, 1 1337 %cmp.j = icmp slt i32 %j.inc, %end 1338 br i1 %cmp.j, label %outer_header, label %exit 1339 1340exit: 1341 ret i32 %i.inc 1342} 1343 1344define i32 @full_sub_loop_test_switch_loop_inverse_2(i32 %end) { 1345; CHECK-LABEL: @full_sub_loop_test_switch_loop_inverse_2( 1346; CHECK-NEXT: entry: 1347; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1348; CHECK: outer_header: 1349; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1350; CHECK-NEXT: br label [[HEADER:%.*]] 1351; CHECK: header: 1352; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1353; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1354; CHECK-NEXT: switch i32 1, label [[DEAD:%.*]] [ 1355; CHECK-NEXT: i32 0, label [[BACKEDGE]] 1356; CHECK-NEXT: ] 1357; CHECK: dead: 1358; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1359; CHECK-NEXT: br label [[BACKEDGE]] 1360; CHECK: backedge: 1361; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1362; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1363; CHECK-NEXT: switch i32 1, label [[HEADER]] [ 1364; CHECK-NEXT: i32 0, label [[OUTER_BACKEDGE]] 1365; CHECK-NEXT: ] 1366; CHECK: outer_backedge: 1367; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1368; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1369; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1370; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1371; CHECK: exit: 1372; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1373; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1374; 1375entry: 1376 br label %outer_header 1377 1378outer_header: 1379 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1380 br label %preheader 1381 1382preheader: 1383 br label %header 1384 1385header: 1386 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1387 br label %live_part 1388 1389live_part: 1390 %mul = mul i32 %i, %i 1391 switch i32 1, label %dead [i32 0, label %backedge] 1392 1393dead: 1394 %i.2 = add i32 %i, 1 1395 br label %backedge 1396 1397backedge: 1398 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1399 %i.inc = add i32 %i.1, 1 1400 switch i32 1, label %header [i32 0, label %outer_backedge] 1401 1402outer_backedge: 1403 %j.inc = add i32 %j, 1 1404 %cmp.j = icmp slt i32 %j.inc, %end 1405 br i1 %cmp.j, label %outer_header, label %exit 1406 1407exit: 1408 ret i32 %i.inc 1409} 1410 1411 1412define i32 @full_sub_loop_test_branch_loop_inverse_3(i32 %end) { 1413; CHECK-LABEL: @full_sub_loop_test_branch_loop_inverse_3( 1414; CHECK-NEXT: entry: 1415; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1416; CHECK: outer_header: 1417; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1418; CHECK-NEXT: br label [[HEADER:%.*]] 1419; CHECK: header: 1420; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1421; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1422; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[DEAD:%.*]] 1423; CHECK: dead: 1424; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1425; CHECK-NEXT: br label [[BACKEDGE]] 1426; CHECK: backedge: 1427; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1428; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1429; CHECK-NEXT: br i1 true, label [[HEADER]], label [[OUTER_BACKEDGE]] 1430; CHECK: outer_backedge: 1431; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1432; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1433; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1434; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1435; CHECK: exit: 1436; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1437; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1438; 1439entry: 1440 br label %outer_header 1441 1442outer_header: 1443 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1444 br label %preheader 1445 1446preheader: 1447 br label %header 1448 1449header: 1450 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1451 br label %live_part 1452 1453live_part: 1454 %mul = mul i32 %i, %i 1455 br i1 true, label %backedge, label %dead 1456 1457dead: 1458 %i.2 = add i32 %i, 1 1459 br label %backedge 1460 1461backedge: 1462 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1463 %i.inc = add i32 %i.1, 1 1464 br i1 true, label %header, label %outer_backedge 1465 1466outer_backedge: 1467 %j.inc = add i32 %j, 1 1468 %cmp.j = icmp slt i32 %j.inc, %end 1469 br i1 %cmp.j, label %outer_header, label %exit 1470 1471exit: 1472 ret i32 %i.inc 1473} 1474 1475define i32 @full_sub_loop_test_switch_loop_inverse_3(i32 %end) { 1476; CHECK-LABEL: @full_sub_loop_test_switch_loop_inverse_3( 1477; CHECK-NEXT: entry: 1478; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 1479; CHECK: outer_header: 1480; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[J_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] 1481; CHECK-NEXT: br label [[HEADER:%.*]] 1482; CHECK: header: 1483; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[OUTER_HEADER]] ], [ [[I_INC:%.*]], [[BACKEDGE:%.*]] ] 1484; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I]], [[I]] 1485; CHECK-NEXT: switch i32 1, label [[BACKEDGE]] [ 1486; CHECK-NEXT: i32 0, label [[DEAD:%.*]] 1487; CHECK-NEXT: ] 1488; CHECK: dead: 1489; CHECK-NEXT: [[I_2:%.*]] = add i32 [[I]], 1 1490; CHECK-NEXT: br label [[BACKEDGE]] 1491; CHECK: backedge: 1492; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[I]], [[HEADER]] ], [ [[I_2]], [[DEAD]] ] 1493; CHECK-NEXT: [[I_INC]] = add i32 [[I_1]], 1 1494; CHECK-NEXT: switch i32 1, label [[HEADER]] [ 1495; CHECK-NEXT: i32 0, label [[OUTER_BACKEDGE]] 1496; CHECK-NEXT: ] 1497; CHECK: outer_backedge: 1498; CHECK-NEXT: [[I_INC_LCSSA:%.*]] = phi i32 [ [[I_INC]], [[BACKEDGE]] ] 1499; CHECK-NEXT: [[J_INC]] = add i32 [[J]], 1 1500; CHECK-NEXT: [[CMP_J:%.*]] = icmp slt i32 [[J_INC]], [[END:%.*]] 1501; CHECK-NEXT: br i1 [[CMP_J]], label [[OUTER_HEADER]], label [[EXIT:%.*]] 1502; CHECK: exit: 1503; CHECK-NEXT: [[I_INC_LCSSA_LCSSA:%.*]] = phi i32 [ [[I_INC_LCSSA]], [[OUTER_BACKEDGE]] ] 1504; CHECK-NEXT: ret i32 [[I_INC_LCSSA_LCSSA]] 1505; 1506entry: 1507 br label %outer_header 1508 1509outer_header: 1510 %j = phi i32 [0, %entry], [%j.inc, %outer_backedge] 1511 br label %preheader 1512 1513preheader: 1514 br label %header 1515 1516header: 1517 %i = phi i32 [0, %preheader], [%i.inc, %backedge] 1518 br label %live_part 1519 1520live_part: 1521 %mul = mul i32 %i, %i 1522 switch i32 1, label %backedge [i32 0, label %dead] 1523 1524dead: 1525 %i.2 = add i32 %i, 1 1526 br label %backedge 1527 1528backedge: 1529 %i.1 = phi i32 [%i, %live_part], [%i.2, %dead] 1530 %i.inc = add i32 %i.1, 1 1531 switch i32 1, label %header [i32 0, label %outer_backedge] 1532 1533outer_backedge: 1534 %j.inc = add i32 %j, 1 1535 %cmp.j = icmp slt i32 %j.inc, %end 1536 br i1 %cmp.j, label %outer_header, label %exit 1537 1538exit: 1539 ret i32 %i.inc 1540} 1541 1542define i32 @exit_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) { 1543; CHECK-LABEL: @exit_branch_from_inner_to_grandparent( 1544; CHECK-NEXT: preheader: 1545; CHECK-NEXT: br label [[LOOP_1:%.*]] 1546; CHECK: loop_1: 1547; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1548; CHECK-NEXT: br label [[LOOP_2:%.*]] 1549; CHECK: loop_2: 1550; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1551; CHECK-NEXT: br label [[LOOP_3:%.*]] 1552; CHECK: loop_3: 1553; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1554; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] 1555; CHECK: loop_3_backedge: 1556; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1557; CHECK-NEXT: br i1 true, label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 1558; CHECK: loop_2_backedge: 1559; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1560; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1561; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 1562; CHECK: loop_1_backedge.loopexit: 1563; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1564; CHECK: loop_1_backedge.loopexit1: 1565; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1566; CHECK: loop_1_backedge: 1567; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1568; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1569; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1570; CHECK: exit: 1571; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1572; CHECK-NEXT: ret i32 [[I_LCSSA]] 1573; 1574preheader: 1575 br label %loop_1 1576 1577loop_1: 1578 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1579 br label %loop_2 1580 1581loop_2: 1582 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1583 br label %loop_3 1584 1585loop_3: 1586 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 1587 br i1 %cond1, label %loop_3_backedge, label %loop_1_backedge 1588 1589loop_3_backedge: 1590 %k.next = add i32 %k, 1 1591 br i1 true, label %loop_3, label %loop_2_backedge 1592 1593loop_2_backedge: 1594 %j.next = add i32 %j, 1 1595 %c_2 = icmp slt i32 %j.next, %N 1596 br i1 %c_2, label %loop_2, label %loop_1_backedge 1597 1598loop_1_backedge: 1599 %i.next = add i32 %i, 1 1600 %c_1 = icmp slt i32 %i.next, %N 1601 br i1 %c_1, label %loop_1, label %exit 1602 1603exit: 1604 ret i32 %i 1605} 1606 1607define i32 @exit_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) { 1608; CHECK-LABEL: @exit_switch_from_inner_to_grandparent( 1609; CHECK-NEXT: preheader: 1610; CHECK-NEXT: br label [[LOOP_1:%.*]] 1611; CHECK: loop_1: 1612; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1613; CHECK-NEXT: br label [[LOOP_2:%.*]] 1614; CHECK: loop_2: 1615; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1616; CHECK-NEXT: br label [[LOOP_3:%.*]] 1617; CHECK: loop_3: 1618; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1619; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] 1620; CHECK: loop_3_backedge: 1621; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1622; CHECK-NEXT: switch i32 1, label [[LOOP_3]] [ 1623; CHECK-NEXT: i32 0, label [[LOOP_2_BACKEDGE]] 1624; CHECK-NEXT: ] 1625; CHECK: loop_2_backedge: 1626; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1627; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1628; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 1629; CHECK: loop_1_backedge.loopexit: 1630; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1631; CHECK: loop_1_backedge.loopexit1: 1632; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1633; CHECK: loop_1_backedge: 1634; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1635; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1636; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1637; CHECK: exit: 1638; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1639; CHECK-NEXT: ret i32 [[I_LCSSA]] 1640; 1641preheader: 1642 br label %loop_1 1643 1644loop_1: 1645 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1646 br label %loop_2 1647 1648loop_2: 1649 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1650 br label %loop_3 1651 1652loop_3: 1653 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 1654 br i1 %cond1, label %loop_3_backedge, label %loop_1_backedge 1655 1656loop_3_backedge: 1657 %k.next = add i32 %k, 1 1658 switch i32 1, label %loop_3 [i32 0, label %loop_2_backedge] 1659 1660loop_2_backedge: 1661 %j.next = add i32 %j, 1 1662 %c_2 = icmp slt i32 %j.next, %N 1663 br i1 %c_2, label %loop_2, label %loop_1_backedge 1664 1665loop_1_backedge: 1666 %i.next = add i32 %i, 1 1667 %c_1 = icmp slt i32 %i.next, %N 1668 br i1 %c_1, label %loop_1, label %exit 1669 1670exit: 1671 ret i32 %i 1672} 1673 1674define i32 @intermediate_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) { 1675; CHECK-LABEL: @intermediate_branch_from_inner_to_grandparent( 1676; CHECK-NEXT: preheader: 1677; CHECK-NEXT: br label [[LOOP_1:%.*]] 1678; CHECK: loop_1: 1679; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1680; CHECK-NEXT: br label [[LOOP_2:%.*]] 1681; CHECK: loop_2: 1682; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1683; CHECK-NEXT: br label [[LOOP_3:%.*]] 1684; CHECK: loop_3: 1685; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1686; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 1687; CHECK: intermediate: 1688; CHECK-NEXT: br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] 1689; CHECK: loop_3_backedge: 1690; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1691; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 1692; CHECK: loop_2_backedge: 1693; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1694; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1695; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 1696; CHECK: loop_1_backedge.loopexit: 1697; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1698; CHECK: loop_1_backedge.loopexit1: 1699; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1700; CHECK: loop_1_backedge: 1701; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1702; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1703; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1704; CHECK: exit: 1705; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1706; CHECK-NEXT: ret i32 [[I_LCSSA]] 1707; 1708preheader: 1709 br label %loop_1 1710 1711loop_1: 1712 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1713 br label %loop_2 1714 1715loop_2: 1716 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1717 br label %loop_3 1718 1719loop_3: 1720 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 1721 br i1 %cond1, label %loop_3_backedge, label %intermediate 1722 1723intermediate: 1724 br i1 false, label %loop_3_backedge, label %loop_1_backedge 1725 1726loop_3_backedge: 1727 %k.next = add i32 %k, 1 1728 br i1 %cond2, label %loop_3, label %loop_2_backedge 1729 1730loop_2_backedge: 1731 %j.next = add i32 %j, 1 1732 %c_2 = icmp slt i32 %j.next, %N 1733 br i1 %c_2, label %loop_2, label %loop_1_backedge 1734 1735loop_1_backedge: 1736 %i.next = add i32 %i, 1 1737 %c_1 = icmp slt i32 %i.next, %N 1738 br i1 %c_1, label %loop_1, label %exit 1739 1740exit: 1741 ret i32 %i 1742} 1743 1744define i32 @intermediate_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i32 %N) { 1745; CHECK-LABEL: @intermediate_switch_from_inner_to_grandparent( 1746; CHECK-NEXT: preheader: 1747; CHECK-NEXT: br label [[LOOP_1:%.*]] 1748; CHECK: loop_1: 1749; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1750; CHECK-NEXT: br label [[LOOP_2:%.*]] 1751; CHECK: loop_2: 1752; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1753; CHECK-NEXT: br label [[LOOP_3:%.*]] 1754; CHECK: loop_3: 1755; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1756; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 1757; CHECK: intermediate: 1758; CHECK-NEXT: switch i32 1, label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] [ 1759; CHECK-NEXT: i32 0, label [[LOOP_3_BACKEDGE]] 1760; CHECK-NEXT: ] 1761; CHECK: loop_3_backedge: 1762; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1763; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 1764; CHECK: loop_2_backedge: 1765; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1766; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1767; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 1768; CHECK: loop_1_backedge.loopexit: 1769; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1770; CHECK: loop_1_backedge.loopexit1: 1771; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1772; CHECK: loop_1_backedge: 1773; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1774; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1775; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1776; CHECK: exit: 1777; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1778; CHECK-NEXT: ret i32 [[I_LCSSA]] 1779; 1780preheader: 1781 br label %loop_1 1782 1783loop_1: 1784 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1785 br label %loop_2 1786 1787loop_2: 1788 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1789 br label %loop_3 1790 1791loop_3: 1792 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 1793 br i1 %cond1, label %loop_3_backedge, label %intermediate 1794 1795intermediate: 1796 switch i32 1, label %loop_1_backedge [i32 0, label %loop_3_backedge] 1797 1798loop_3_backedge: 1799 %k.next = add i32 %k, 1 1800 br i1 %cond2, label %loop_3, label %loop_2_backedge 1801 1802loop_2_backedge: 1803 %j.next = add i32 %j, 1 1804 %c_2 = icmp slt i32 %j.next, %N 1805 br i1 %c_2, label %loop_2, label %loop_1_backedge 1806 1807loop_1_backedge: 1808 %i.next = add i32 %i, 1 1809 %c_1 = icmp slt i32 %i.next, %N 1810 br i1 %c_1, label %loop_1, label %exit 1811 1812exit: 1813 ret i32 %i 1814} 1815 1816define i32 @intermediate_branch_from_inner_to_parent(i1 %cond1, i1 %cond2, i32 %N) { 1817; CHECK-LABEL: @intermediate_branch_from_inner_to_parent( 1818; CHECK-NEXT: preheader: 1819; CHECK-NEXT: br label [[LOOP_1:%.*]] 1820; CHECK: loop_1: 1821; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1822; CHECK-NEXT: br label [[LOOP_2:%.*]] 1823; CHECK: loop_2: 1824; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1825; CHECK-NEXT: br label [[LOOP_3:%.*]] 1826; CHECK: loop_3: 1827; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1828; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 1829; CHECK: intermediate: 1830; CHECK-NEXT: br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_2_BACKEDGE]] 1831; CHECK: loop_3_backedge: 1832; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1833; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 1834; CHECK: loop_2_backedge: 1835; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1836; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1837; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]] 1838; CHECK: loop_1_backedge: 1839; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1840; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1841; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1842; CHECK: exit: 1843; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1844; CHECK-NEXT: ret i32 [[I_LCSSA]] 1845; 1846preheader: 1847 br label %loop_1 1848 1849loop_1: 1850 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1851 br label %loop_2 1852 1853loop_2: 1854 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1855 br label %loop_3 1856 1857loop_3: 1858 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 1859 br i1 %cond1, label %loop_3_backedge, label %intermediate 1860 1861intermediate: 1862 br i1 false, label %loop_3_backedge, label %loop_2_backedge 1863 1864loop_3_backedge: 1865 %k.next = add i32 %k, 1 1866 br i1 %cond2, label %loop_3, label %loop_2_backedge 1867 1868loop_2_backedge: 1869 %j.next = add i32 %j, 1 1870 %c_2 = icmp slt i32 %j.next, %N 1871 br i1 %c_2, label %loop_2, label %loop_1_backedge 1872 1873loop_1_backedge: 1874 %i.next = add i32 %i, 1 1875 %c_1 = icmp slt i32 %i.next, %N 1876 br i1 %c_1, label %loop_1, label %exit 1877 1878exit: 1879 ret i32 %i 1880} 1881 1882define i32 @intermediate_switch_from_inner_to_parent(i1 %cond1, i1 %cond2, i32 %N) { 1883; CHECK-LABEL: @intermediate_switch_from_inner_to_parent( 1884; CHECK-NEXT: preheader: 1885; CHECK-NEXT: br label [[LOOP_1:%.*]] 1886; CHECK: loop_1: 1887; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1888; CHECK-NEXT: br label [[LOOP_2:%.*]] 1889; CHECK: loop_2: 1890; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1891; CHECK-NEXT: br label [[LOOP_3:%.*]] 1892; CHECK: loop_3: 1893; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1894; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 1895; CHECK: intermediate: 1896; CHECK-NEXT: switch i32 1, label [[LOOP_2_BACKEDGE]] [ 1897; CHECK-NEXT: i32 0, label [[LOOP_3_BACKEDGE]] 1898; CHECK-NEXT: ] 1899; CHECK: loop_3_backedge: 1900; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1901; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 1902; CHECK: loop_2_backedge: 1903; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1904; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1905; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]] 1906; CHECK: loop_1_backedge: 1907; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1908; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1909; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1910; CHECK: exit: 1911; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1912; CHECK-NEXT: ret i32 [[I_LCSSA]] 1913; 1914preheader: 1915 br label %loop_1 1916 1917loop_1: 1918 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1919 br label %loop_2 1920 1921loop_2: 1922 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1923 br label %loop_3 1924 1925loop_3: 1926 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 1927 br i1 %cond1, label %loop_3_backedge, label %intermediate 1928 1929intermediate: 1930 switch i32 1, label %loop_2_backedge [i32 0, label %loop_3_backedge] 1931 1932loop_3_backedge: 1933 %k.next = add i32 %k, 1 1934 br i1 %cond2, label %loop_3, label %loop_2_backedge 1935 1936loop_2_backedge: 1937 %j.next = add i32 %j, 1 1938 %c_2 = icmp slt i32 %j.next, %N 1939 br i1 %c_2, label %loop_2, label %loop_1_backedge 1940 1941loop_1_backedge: 1942 %i.next = add i32 %i, 1 1943 %c_1 = icmp slt i32 %i.next, %N 1944 br i1 %c_1, label %loop_1, label %exit 1945 1946exit: 1947 ret i32 %i 1948} 1949 1950define i32 @intermediate_subloop_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 1951; CHECK-LABEL: @intermediate_subloop_branch_from_inner_to_grandparent( 1952; CHECK-NEXT: preheader: 1953; CHECK-NEXT: br label [[LOOP_1:%.*]] 1954; CHECK: loop_1: 1955; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 1956; CHECK-NEXT: br label [[LOOP_2:%.*]] 1957; CHECK: loop_2: 1958; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 1959; CHECK-NEXT: br label [[LOOP_3:%.*]] 1960; CHECK: loop_3: 1961; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 1962; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 1963; CHECK: intermediate: 1964; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 1965; CHECK: intermediate_loop: 1966; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]] 1967; CHECK: intermediate_exit: 1968; CHECK-NEXT: br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] 1969; CHECK: loop_3_backedge: 1970; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 1971; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 1972; CHECK: loop_2_backedge: 1973; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 1974; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 1975; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 1976; CHECK: loop_1_backedge.loopexit: 1977; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1978; CHECK: loop_1_backedge.loopexit1: 1979; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 1980; CHECK: loop_1_backedge: 1981; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 1982; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 1983; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 1984; CHECK: exit: 1985; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 1986; CHECK-NEXT: ret i32 [[I_LCSSA]] 1987; 1988preheader: 1989 br label %loop_1 1990 1991loop_1: 1992 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 1993 br label %loop_2 1994 1995loop_2: 1996 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 1997 br label %loop_3 1998 1999loop_3: 2000 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2001 br i1 %cond1, label %loop_3_backedge, label %intermediate 2002 2003intermediate: 2004 br label %intermediate_loop 2005 2006intermediate_loop: 2007 br i1 %cond3, label %intermediate_loop, label %intermediate_exit 2008 2009intermediate_exit: 2010 br i1 false, label %loop_3_backedge, label %loop_1_backedge 2011 2012loop_3_backedge: 2013 %k.next = add i32 %k, 1 2014 br i1 %cond2, label %loop_3, label %loop_2_backedge 2015 2016loop_2_backedge: 2017 %j.next = add i32 %j, 1 2018 %c_2 = icmp slt i32 %j.next, %N 2019 br i1 %c_2, label %loop_2, label %loop_1_backedge 2020 2021loop_1_backedge: 2022 %i.next = add i32 %i, 1 2023 %c_1 = icmp slt i32 %i.next, %N 2024 br i1 %c_1, label %loop_1, label %exit 2025 2026exit: 2027 ret i32 %i 2028} 2029 2030define i32 @intermediate_subloop_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2031; CHECK-LABEL: @intermediate_subloop_switch_from_inner_to_grandparent( 2032; CHECK-NEXT: preheader: 2033; CHECK-NEXT: br label [[LOOP_1:%.*]] 2034; CHECK: loop_1: 2035; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2036; CHECK-NEXT: br label [[LOOP_2:%.*]] 2037; CHECK: loop_2: 2038; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2039; CHECK-NEXT: br label [[LOOP_3:%.*]] 2040; CHECK: loop_3: 2041; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2042; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2043; CHECK: intermediate: 2044; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2045; CHECK: intermediate_loop: 2046; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]] 2047; CHECK: intermediate_exit: 2048; CHECK-NEXT: switch i32 1, label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] [ 2049; CHECK-NEXT: i32 0, label [[LOOP_3_BACKEDGE]] 2050; CHECK-NEXT: ] 2051; CHECK: loop_3_backedge: 2052; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2053; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2054; CHECK: loop_2_backedge: 2055; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2056; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2057; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 2058; CHECK: loop_1_backedge.loopexit: 2059; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 2060; CHECK: loop_1_backedge.loopexit1: 2061; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 2062; CHECK: loop_1_backedge: 2063; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2064; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2065; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2066; CHECK: exit: 2067; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2068; CHECK-NEXT: ret i32 [[I_LCSSA]] 2069; 2070preheader: 2071 br label %loop_1 2072 2073loop_1: 2074 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2075 br label %loop_2 2076 2077loop_2: 2078 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2079 br label %loop_3 2080 2081loop_3: 2082 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2083 br i1 %cond1, label %loop_3_backedge, label %intermediate 2084 2085intermediate: 2086 br label %intermediate_loop 2087 2088intermediate_loop: 2089 br i1 %cond3, label %intermediate_loop, label %intermediate_exit 2090 2091intermediate_exit: 2092 switch i32 1, label %loop_1_backedge [i32 0, label %loop_3_backedge] 2093 2094loop_3_backedge: 2095 %k.next = add i32 %k, 1 2096 br i1 %cond2, label %loop_3, label %loop_2_backedge 2097 2098loop_2_backedge: 2099 %j.next = add i32 %j, 1 2100 %c_2 = icmp slt i32 %j.next, %N 2101 br i1 %c_2, label %loop_2, label %loop_1_backedge 2102 2103loop_1_backedge: 2104 %i.next = add i32 %i, 1 2105 %c_1 = icmp slt i32 %i.next, %N 2106 br i1 %c_1, label %loop_1, label %exit 2107 2108exit: 2109 ret i32 %i 2110} 2111 2112define i32 @intermediate_subloop_branch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2113; CHECK-LABEL: @intermediate_subloop_branch_from_inner_to_parent( 2114; CHECK-NEXT: preheader: 2115; CHECK-NEXT: br label [[LOOP_1:%.*]] 2116; CHECK: loop_1: 2117; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2118; CHECK-NEXT: br label [[LOOP_2:%.*]] 2119; CHECK: loop_2: 2120; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2121; CHECK-NEXT: br label [[LOOP_3:%.*]] 2122; CHECK: loop_3: 2123; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2124; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2125; CHECK: intermediate: 2126; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2127; CHECK: intermediate_loop: 2128; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]] 2129; CHECK: intermediate_exit: 2130; CHECK-NEXT: br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_2_BACKEDGE]] 2131; CHECK: loop_3_backedge: 2132; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2133; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2134; CHECK: loop_2_backedge: 2135; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2136; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2137; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]] 2138; CHECK: loop_1_backedge: 2139; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2140; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2141; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2142; CHECK: exit: 2143; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2144; CHECK-NEXT: ret i32 [[I_LCSSA]] 2145; 2146preheader: 2147 br label %loop_1 2148 2149loop_1: 2150 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2151 br label %loop_2 2152 2153loop_2: 2154 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2155 br label %loop_3 2156 2157loop_3: 2158 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2159 br i1 %cond1, label %loop_3_backedge, label %intermediate 2160 2161intermediate: 2162 br label %intermediate_loop 2163 2164intermediate_loop: 2165 br i1 %cond3, label %intermediate_loop, label %intermediate_exit 2166 2167intermediate_exit: 2168 br i1 false, label %loop_3_backedge, label %loop_2_backedge 2169 2170loop_3_backedge: 2171 %k.next = add i32 %k, 1 2172 br i1 %cond2, label %loop_3, label %loop_2_backedge 2173 2174loop_2_backedge: 2175 %j.next = add i32 %j, 1 2176 %c_2 = icmp slt i32 %j.next, %N 2177 br i1 %c_2, label %loop_2, label %loop_1_backedge 2178 2179loop_1_backedge: 2180 %i.next = add i32 %i, 1 2181 %c_1 = icmp slt i32 %i.next, %N 2182 br i1 %c_1, label %loop_1, label %exit 2183 2184exit: 2185 ret i32 %i 2186} 2187 2188define i32 @intermediate_subloop_switch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2189; CHECK-LABEL: @intermediate_subloop_switch_from_inner_to_parent( 2190; CHECK-NEXT: preheader: 2191; CHECK-NEXT: br label [[LOOP_1:%.*]] 2192; CHECK: loop_1: 2193; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2194; CHECK-NEXT: br label [[LOOP_2:%.*]] 2195; CHECK: loop_2: 2196; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2197; CHECK-NEXT: br label [[LOOP_3:%.*]] 2198; CHECK: loop_3: 2199; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2200; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2201; CHECK: intermediate: 2202; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2203; CHECK: intermediate_loop: 2204; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP]], label [[INTERMEDIATE_EXIT:%.*]] 2205; CHECK: intermediate_exit: 2206; CHECK-NEXT: switch i32 1, label [[LOOP_2_BACKEDGE]] [ 2207; CHECK-NEXT: i32 0, label [[LOOP_3_BACKEDGE]] 2208; CHECK-NEXT: ] 2209; CHECK: loop_3_backedge: 2210; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2211; CHECK-NEXT: br i1 [[COND2:%.*]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2212; CHECK: loop_2_backedge: 2213; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2214; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2215; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]] 2216; CHECK: loop_1_backedge: 2217; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2218; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2219; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2220; CHECK: exit: 2221; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2222; CHECK-NEXT: ret i32 [[I_LCSSA]] 2223; 2224preheader: 2225 br label %loop_1 2226 2227loop_1: 2228 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2229 br label %loop_2 2230 2231loop_2: 2232 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2233 br label %loop_3 2234 2235loop_3: 2236 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2237 br i1 %cond1, label %loop_3_backedge, label %intermediate 2238 2239intermediate: 2240 br label %intermediate_loop 2241 2242intermediate_loop: 2243 br i1 %cond3, label %intermediate_loop, label %intermediate_exit 2244 2245intermediate_exit: 2246 switch i32 1, label %loop_2_backedge [i32 0, label %loop_3_backedge] 2247 2248loop_3_backedge: 2249 %k.next = add i32 %k, 1 2250 br i1 %cond2, label %loop_3, label %loop_2_backedge 2251 2252loop_2_backedge: 2253 %j.next = add i32 %j, 1 2254 %c_2 = icmp slt i32 %j.next, %N 2255 br i1 %c_2, label %loop_2, label %loop_1_backedge 2256 2257loop_1_backedge: 2258 %i.next = add i32 %i, 1 2259 %c_1 = icmp slt i32 %i.next, %N 2260 br i1 %c_1, label %loop_1, label %exit 2261 2262exit: 2263 ret i32 %i 2264} 2265 2266define i32 @intermediate_complex_subloop_branch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2267; CHECK-LABEL: @intermediate_complex_subloop_branch_from_inner_to_parent( 2268; CHECK-NEXT: preheader: 2269; CHECK-NEXT: br label [[LOOP_1:%.*]] 2270; CHECK: loop_1: 2271; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2272; CHECK-NEXT: br label [[LOOP_2:%.*]] 2273; CHECK: loop_2: 2274; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2275; CHECK-NEXT: br label [[LOOP_3:%.*]] 2276; CHECK: loop_3: 2277; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2278; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2279; CHECK: intermediate: 2280; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2281; CHECK: intermediate_loop: 2282; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]] 2283; CHECK: intermediate_loop.backedge: 2284; CHECK-NEXT: br label [[INTERMEDIATE_LOOP]] 2285; CHECK: intermediate_block: 2286; CHECK-NEXT: br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]] 2287; CHECK: intermediate_exit: 2288; CHECK-NEXT: br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_2_BACKEDGE]] 2289; CHECK: loop_3_backedge: 2290; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2291; CHECK-NEXT: br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2292; CHECK: loop_2_backedge: 2293; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2294; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2295; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]] 2296; CHECK: loop_1_backedge: 2297; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2298; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2299; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2300; CHECK: exit: 2301; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2302; CHECK-NEXT: ret i32 [[I_LCSSA]] 2303; 2304preheader: 2305 br label %loop_1 2306 2307loop_1: 2308 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2309 br label %loop_2 2310 2311loop_2: 2312 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2313 br label %loop_3 2314 2315loop_3: 2316 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2317 br i1 %cond1, label %loop_3_backedge, label %intermediate 2318 2319intermediate: 2320 br label %intermediate_loop 2321 2322intermediate_loop: 2323 br i1 %cond3, label %intermediate_loop, label %intermediate_block 2324 2325intermediate_block: 2326 br i1 %cond2, label %intermediate_loop, label %intermediate_exit 2327 2328intermediate_exit: 2329 br i1 false, label %loop_3_backedge, label %loop_2_backedge 2330 2331loop_3_backedge: 2332 %k.next = add i32 %k, 1 2333 br i1 %cond2, label %loop_3, label %loop_2_backedge 2334 2335loop_2_backedge: 2336 %j.next = add i32 %j, 1 2337 %c_2 = icmp slt i32 %j.next, %N 2338 br i1 %c_2, label %loop_2, label %loop_1_backedge 2339 2340loop_1_backedge: 2341 %i.next = add i32 %i, 1 2342 %c_1 = icmp slt i32 %i.next, %N 2343 br i1 %c_1, label %loop_1, label %exit 2344 2345exit: 2346 ret i32 %i 2347} 2348 2349define i32 @intermediate_complex_subloop_switch_from_inner_to_parent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2350; CHECK-LABEL: @intermediate_complex_subloop_switch_from_inner_to_parent( 2351; CHECK-NEXT: preheader: 2352; CHECK-NEXT: br label [[LOOP_1:%.*]] 2353; CHECK: loop_1: 2354; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2355; CHECK-NEXT: br label [[LOOP_2:%.*]] 2356; CHECK: loop_2: 2357; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2358; CHECK-NEXT: br label [[LOOP_3:%.*]] 2359; CHECK: loop_3: 2360; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2361; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2362; CHECK: intermediate: 2363; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2364; CHECK: intermediate_loop: 2365; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]] 2366; CHECK: intermediate_loop.backedge: 2367; CHECK-NEXT: br label [[INTERMEDIATE_LOOP]] 2368; CHECK: intermediate_block: 2369; CHECK-NEXT: br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]] 2370; CHECK: intermediate_exit: 2371; CHECK-NEXT: switch i32 1, label [[LOOP_2_BACKEDGE]] [ 2372; CHECK-NEXT: i32 0, label [[LOOP_3_BACKEDGE]] 2373; CHECK-NEXT: ] 2374; CHECK: loop_3_backedge: 2375; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2376; CHECK-NEXT: br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2377; CHECK: loop_2_backedge: 2378; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2379; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2380; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE]] 2381; CHECK: loop_1_backedge: 2382; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2383; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2384; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2385; CHECK: exit: 2386; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2387; CHECK-NEXT: ret i32 [[I_LCSSA]] 2388; 2389preheader: 2390 br label %loop_1 2391 2392loop_1: 2393 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2394 br label %loop_2 2395 2396loop_2: 2397 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2398 br label %loop_3 2399 2400loop_3: 2401 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2402 br i1 %cond1, label %loop_3_backedge, label %intermediate 2403 2404intermediate: 2405 br label %intermediate_loop 2406 2407intermediate_loop: 2408 br i1 %cond3, label %intermediate_loop, label %intermediate_block 2409 2410intermediate_block: 2411 br i1 %cond2, label %intermediate_loop, label %intermediate_exit 2412 2413intermediate_exit: 2414 switch i32 1, label %loop_2_backedge [i32 0, label %loop_3_backedge] 2415 2416loop_3_backedge: 2417 %k.next = add i32 %k, 1 2418 br i1 %cond2, label %loop_3, label %loop_2_backedge 2419 2420loop_2_backedge: 2421 %j.next = add i32 %j, 1 2422 %c_2 = icmp slt i32 %j.next, %N 2423 br i1 %c_2, label %loop_2, label %loop_1_backedge 2424 2425loop_1_backedge: 2426 %i.next = add i32 %i, 1 2427 %c_1 = icmp slt i32 %i.next, %N 2428 br i1 %c_1, label %loop_1, label %exit 2429 2430exit: 2431 ret i32 %i 2432} 2433 2434 2435define i32 @intermediate_complex_subloop_branch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2436; CHECK-LABEL: @intermediate_complex_subloop_branch_from_inner_to_grandparent( 2437; CHECK-NEXT: preheader: 2438; CHECK-NEXT: br label [[LOOP_1:%.*]] 2439; CHECK: loop_1: 2440; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2441; CHECK-NEXT: br label [[LOOP_2:%.*]] 2442; CHECK: loop_2: 2443; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2444; CHECK-NEXT: br label [[LOOP_3:%.*]] 2445; CHECK: loop_3: 2446; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2447; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2448; CHECK: intermediate: 2449; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2450; CHECK: intermediate_loop: 2451; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]] 2452; CHECK: intermediate_loop.backedge: 2453; CHECK-NEXT: br label [[INTERMEDIATE_LOOP]] 2454; CHECK: intermediate_block: 2455; CHECK-NEXT: br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]] 2456; CHECK: intermediate_exit: 2457; CHECK-NEXT: br i1 false, label [[LOOP_3_BACKEDGE]], label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] 2458; CHECK: loop_3_backedge: 2459; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2460; CHECK-NEXT: br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2461; CHECK: loop_2_backedge: 2462; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2463; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2464; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 2465; CHECK: loop_1_backedge.loopexit: 2466; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 2467; CHECK: loop_1_backedge.loopexit1: 2468; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 2469; CHECK: loop_1_backedge: 2470; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2471; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2472; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2473; CHECK: exit: 2474; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2475; CHECK-NEXT: ret i32 [[I_LCSSA]] 2476; 2477preheader: 2478 br label %loop_1 2479 2480loop_1: 2481 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2482 br label %loop_2 2483 2484loop_2: 2485 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2486 br label %loop_3 2487 2488loop_3: 2489 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2490 br i1 %cond1, label %loop_3_backedge, label %intermediate 2491 2492intermediate: 2493 br label %intermediate_loop 2494 2495intermediate_loop: 2496 br i1 %cond3, label %intermediate_loop, label %intermediate_block 2497 2498intermediate_block: 2499 br i1 %cond2, label %intermediate_loop, label %intermediate_exit 2500 2501intermediate_exit: 2502 br i1 false, label %loop_3_backedge, label %loop_1_backedge 2503 2504loop_3_backedge: 2505 %k.next = add i32 %k, 1 2506 br i1 %cond2, label %loop_3, label %loop_2_backedge 2507 2508loop_2_backedge: 2509 %j.next = add i32 %j, 1 2510 %c_2 = icmp slt i32 %j.next, %N 2511 br i1 %c_2, label %loop_2, label %loop_1_backedge 2512 2513loop_1_backedge: 2514 %i.next = add i32 %i, 1 2515 %c_1 = icmp slt i32 %i.next, %N 2516 br i1 %c_1, label %loop_1, label %exit 2517 2518exit: 2519 ret i32 %i 2520} 2521 2522define i32 @intermediate_complex_subloop_switch_from_inner_to_grandparent(i1 %cond1, i1 %cond2, i1 %cond3, i32 %N) { 2523; CHECK-LABEL: @intermediate_complex_subloop_switch_from_inner_to_grandparent( 2524; CHECK-NEXT: preheader: 2525; CHECK-NEXT: br label [[LOOP_1:%.*]] 2526; CHECK: loop_1: 2527; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[PREHEADER:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP_1_BACKEDGE:%.*]] ] 2528; CHECK-NEXT: br label [[LOOP_2:%.*]] 2529; CHECK: loop_2: 2530; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[LOOP_1]] ], [ [[J_NEXT:%.*]], [[LOOP_2_BACKEDGE:%.*]] ] 2531; CHECK-NEXT: br label [[LOOP_3:%.*]] 2532; CHECK: loop_3: 2533; CHECK-NEXT: [[K:%.*]] = phi i32 [ 0, [[LOOP_2]] ], [ [[K_NEXT:%.*]], [[LOOP_3_BACKEDGE:%.*]] ] 2534; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP_3_BACKEDGE]], label [[INTERMEDIATE:%.*]] 2535; CHECK: intermediate: 2536; CHECK-NEXT: br label [[INTERMEDIATE_LOOP:%.*]] 2537; CHECK: intermediate_loop: 2538; CHECK-NEXT: br i1 [[COND3:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE:%.*]], label [[INTERMEDIATE_BLOCK:%.*]] 2539; CHECK: intermediate_loop.backedge: 2540; CHECK-NEXT: br label [[INTERMEDIATE_LOOP]] 2541; CHECK: intermediate_block: 2542; CHECK-NEXT: br i1 [[COND2:%.*]], label [[INTERMEDIATE_LOOP_BACKEDGE]], label [[INTERMEDIATE_EXIT:%.*]] 2543; CHECK: intermediate_exit: 2544; CHECK-NEXT: switch i32 1, label [[LOOP_1_BACKEDGE_LOOPEXIT:%.*]] [ 2545; CHECK-NEXT: i32 0, label [[LOOP_3_BACKEDGE]] 2546; CHECK-NEXT: ] 2547; CHECK: loop_3_backedge: 2548; CHECK-NEXT: [[K_NEXT]] = add i32 [[K]], 1 2549; CHECK-NEXT: br i1 [[COND2]], label [[LOOP_3]], label [[LOOP_2_BACKEDGE]] 2550; CHECK: loop_2_backedge: 2551; CHECK-NEXT: [[J_NEXT]] = add i32 [[J]], 1 2552; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[J_NEXT]], [[N:%.*]] 2553; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2]], label [[LOOP_1_BACKEDGE_LOOPEXIT1:%.*]] 2554; CHECK: loop_1_backedge.loopexit: 2555; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 2556; CHECK: loop_1_backedge.loopexit1: 2557; CHECK-NEXT: br label [[LOOP_1_BACKEDGE]] 2558; CHECK: loop_1_backedge: 2559; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 2560; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[I_NEXT]], [[N]] 2561; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_1]], label [[EXIT:%.*]] 2562; CHECK: exit: 2563; CHECK-NEXT: [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[LOOP_1_BACKEDGE]] ] 2564; CHECK-NEXT: ret i32 [[I_LCSSA]] 2565; 2566preheader: 2567 br label %loop_1 2568 2569loop_1: 2570 %i = phi i32 [ 0, %preheader ], [ %i.next, %loop_1_backedge ] 2571 br label %loop_2 2572 2573loop_2: 2574 %j = phi i32 [ 0, %loop_1 ], [ %j.next, %loop_2_backedge ] 2575 br label %loop_3 2576 2577loop_3: 2578 %k = phi i32 [ 0, %loop_2 ], [ %k.next, %loop_3_backedge ] 2579 br i1 %cond1, label %loop_3_backedge, label %intermediate 2580 2581intermediate: 2582 br label %intermediate_loop 2583 2584intermediate_loop: 2585 br i1 %cond3, label %intermediate_loop, label %intermediate_block 2586 2587intermediate_block: 2588 br i1 %cond2, label %intermediate_loop, label %intermediate_exit 2589 2590intermediate_exit: 2591 switch i32 1, label %loop_1_backedge [i32 0, label %loop_3_backedge] 2592 2593loop_3_backedge: 2594 %k.next = add i32 %k, 1 2595 br i1 %cond2, label %loop_3, label %loop_2_backedge 2596 2597loop_2_backedge: 2598 %j.next = add i32 %j, 1 2599 %c_2 = icmp slt i32 %j.next, %N 2600 br i1 %c_2, label %loop_2, label %loop_1_backedge 2601 2602loop_1_backedge: 2603 %i.next = add i32 %i, 1 2604 %c_1 = icmp slt i32 %i.next, %N 2605 br i1 %c_1, label %loop_1, label %exit 2606 2607exit: 2608 ret i32 %i 2609} 2610