1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -S -loop-rotate -o - -verify-loop-info -verify-dom-info | FileCheck %s
3
4@d = external global i64, align 8
5@f = external global i32, align 4
6@g = external global i32, align 4
7@i = external global i32, align 4
8@h = external global i32, align 4
9
10define i32 @o() #0 {
11; CHECK-LABEL: @o(
12; CHECK-NEXT:    [[TMP1:%.*]] = alloca [1 x i32], align 4
13; CHECK-NEXT:    [[TMP2:%.*]] = load i8*, i8** bitcast (i64* @d to i8**), align 8
14; CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* @f, align 4
15; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
16; CHECK-NEXT:    br i1 [[TMP4]], label [[TMP17:%.*]], label [[DOTLR_PH2:%.*]]
17; CHECK:       .lr.ph2:
18; CHECK-NEXT:    br label [[TMP5:%.*]]
19; CHECK:         [[TMP6:%.*]] = phi i32 [ [[TMP3]], [[DOTLR_PH2]] ], [ [[TMP15:%.*]], [[M_EXIT:%.*]] ]
20; CHECK-NEXT:    [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 4
21; CHECK-NEXT:    [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
22; CHECK-NEXT:    store i32 [[TMP8]], i32* @g, align 4
23; CHECK-NEXT:    [[TMP9:%.*]] = bitcast [1 x i32]* [[TMP1]] to i8*
24; CHECK-NEXT:    [[TMP10:%.*]] = call i32 @n(i8* nonnull [[TMP9]], i8* [[TMP2]])
25; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
26; CHECK-NEXT:    br i1 [[TMP11]], label [[THREAD_PRE_SPLIT:%.*]], label [[DOT_CRIT_EDGE:%.*]]
27; CHECK:       thread-pre-split:
28; CHECK-NEXT:    [[DOTPR:%.*]] = load i32, i32* @i, align 4
29; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[DOTPR]], 0
30; CHECK-NEXT:    br i1 [[TMP12]], label [[M_EXIT]], label [[DOTLR_PH:%.*]]
31; CHECK:       .lr.ph:
32; CHECK-NEXT:    br label [[TMP13:%.*]]
33; CHECK:         [[DOT11:%.*]] = phi i32 [ undef, [[DOTLR_PH]] ], [ [[TMP14:%.*]], [[J_EXIT_I:%.*]] ]
34; CHECK-NEXT:    callbr void asm sideeffect "", "i,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@o, [[M_EXIT]])) #1
35; CHECK-NEXT:    to label [[J_EXIT_I]] [label %m.exit]
36; CHECK:       j.exit.i:
37; CHECK-NEXT:    [[TMP14]] = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #2
38; CHECK-NEXT:    br i1 [[TMP12]], label [[DOTM_EXIT_CRIT_EDGE:%.*]], label [[TMP13]]
39; CHECK:       .m.exit_crit_edge:
40; CHECK-NEXT:    [[SPLIT:%.*]] = phi i32 [ [[TMP14]], [[J_EXIT_I]] ]
41; CHECK-NEXT:    br label [[M_EXIT]]
42; CHECK:       m.exit:
43; CHECK-NEXT:    [[DOT1_LCSSA:%.*]] = phi i32 [ [[DOT11]], [[TMP13]] ], [ [[SPLIT]], [[DOTM_EXIT_CRIT_EDGE]] ], [ undef, [[THREAD_PRE_SPLIT]] ]
44; CHECK-NEXT:    store i32 [[DOT1_LCSSA]], i32* @h, align 4
45; CHECK-NEXT:    [[TMP15]] = load i32, i32* @f, align 4
46; CHECK-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
47; CHECK-NEXT:    br i1 [[TMP16]], label [[DOT_CRIT_EDGE3:%.*]], label [[TMP5]]
48; CHECK:       ._crit_edge:
49; CHECK-NEXT:    br label [[TMP17]]
50; CHECK:       ._crit_edge3:
51; CHECK-NEXT:    br label [[TMP17]]
52; CHECK:         ret i32 undef
53;
54  %1 = alloca [1 x i32], align 4
55  %2 = load i8*, i8** bitcast (i64* @d to i8**), align 8
56  br label %3
57
58; <label>:3:                                      ; preds = %m.exit, %0
59  %4 = load i32, i32* @f, align 4
60  %5 = icmp eq i32 %4, 0
61  br i1 %5, label %16, label %6
62
63; <label>:6:                                      ; preds = %3
64  %7 = icmp ult i32 %4, 4
65  %8 = zext i1 %7 to i32
66  store i32 %8, i32* @g, align 4
67  %9 = bitcast [1 x i32]* %1 to i8*
68  %10 = call i32 @n(i8* nonnull %9, i8* %2)
69  %11 = icmp eq i32 %10, 0
70  br i1 %11, label %thread-pre-split, label %16
71
72thread-pre-split:                                 ; preds = %6
73  %.pr = load i32, i32* @i, align 4
74  br label %12
75
76; <label>:12:                                     ; preds = %j.exit.i, %thread-pre-split
77  %.1 = phi i32 [ %15, %j.exit.i ], [ undef, %thread-pre-split ]
78  %13 = icmp eq i32 %.pr, 0
79  br i1 %13, label %m.exit, label %14
80
81; <label>:14:                                     ; preds = %12
82  callbr void asm sideeffect "", "i,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@o, %m.exit)) #1
83  to label %j.exit.i [label %m.exit]
84
85j.exit.i:                                         ; preds = %14
86  %15 = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #2
87  br label %12
88
89m.exit:                                           ; preds = %14, %12
90  %.1.lcssa = phi i32 [ %.1, %14 ], [ %.1, %12 ]
91  store i32 %.1.lcssa, i32* @h, align 4
92  br label %3
93
94; <label>:16:                                     ; preds = %6, %3
95  ret i32 undef
96}
97
98declare i32 @n(i8*, i8*)  #0
99
100attributes #0 = { "use-soft-float"="false" }
101attributes #1 = { nounwind }
102attributes #2 = { nounwind readnone }
103