1; RUN: opt -S -load-store-vectorizer -mattr=-unaligned-buffer-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s 2; RUN: opt -S -load-store-vectorizer -mattr=+unaligned-buffer-access,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s 3 4target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" 5target triple = "amdgcn--" 6 7; ALL-LABEL: @load_unknown_offset_align1_i8( 8; ALL: alloca [128 x i8], align 1 9; UNALIGNED: load <2 x i8>, <2 x i8>* %{{[0-9]+}}, align 1{{$}} 10 11; ALIGNED: load i8, i8* %ptr0, align 1{{$}} 12; ALIGNED: load i8, i8* %ptr1, align 1{{$}} 13define amdgpu_kernel void @load_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 { 14 %alloca = alloca [128 x i8], align 1 15 %ptr0 = getelementptr inbounds [128 x i8], [128 x i8]* %alloca, i32 0, i32 %offset 16 %val0 = load i8, i8* %ptr0, align 1 17 %ptr1 = getelementptr inbounds i8, i8* %ptr0, i32 1 18 %val1 = load i8, i8* %ptr1, align 1 19 %add = add i8 %val0, %val1 20 store i8 %add, i8 addrspace(1)* %out 21 ret void 22} 23 24; ALL-LABEL: @load_unknown_offset_align1_i16( 25; ALL: alloca [128 x i16], align 1{{$}} 26; UNALIGNED: load <2 x i16>, <2 x i16>* %{{[0-9]+}}, align 1{{$}} 27 28; ALIGNED: load i16, i16* %ptr0, align 1{{$}} 29; ALIGNED: load i16, i16* %ptr1, align 1{{$}} 30define amdgpu_kernel void @load_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 { 31 %alloca = alloca [128 x i16], align 1 32 %ptr0 = getelementptr inbounds [128 x i16], [128 x i16]* %alloca, i32 0, i32 %offset 33 %val0 = load i16, i16* %ptr0, align 1 34 %ptr1 = getelementptr inbounds i16, i16* %ptr0, i32 1 35 %val1 = load i16, i16* %ptr1, align 1 36 %add = add i16 %val0, %val1 37 store i16 %add, i16 addrspace(1)* %out 38 ret void 39} 40 41; FIXME: Although the offset is unknown here, we know it is a multiple 42; of the element size, so should still be align 4 43 44; ALL-LABEL: @load_unknown_offset_align1_i32( 45; ALL: alloca [128 x i32], align 1 46; UNALIGNED: load <2 x i32>, <2 x i32>* %{{[0-9]+}}, align 1{{$}} 47 48; ALIGNED: load i32, i32* %ptr0, align 1 49; ALIGNED: load i32, i32* %ptr1, align 1 50define amdgpu_kernel void @load_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { 51 %alloca = alloca [128 x i32], align 1 52 %ptr0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca, i32 0, i32 %offset 53 %val0 = load i32, i32* %ptr0, align 1 54 %ptr1 = getelementptr inbounds i32, i32* %ptr0, i32 1 55 %val1 = load i32, i32* %ptr1, align 1 56 %add = add i32 %val0, %val1 57 store i32 %add, i32 addrspace(1)* %out 58 ret void 59} 60 61; FIXME: Should always increase alignment of the load 62; Make sure alloca alignment isn't decreased 63; ALL-LABEL: @load_alloca16_unknown_offset_align1_i32( 64; ALL: alloca [128 x i32], align 16 65 66; UNALIGNED: load <2 x i32>, <2 x i32>* %{{[0-9]+}}, align 1{{$}} 67 68; FIXME: Should change alignment 69; ALIGNED: load i32 70; ALIGNED: load i32 71define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { 72 %alloca = alloca [128 x i32], align 16 73 %ptr0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca, i32 0, i32 %offset 74 %val0 = load i32, i32* %ptr0, align 1 75 %ptr1 = getelementptr inbounds i32, i32* %ptr0, i32 1 76 %val1 = load i32, i32* %ptr1, align 1 77 %add = add i32 %val0, %val1 78 store i32 %add, i32 addrspace(1)* %out 79 ret void 80} 81 82; ALL-LABEL: @store_unknown_offset_align1_i8( 83; ALL: alloca [128 x i8], align 1 84; UNALIGNED: store <2 x i8> <i8 9, i8 10>, <2 x i8>* %{{[0-9]+}}, align 1{{$}} 85 86; ALIGNED: store i8 9, i8* %ptr0, align 1{{$}} 87; ALIGNED: store i8 10, i8* %ptr1, align 1{{$}} 88define amdgpu_kernel void @store_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 { 89 %alloca = alloca [128 x i8], align 1 90 %ptr0 = getelementptr inbounds [128 x i8], [128 x i8]* %alloca, i32 0, i32 %offset 91 store i8 9, i8* %ptr0, align 1 92 %ptr1 = getelementptr inbounds i8, i8* %ptr0, i32 1 93 store i8 10, i8* %ptr1, align 1 94 ret void 95} 96 97; ALL-LABEL: @store_unknown_offset_align1_i16( 98; ALL: alloca [128 x i16], align 1 99; UNALIGNED: store <2 x i16> <i16 9, i16 10>, <2 x i16>* %{{[0-9]+}}, align 1{{$}} 100 101; ALIGNED: store i16 9, i16* %ptr0, align 1{{$}} 102; ALIGNED: store i16 10, i16* %ptr1, align 1{{$}} 103define amdgpu_kernel void @store_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 { 104 %alloca = alloca [128 x i16], align 1 105 %ptr0 = getelementptr inbounds [128 x i16], [128 x i16]* %alloca, i32 0, i32 %offset 106 store i16 9, i16* %ptr0, align 1 107 %ptr1 = getelementptr inbounds i16, i16* %ptr0, i32 1 108 store i16 10, i16* %ptr1, align 1 109 ret void 110} 111 112; FIXME: Although the offset is unknown here, we know it is a multiple 113; of the element size, so it still should be align 4. 114 115; ALL-LABEL: @store_unknown_offset_align1_i32( 116; ALL: alloca [128 x i32], align 1 117 118; UNALIGNED: store <2 x i32> <i32 9, i32 10>, <2 x i32>* %{{[0-9]+}}, align 1{{$}} 119 120; ALIGNED: store i32 9, i32* %ptr0, align 1 121; ALIGNED: store i32 10, i32* %ptr1, align 1 122define amdgpu_kernel void @store_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { 123 %alloca = alloca [128 x i32], align 1 124 %ptr0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca, i32 0, i32 %offset 125 store i32 9, i32* %ptr0, align 1 126 %ptr1 = getelementptr inbounds i32, i32* %ptr0, i32 1 127 store i32 10, i32* %ptr1, align 1 128 ret void 129} 130 131attributes #0 = { nounwind } 132 133