1; RUN: opt -S -load-store-vectorizer -mattr=-unaligned-buffer-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s 2; RUN: opt -S -load-store-vectorizer -mattr=+unaligned-buffer-access,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s 3 4target triple = "amdgcn--" 5target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" 6 7; ALL-LABEL: @load_unknown_offset_align1_i8( 8; ALL: alloca [128 x i8], align 1 9; UNALIGNED: load <2 x i8>, <2 x i8> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 10 11; ALIGNED: load i8, i8 addrspace(5)* %ptr0, align 1{{$}} 12; ALIGNED: load i8, i8 addrspace(5)* %ptr1, align 1{{$}} 13define amdgpu_kernel void @load_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 { 14 %alloca = alloca [128 x i8], align 1, addrspace(5) 15 %ptr0 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %alloca, i32 0, i32 %offset 16 %val0 = load i8, i8 addrspace(5)* %ptr0, align 1 17 %ptr1 = getelementptr inbounds i8, i8 addrspace(5)* %ptr0, i32 1 18 %val1 = load i8, i8 addrspace(5)* %ptr1, align 1 19 %add = add i8 %val0, %val1 20 store i8 %add, i8 addrspace(1)* %out 21 ret void 22} 23 24; ALL-LABEL: @load_unknown_offset_align1_i16( 25; ALL: alloca [128 x i16], align 1, addrspace(5){{$}} 26; UNALIGNED: load <2 x i16>, <2 x i16> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 27 28; ALIGNED: load i16, i16 addrspace(5)* %ptr0, align 1{{$}} 29; ALIGNED: load i16, i16 addrspace(5)* %ptr1, align 1{{$}} 30define amdgpu_kernel void @load_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 { 31 %alloca = alloca [128 x i16], align 1, addrspace(5) 32 %ptr0 = getelementptr inbounds [128 x i16], [128 x i16] addrspace(5)* %alloca, i32 0, i32 %offset 33 %val0 = load i16, i16 addrspace(5)* %ptr0, align 1 34 %ptr1 = getelementptr inbounds i16, i16 addrspace(5)* %ptr0, i32 1 35 %val1 = load i16, i16 addrspace(5)* %ptr1, align 1 36 %add = add i16 %val0, %val1 37 store i16 %add, i16 addrspace(1)* %out 38 ret void 39} 40 41; FIXME: Although the offset is unknown here, we know it is a multiple 42; of the element size, so should still be align 4 43 44; ALL-LABEL: @load_unknown_offset_align1_i32( 45; ALL: alloca [128 x i32], align 1 46; UNALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 47 48; ALIGNED: load i32, i32 addrspace(5)* %ptr0, align 1 49; ALIGNED: load i32, i32 addrspace(5)* %ptr1, align 1 50define amdgpu_kernel void @load_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { 51 %alloca = alloca [128 x i32], align 1, addrspace(5) 52 %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset 53 %val0 = load i32, i32 addrspace(5)* %ptr0, align 1 54 %ptr1 = getelementptr inbounds i32, i32 addrspace(5)* %ptr0, i32 1 55 %val1 = load i32, i32 addrspace(5)* %ptr1, align 1 56 %add = add i32 %val0, %val1 57 store i32 %add, i32 addrspace(1)* %out 58 ret void 59} 60 61; FIXME: Should always increase alignment of the load 62; Make sure alloca alignment isn't decreased 63; ALL-LABEL: @load_alloca16_unknown_offset_align1_i32( 64; ALL: alloca [128 x i32], align 16 65 66; UNALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 67; ALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 4{{$}} 68define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { 69 %alloca = alloca [128 x i32], align 16, addrspace(5) 70 %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset 71 %val0 = load i32, i32 addrspace(5)* %ptr0, align 1 72 %ptr1 = getelementptr inbounds i32, i32 addrspace(5)* %ptr0, i32 1 73 %val1 = load i32, i32 addrspace(5)* %ptr1, align 1 74 %add = add i32 %val0, %val1 75 store i32 %add, i32 addrspace(1)* %out 76 ret void 77} 78 79; ALL-LABEL: @store_unknown_offset_align1_i8( 80; ALL: alloca [128 x i8], align 1 81; UNALIGNED: store <2 x i8> <i8 9, i8 10>, <2 x i8> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 82 83; ALIGNED: store i8 9, i8 addrspace(5)* %ptr0, align 1{{$}} 84; ALIGNED: store i8 10, i8 addrspace(5)* %ptr1, align 1{{$}} 85define amdgpu_kernel void @store_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 { 86 %alloca = alloca [128 x i8], align 1, addrspace(5) 87 %ptr0 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %alloca, i32 0, i32 %offset 88 store i8 9, i8 addrspace(5)* %ptr0, align 1 89 %ptr1 = getelementptr inbounds i8, i8 addrspace(5)* %ptr0, i32 1 90 store i8 10, i8 addrspace(5)* %ptr1, align 1 91 ret void 92} 93 94; ALL-LABEL: @store_unknown_offset_align1_i16( 95; ALL: alloca [128 x i16], align 1 96; UNALIGNED: store <2 x i16> <i16 9, i16 10>, <2 x i16> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 97 98; ALIGNED: store i16 9, i16 addrspace(5)* %ptr0, align 1{{$}} 99; ALIGNED: store i16 10, i16 addrspace(5)* %ptr1, align 1{{$}} 100define amdgpu_kernel void @store_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 { 101 %alloca = alloca [128 x i16], align 1, addrspace(5) 102 %ptr0 = getelementptr inbounds [128 x i16], [128 x i16] addrspace(5)* %alloca, i32 0, i32 %offset 103 store i16 9, i16 addrspace(5)* %ptr0, align 1 104 %ptr1 = getelementptr inbounds i16, i16 addrspace(5)* %ptr0, i32 1 105 store i16 10, i16 addrspace(5)* %ptr1, align 1 106 ret void 107} 108 109; FIXME: Although the offset is unknown here, we know it is a multiple 110; of the element size, so it still should be align 4. 111 112; ALL-LABEL: @store_unknown_offset_align1_i32( 113; ALL: alloca [128 x i32], align 1 114 115; UNALIGNED: store <2 x i32> <i32 9, i32 10>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}} 116 117; ALIGNED: store i32 9, i32 addrspace(5)* %ptr0, align 1 118; ALIGNED: store i32 10, i32 addrspace(5)* %ptr1, align 1 119define amdgpu_kernel void @store_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { 120 %alloca = alloca [128 x i32], align 1, addrspace(5) 121 %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset 122 store i32 9, i32 addrspace(5)* %ptr0, align 1 123 %ptr1 = getelementptr inbounds i32, i32 addrspace(5)* %ptr0, i32 1 124 store i32 10, i32 addrspace(5)* %ptr1, align 1 125 ret void 126} 127 128; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32( 129; ALIGNED: %alloca = alloca [8 x i32], align 4, addrspace(5) 130; ALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 4 131 132; UNALIGNED: %alloca = alloca [8 x i32], align 1, addrspace(5) 133; UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 1 134define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32() { 135 %alloca = alloca [8 x i32], align 1, addrspace(5) 136 %out = bitcast [8 x i32] addrspace(5)* %alloca to i32 addrspace(5)* 137 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1 138 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2 139 %out.gep.3 = getelementptr i32, i32 addrspace(5)* %out, i32 3 140 141 store i32 9, i32 addrspace(5)* %out, align 1 142 store i32 1, i32 addrspace(5)* %out.gep.1, align 1 143 store i32 23, i32 addrspace(5)* %out.gep.2, align 1 144 store i32 19, i32 addrspace(5)* %out.gep.3, align 1 145 ret void 146} 147 148; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8( 149; ALIGNED: %alloca = alloca [8 x i8], align 4, addrspace(5) 150; ALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8> addrspace(5)* %1, align 4 151 152; UNALIGNED: %alloca = alloca [8 x i8], align 1, addrspace(5) 153; UNALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8> addrspace(5)* %1, align 1 154define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8() { 155 %alloca = alloca [8 x i8], align 1, addrspace(5) 156 %out = bitcast [8 x i8] addrspace(5)* %alloca to i8 addrspace(5)* 157 %out.gep.1 = getelementptr i8, i8 addrspace(5)* %out, i8 1 158 %out.gep.2 = getelementptr i8, i8 addrspace(5)* %out, i8 2 159 %out.gep.3 = getelementptr i8, i8 addrspace(5)* %out, i8 3 160 161 store i8 9, i8 addrspace(5)* %out, align 1 162 store i8 1, i8 addrspace(5)* %out.gep.1, align 1 163 store i8 23, i8 addrspace(5)* %out.gep.2, align 1 164 store i8 19, i8 addrspace(5)* %out.gep.3, align 1 165 ret void 166} 167 168; ALL-LABEL: @merge_private_load_4_vector_elts_loads_v4i32( 169; ALIGNED: %alloca = alloca [8 x i32], align 4, addrspace(5) 170; ALIGNED: load <4 x i32>, <4 x i32> addrspace(5)* %1, align 4 171 172; UNALIGNED: %alloca = alloca [8 x i32], align 1, addrspace(5) 173; UNALIGNED: load <4 x i32>, <4 x i32> addrspace(5)* %1, align 1 174define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i32() { 175 %alloca = alloca [8 x i32], align 1, addrspace(5) 176 %out = bitcast [8 x i32] addrspace(5)* %alloca to i32 addrspace(5)* 177 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1 178 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2 179 %out.gep.3 = getelementptr i32, i32 addrspace(5)* %out, i32 3 180 181 %load0 = load i32, i32 addrspace(5)* %out, align 1 182 %load1 = load i32, i32 addrspace(5)* %out.gep.1, align 1 183 %load2 = load i32, i32 addrspace(5)* %out.gep.2, align 1 184 %load3 = load i32, i32 addrspace(5)* %out.gep.3, align 1 185 ret void 186} 187 188; ALL-LABEL: @merge_private_load_4_vector_elts_loads_v4i8( 189; ALIGNED: %alloca = alloca [8 x i8], align 4, addrspace(5) 190; ALIGNED: load <4 x i8>, <4 x i8> addrspace(5)* %1, align 4 191 192; UNALIGNED: %alloca = alloca [8 x i8], align 1, addrspace(5) 193; UNALIGNED: load <4 x i8>, <4 x i8> addrspace(5)* %1, align 1 194define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i8() { 195 %alloca = alloca [8 x i8], align 1, addrspace(5) 196 %out = bitcast [8 x i8] addrspace(5)* %alloca to i8 addrspace(5)* 197 %out.gep.1 = getelementptr i8, i8 addrspace(5)* %out, i8 1 198 %out.gep.2 = getelementptr i8, i8 addrspace(5)* %out, i8 2 199 %out.gep.3 = getelementptr i8, i8 addrspace(5)* %out, i8 3 200 201 %load0 = load i8, i8 addrspace(5)* %out, align 1 202 %load1 = load i8, i8 addrspace(5)* %out.gep.1, align 1 203 %load2 = load i8, i8 addrspace(5)* %out.gep.2, align 1 204 %load3 = load i8, i8 addrspace(5)* %out.gep.3, align 1 205 ret void 206} 207 208attributes #0 = { nounwind } 209