1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instsimplify -S | FileCheck %s 3 4declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a) 5declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a) 6declare i32 @llvm.vector.reduce.mul.v1i32(<1 x i32> %a) 7declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %a) 8declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a) 9declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %a) 10declare i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %a) 11declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a) 12declare i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %a) 13declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %a) 14declare i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %a) 15declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %a) 16declare i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %a) 17declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %a) 18declare i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %a) 19declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %a) 20declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a) 21declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %a) 22 23 24define i32 @add_0() { 25; CHECK-LABEL: @add_0( 26; CHECK-NEXT: ret i32 0 27; 28 %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> zeroinitializer) 29 ret i32 %x 30} 31 32define i32 @add_1() { 33; CHECK-LABEL: @add_1( 34; CHECK-NEXT: ret i32 8 35; 36 %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 37 ret i32 %x 38} 39 40define i32 @add_inc() { 41; CHECK-LABEL: @add_inc( 42; CHECK-NEXT: ret i32 18 43; 44 %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 45 ret i32 %x 46} 47 48define i32 @add_1v() { 49; CHECK-LABEL: @add_1v( 50; CHECK-NEXT: ret i32 10 51; 52 %x = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> <i32 10>) 53 ret i32 %x 54} 55 56define i32 @add_undef() { 57; CHECK-LABEL: @add_undef( 58; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef) 59; CHECK-NEXT: ret i32 [[X]] 60; 61 %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef) 62 ret i32 %x 63} 64 65define i32 @add_undef1() { 66; CHECK-LABEL: @add_undef1( 67; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 68; CHECK-NEXT: ret i32 [[X]] 69; 70 %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 71 ret i32 %x 72} 73 74 75 76define i32 @mul_0() { 77; CHECK-LABEL: @mul_0( 78; CHECK-NEXT: ret i32 0 79; 80 %x = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> zeroinitializer) 81 ret i32 %x 82} 83 84define i32 @mul_1() { 85; CHECK-LABEL: @mul_1( 86; CHECK-NEXT: ret i32 1 87; 88 %x = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 89 ret i32 %x 90} 91 92define i32 @mul_inc() { 93; CHECK-LABEL: @mul_inc( 94; CHECK-NEXT: ret i32 40320 95; 96 %x = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 97 ret i32 %x 98} 99 100define i32 @mul_1v() { 101; CHECK-LABEL: @mul_1v( 102; CHECK-NEXT: ret i32 10 103; 104 %x = call i32 @llvm.vector.reduce.mul.v1i32(<1 x i32> <i32 10>) 105 ret i32 %x 106} 107 108define i32 @mul_undef() { 109; CHECK-LABEL: @mul_undef( 110; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef) 111; CHECK-NEXT: ret i32 [[X]] 112; 113 %x = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef) 114 ret i32 %x 115} 116 117define i32 @mul_undef1() { 118; CHECK-LABEL: @mul_undef1( 119; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 120; CHECK-NEXT: ret i32 [[X]] 121; 122 %x = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 123 ret i32 %x 124} 125 126 127define i32 @and_0() { 128; CHECK-LABEL: @and_0( 129; CHECK-NEXT: ret i32 0 130; 131 %x = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> zeroinitializer) 132 ret i32 %x 133} 134 135define i32 @and_1() { 136; CHECK-LABEL: @and_1( 137; CHECK-NEXT: ret i32 1 138; 139 %x = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 140 ret i32 %x 141} 142 143define i32 @and_inc() { 144; CHECK-LABEL: @and_inc( 145; CHECK-NEXT: ret i32 0 146; 147 %x = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 148 ret i32 %x 149} 150 151define i32 @and_1v() { 152; CHECK-LABEL: @and_1v( 153; CHECK-NEXT: ret i32 10 154; 155 %x = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> <i32 10>) 156 ret i32 %x 157} 158 159define i32 @and_undef() { 160; CHECK-LABEL: @and_undef( 161; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> undef) 162; CHECK-NEXT: ret i32 [[X]] 163; 164 %x = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> undef) 165 ret i32 %x 166} 167 168define i32 @and_undef1() { 169; CHECK-LABEL: @and_undef1( 170; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 171; CHECK-NEXT: ret i32 [[X]] 172; 173 %x = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 174 ret i32 %x 175} 176 177 178define i32 @or_0() { 179; CHECK-LABEL: @or_0( 180; CHECK-NEXT: ret i32 0 181; 182 %x = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> zeroinitializer) 183 ret i32 %x 184} 185 186define i32 @or_1() { 187; CHECK-LABEL: @or_1( 188; CHECK-NEXT: ret i32 1 189; 190 %x = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 191 ret i32 %x 192} 193 194define i32 @or_inc() { 195; CHECK-LABEL: @or_inc( 196; CHECK-NEXT: ret i32 -1 197; 198 %x = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 199 ret i32 %x 200} 201 202define i32 @or_1v() { 203; CHECK-LABEL: @or_1v( 204; CHECK-NEXT: ret i32 10 205; 206 %x = call i32 @llvm.vector.reduce.or.v1i32(<1 x i32> <i32 10>) 207 ret i32 %x 208} 209 210define i32 @or_undef() { 211; CHECK-LABEL: @or_undef( 212; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef) 213; CHECK-NEXT: ret i32 [[X]] 214; 215 %x = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef) 216 ret i32 %x 217} 218 219define i32 @or_undef1() { 220; CHECK-LABEL: @or_undef1( 221; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 222; CHECK-NEXT: ret i32 [[X]] 223; 224 %x = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 225 ret i32 %x 226} 227 228 229define i32 @xor_0() { 230; CHECK-LABEL: @xor_0( 231; CHECK-NEXT: ret i32 0 232; 233 %x = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> zeroinitializer) 234 ret i32 %x 235} 236 237define i32 @xor_1() { 238; CHECK-LABEL: @xor_1( 239; CHECK-NEXT: ret i32 0 240; 241 %x = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 242 ret i32 %x 243} 244 245define i32 @xor_inc() { 246; CHECK-LABEL: @xor_inc( 247; CHECK-NEXT: ret i32 10 248; 249 %x = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 250 ret i32 %x 251} 252 253define i32 @xor_1v() { 254; CHECK-LABEL: @xor_1v( 255; CHECK-NEXT: ret i32 10 256; 257 %x = call i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> <i32 10>) 258 ret i32 %x 259} 260 261define i32 @xor_undef() { 262; CHECK-LABEL: @xor_undef( 263; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> undef) 264; CHECK-NEXT: ret i32 [[X]] 265; 266 %x = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> undef) 267 ret i32 %x 268} 269 270define i32 @xor_undef1() { 271; CHECK-LABEL: @xor_undef1( 272; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 273; CHECK-NEXT: ret i32 [[X]] 274; 275 %x = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 276 ret i32 %x 277} 278 279 280define i32 @smin_0() { 281; CHECK-LABEL: @smin_0( 282; CHECK-NEXT: ret i32 0 283; 284 %x = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> zeroinitializer) 285 ret i32 %x 286} 287 288define i32 @smin_1() { 289; CHECK-LABEL: @smin_1( 290; CHECK-NEXT: ret i32 1 291; 292 %x = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 293 ret i32 %x 294} 295 296define i32 @smin_inc() { 297; CHECK-LABEL: @smin_inc( 298; CHECK-NEXT: ret i32 -6 299; 300 %x = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 301 ret i32 %x 302} 303 304define i32 @smin_1v() { 305; CHECK-LABEL: @smin_1v( 306; CHECK-NEXT: ret i32 10 307; 308 %x = call i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> <i32 10>) 309 ret i32 %x 310} 311 312define i32 @smin_undef() { 313; CHECK-LABEL: @smin_undef( 314; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef) 315; CHECK-NEXT: ret i32 [[X]] 316; 317 %x = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef) 318 ret i32 %x 319} 320 321define i32 @smin_undef1() { 322; CHECK-LABEL: @smin_undef1( 323; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 324; CHECK-NEXT: ret i32 [[X]] 325; 326 %x = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 327 ret i32 %x 328} 329 330 331define i32 @smax_0() { 332; CHECK-LABEL: @smax_0( 333; CHECK-NEXT: ret i32 0 334; 335 %x = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> zeroinitializer) 336 ret i32 %x 337} 338 339define i32 @smax_1() { 340; CHECK-LABEL: @smax_1( 341; CHECK-NEXT: ret i32 1 342; 343 %x = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 344 ret i32 %x 345} 346 347define i32 @smax_inc() { 348; CHECK-LABEL: @smax_inc( 349; CHECK-NEXT: ret i32 8 350; 351 %x = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 352 ret i32 %x 353} 354 355define i32 @smax_1v() { 356; CHECK-LABEL: @smax_1v( 357; CHECK-NEXT: ret i32 10 358; 359 %x = call i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> <i32 10>) 360 ret i32 %x 361} 362 363define i32 @smax_undef() { 364; CHECK-LABEL: @smax_undef( 365; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef) 366; CHECK-NEXT: ret i32 [[X]] 367; 368 %x = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef) 369 ret i32 %x 370} 371 372define i32 @smax_undef1() { 373; CHECK-LABEL: @smax_undef1( 374; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 375; CHECK-NEXT: ret i32 [[X]] 376; 377 %x = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 378 ret i32 %x 379} 380 381 382define i32 @umin_0() { 383; CHECK-LABEL: @umin_0( 384; CHECK-NEXT: ret i32 0 385; 386 %x = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> zeroinitializer) 387 ret i32 %x 388} 389 390define i32 @umin_1() { 391; CHECK-LABEL: @umin_1( 392; CHECK-NEXT: ret i32 1 393; 394 %x = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 395 ret i32 %x 396} 397 398define i32 @umin_inc() { 399; CHECK-LABEL: @umin_inc( 400; CHECK-NEXT: ret i32 1 401; 402 %x = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 403 ret i32 %x 404} 405 406define i32 @umin_1v() { 407; CHECK-LABEL: @umin_1v( 408; CHECK-NEXT: ret i32 10 409; 410 %x = call i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> <i32 10>) 411 ret i32 %x 412} 413 414define i32 @umin_undef() { 415; CHECK-LABEL: @umin_undef( 416; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef) 417; CHECK-NEXT: ret i32 [[X]] 418; 419 %x = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef) 420 ret i32 %x 421} 422 423define i32 @umin_undef1() { 424; CHECK-LABEL: @umin_undef1( 425; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 426; CHECK-NEXT: ret i32 [[X]] 427; 428 %x = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 429 ret i32 %x 430} 431 432 433define i32 @umax_0() { 434; CHECK-LABEL: @umax_0( 435; CHECK-NEXT: ret i32 0 436; 437 %x = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> zeroinitializer) 438 ret i32 %x 439} 440 441define i32 @umax_1() { 442; CHECK-LABEL: @umax_1( 443; CHECK-NEXT: ret i32 1 444; 445 %x = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 446 ret i32 %x 447} 448 449define i32 @umax_inc() { 450; CHECK-LABEL: @umax_inc( 451; CHECK-NEXT: ret i32 -3 452; 453 %x = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> <i32 1, i32 -3, i32 5, i32 7, i32 2, i32 4, i32 -6, i32 8>) 454 ret i32 %x 455} 456 457define i32 @umax_1v() { 458; CHECK-LABEL: @umax_1v( 459; CHECK-NEXT: ret i32 10 460; 461 %x = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> <i32 10>) 462 ret i32 %x 463} 464 465define i32 @umax_undef() { 466; CHECK-LABEL: @umax_undef( 467; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef) 468; CHECK-NEXT: ret i32 [[X]] 469; 470 %x = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef) 471 ret i32 %x 472} 473 474define i32 @umax_undef1d() { 475; CHECK-LABEL: @umax_undef1d( 476; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 477; CHECK-NEXT: ret i32 [[X]] 478; 479 %x = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1>) 480 ret i32 %x 481} 482