1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
5; CHECK-LABEL: @vec_select(
6; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
7; CHECK-NEXT:    [[ISNEG:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
8; CHECK-NEXT:    [[T2:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> zeroinitializer, <4 x i32> [[A]]
9; CHECK-NEXT:    [[ISNEG1:%.*]] = icmp slt <4 x i32> [[B]], zeroinitializer
10; CHECK-NEXT:    [[T3:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i32> [[SUB]], <4 x i32> zeroinitializer
11; CHECK-NEXT:    [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
12; CHECK-NEXT:    ret <4 x i32> [[COND]]
13;
14  %cmp = icmp slt <4 x i32> %b, zeroinitializer
15  %sext = sext <4 x i1> %cmp to <4 x i32>
16  %sub = sub nsw <4 x i32> zeroinitializer, %a
17  %t0 = icmp slt <4 x i32> %sext, zeroinitializer
18  %sext3 = sext <4 x i1> %t0 to <4 x i32>
19  %t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
20  %t2 = and <4 x i32> %a, %t1
21  %t3 = and <4 x i32> %sext3, %sub
22  %cond = or <4 x i32> %t2, %t3
23  ret <4 x i32> %cond
24}
25
26define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) {
27; CHECK-LABEL: @vec_select_alternate_sign_bit_test(
28; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
29; CHECK-NEXT:    [[ISNEG1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
30; CHECK-NEXT:    [[T2:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i32> [[A]], <4 x i32> zeroinitializer
31; CHECK-NEXT:    [[ISNEG:%.*]] = icmp slt <4 x i32> [[B]], zeroinitializer
32; CHECK-NEXT:    [[T3:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> zeroinitializer, <4 x i32> [[SUB]]
33; CHECK-NEXT:    [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
34; CHECK-NEXT:    ret <4 x i32> [[COND]]
35;
36  %cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
37  %sext = sext <4 x i1> %cmp to <4 x i32>
38  %sub = sub nsw <4 x i32> zeroinitializer, %a
39  %t0 = icmp slt <4 x i32> %sext, zeroinitializer
40  %sext3 = sext <4 x i1> %t0 to <4 x i32>
41  %t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
42  %t2 = and <4 x i32> %a, %t1
43  %t3 = and <4 x i32> %sext3, %sub
44  %cond = or <4 x i32> %t2, %t3
45  ret <4 x i32> %cond
46}
47
48define <2 x i32> @is_negative_undef_elt(<2 x i32> %a) {
49; CHECK-LABEL: @is_negative_undef_elt(
50; CHECK-NEXT:    [[A_LOBIT:%.*]] = ashr <2 x i32> [[A:%.*]], <i32 31, i32 31>
51; CHECK-NEXT:    ret <2 x i32> [[A_LOBIT]]
52;
53  %cmp = icmp slt <2 x i32> %a, <i32 0, i32 undef>
54  %sext = sext <2 x i1> %cmp to <2 x i32>
55  ret <2 x i32> %sext
56
57}
58
59define <2 x i32> @is_positive_undef_elt(<2 x i32> %a) {
60; CHECK-LABEL: @is_positive_undef_elt(
61; CHECK-NEXT:    [[A_LOBIT:%.*]] = ashr <2 x i32> [[A:%.*]], <i32 31, i32 31>
62; CHECK-NEXT:    [[A_LOBIT_NOT:%.*]] = xor <2 x i32> [[A_LOBIT]], <i32 -1, i32 -1>
63; CHECK-NEXT:    ret <2 x i32> [[A_LOBIT_NOT]]
64;
65  %cmp = icmp sgt <2 x i32> %a, <i32 undef, i32 -1>
66  %sext = sext <2 x i1> %cmp to <2 x i32>
67  ret <2 x i32> %sext
68}
69
70