1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4target datalayout = "e-p:64:64:64-p1:16:16:16-p2:32:32:32-p3:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 5 6define i32 @test1(i32 %X) { 7; CHECK-LABEL: @test1( 8; CHECK-NEXT: [[X_LOBIT:%.*]] = lshr i32 %X, 31 9; CHECK-NEXT: ret i32 [[X_LOBIT]] 10; 11 %a = icmp slt i32 %X, 0 12 %b = zext i1 %a to i32 13 ret i32 %b 14} 15 16define i32 @test2(i32 %X) { 17; CHECK-LABEL: @test2( 18; CHECK-NEXT: [[X_LOBIT:%.*]] = lshr i32 %X, 31 19; CHECK-NEXT: [[X_LOBIT_NOT:%.*]] = xor i32 [[X_LOBIT]], 1 20; CHECK-NEXT: ret i32 [[X_LOBIT_NOT]] 21; 22 %a = icmp ult i32 %X, -2147483648 23 %b = zext i1 %a to i32 24 ret i32 %b 25} 26 27define i32 @test3(i32 %X) { 28; CHECK-LABEL: @test3( 29; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 %X, 31 30; CHECK-NEXT: ret i32 [[X_LOBIT]] 31; 32 %a = icmp slt i32 %X, 0 33 %b = sext i1 %a to i32 34 ret i32 %b 35} 36 37define i32 @test4(i32 %X) { 38; CHECK-LABEL: @test4( 39; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 %X, 31 40; CHECK-NEXT: [[X_LOBIT_NOT:%.*]] = xor i32 [[X_LOBIT]], -1 41; CHECK-NEXT: ret i32 [[X_LOBIT_NOT]] 42; 43 %a = icmp ult i32 %X, -2147483648 44 %b = sext i1 %a to i32 45 ret i32 %b 46} 47 48; PR4837 49define <2 x i1> @test5(<2 x i64> %x) { 50; CHECK-LABEL: @test5( 51; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true> 52; 53 %V = icmp eq <2 x i64> %x, undef 54 ret <2 x i1> %V 55} 56 57define i32 @test6(i32 %a, i32 %b) { 58; CHECK-LABEL: @test6( 59; CHECK-NEXT: [[E:%.*]] = ashr i32 %a, 31 60; CHECK-NEXT: [[F:%.*]] = and i32 [[E]], %b 61; CHECK-NEXT: ret i32 [[F]] 62; 63 %c = icmp sle i32 %a, -1 64 %d = zext i1 %c to i32 65 %e = sub i32 0, %d 66 %f = and i32 %e, %b 67 ret i32 %f 68} 69 70 71define i1 @test7(i32 %x) { 72; CHECK-LABEL: @test7( 73; CHECK-NEXT: [[B:%.*]] = icmp ne i32 %x, 0 74; CHECK-NEXT: ret i1 [[B]] 75; 76 %a = add i32 %x, -1 77 %b = icmp ult i32 %a, %x 78 ret i1 %b 79} 80 81define i1 @test8(i32 %x) { 82; CHECK-LABEL: @test8( 83; CHECK-NEXT: ret i1 false 84; 85 %a = add i32 %x, -1 86 %b = icmp eq i32 %a, %x 87 ret i1 %b 88} 89 90define i1 @test9(i32 %x) { 91; CHECK-LABEL: @test9( 92; CHECK-NEXT: [[B:%.*]] = icmp ugt i32 %x, 1 93; CHECK-NEXT: ret i1 [[B]] 94; 95 %a = add i32 %x, -2 96 %b = icmp ugt i32 %x, %a 97 ret i1 %b 98} 99 100define i1 @test10(i32 %x) { 101; CHECK-LABEL: @test10( 102; CHECK-NEXT: [[B:%.*]] = icmp ne i32 %x, -2147483648 103; CHECK-NEXT: ret i1 [[B]] 104; 105 %a = add i32 %x, -1 106 %b = icmp slt i32 %a, %x 107 ret i1 %b 108} 109 110define i1 @test11(i32 %x) { 111; CHECK-LABEL: @test11( 112; CHECK-NEXT: ret i1 true 113; 114 %a = add nsw i32 %x, 8 115 %b = icmp slt i32 %x, %a 116 ret i1 %b 117} 118 119; PR6195 120define i1 @test12(i1 %A) { 121; CHECK-LABEL: @test12( 122; CHECK-NEXT: [[NOT_A:%.*]] = xor i1 %A, true 123; CHECK-NEXT: ret i1 [[NOT_A]] 124; 125 %S = select i1 %A, i64 -4294967295, i64 8589934591 126 %B = icmp ne i64 bitcast (<2 x i32> <i32 1, i32 -1> to i64), %S 127 ret i1 %B 128} 129 130; PR6481 131define i1 @test13(i8 %X) { 132; CHECK-LABEL: @test13( 133; CHECK-NEXT: ret i1 false 134; 135 %cmp = icmp slt i8 undef, %X 136 ret i1 %cmp 137} 138 139define i1 @test14(i8 %X) { 140; CHECK-LABEL: @test14( 141; CHECK-NEXT: ret i1 false 142; 143 %cmp = icmp slt i8 undef, -128 144 ret i1 %cmp 145} 146 147define i1 @test15() { 148; CHECK-LABEL: @test15( 149; CHECK-NEXT: ret i1 undef 150; 151 %cmp = icmp eq i8 undef, -128 152 ret i1 %cmp 153} 154 155define i1 @test16() { 156; CHECK-LABEL: @test16( 157; CHECK-NEXT: ret i1 undef 158; 159 %cmp = icmp ne i8 undef, -128 160 ret i1 %cmp 161} 162 163define i1 @test17(i32 %x) { 164; CHECK-LABEL: @test17( 165; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 %x, 3 166; CHECK-NEXT: ret i1 [[CMP]] 167; 168 %shl = shl i32 1, %x 169 %and = and i32 %shl, 8 170 %cmp = icmp eq i32 %and, 0 171 ret i1 %cmp 172} 173 174define <2 x i1> @test17vec(<2 x i32> %x) { 175; CHECK-LABEL: @test17vec( 176; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, <i32 3, i32 3> 177; CHECK-NEXT: ret <2 x i1> [[CMP]] 178; 179 %shl = shl <2 x i32> <i32 1, i32 1>, %x 180 %and = and <2 x i32> %shl, <i32 8, i32 8> 181 %cmp = icmp eq <2 x i32> %and, zeroinitializer 182 ret <2 x i1> %cmp 183} 184 185define i1 @test17a(i32 %x) { 186; CHECK-LABEL: @test17a( 187; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %x, 2 188; CHECK-NEXT: ret i1 [[CMP]] 189; 190 %shl = shl i32 1, %x 191 %and = and i32 %shl, 7 192 %cmp = icmp eq i32 %and, 0 193 ret i1 %cmp 194} 195 196define <2 x i1> @test17a_vec(<2 x i32> %x) { 197; CHECK-LABEL: @test17a_vec( 198; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %x, <i32 2, i32 2> 199; CHECK-NEXT: ret <2 x i1> [[CMP]] 200; 201 %shl = shl <2 x i32> <i32 1, i32 1>, %x 202 %and = and <2 x i32> %shl, <i32 7, i32 7> 203 %cmp = icmp eq <2 x i32> %and, zeroinitializer 204 ret <2 x i1> %cmp 205} 206 207define i1 @test18_eq(i32 %x) { 208; CHECK-LABEL: @test18_eq( 209; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 %x, 3 210; CHECK-NEXT: ret i1 [[CMP]] 211; 212 %sh = lshr i32 8, %x 213 %and = and i32 %sh, 1 214 %cmp = icmp eq i32 %and, 0 215 ret i1 %cmp 216} 217 218define <2 x i1> @test18_eq_vec(<2 x i32> %x) { 219; CHECK-LABEL: @test18_eq_vec( 220; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, <i32 3, i32 3> 221; CHECK-NEXT: ret <2 x i1> [[CMP]] 222; 223 %sh = lshr <2 x i32> <i32 8, i32 8>, %x 224 %and = and <2 x i32> %sh, <i32 1, i32 1> 225 %cmp = icmp eq <2 x i32> %and, zeroinitializer 226 ret <2 x i1> %cmp 227} 228 229define i1 @test18_ne(i32 %x) { 230; CHECK-LABEL: @test18_ne( 231; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %x, 3 232; CHECK-NEXT: ret i1 [[CMP]] 233; 234 %sh = lshr i32 8, %x 235 %and = and i32 %sh, 1 236 %cmp = icmp ne i32 %and, 0 237 ret i1 %cmp 238} 239 240define <2 x i1> @test18_ne_vec(<2 x i32> %x) { 241; CHECK-LABEL: @test18_ne_vec( 242; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %x, <i32 3, i32 3> 243; CHECK-NEXT: ret <2 x i1> [[CMP]] 244; 245 %sh = lshr <2 x i32> <i32 8, i32 8>, %x 246 %and = and <2 x i32> %sh, <i32 1, i32 1> 247 %cmp = icmp ne <2 x i32> %and, zeroinitializer 248 ret <2 x i1> %cmp 249} 250 251define i1 @test19(i32 %x) { 252; CHECK-LABEL: @test19( 253; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %x, 3 254; CHECK-NEXT: ret i1 [[CMP]] 255; 256 %shl = shl i32 1, %x 257 %and = and i32 %shl, 8 258 %cmp = icmp eq i32 %and, 8 259 ret i1 %cmp 260} 261 262define <2 x i1> @test19vec(<2 x i32> %x) { 263; CHECK-LABEL: @test19vec( 264; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %x, <i32 3, i32 3> 265; CHECK-NEXT: ret <2 x i1> [[CMP]] 266; 267 %shl = shl <2 x i32> <i32 1, i32 1>, %x 268 %and = and <2 x i32> %shl, <i32 8, i32 8> 269 %cmp = icmp eq <2 x i32> %and, <i32 8, i32 8> 270 ret <2 x i1> %cmp 271} 272 273define <2 x i1> @cmp_and_signbit_vec(<2 x i3> %x) { 274; CHECK-LABEL: @cmp_and_signbit_vec( 275; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i3> %x, zeroinitializer 276; CHECK-NEXT: ret <2 x i1> [[CMP]] 277; 278 %and = and <2 x i3> %x, <i3 4, i3 4> 279 %cmp = icmp ne <2 x i3> %and, zeroinitializer 280 ret <2 x i1> %cmp 281} 282 283define i1 @test20(i32 %x) { 284; CHECK-LABEL: @test20( 285; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %x, 3 286; CHECK-NEXT: ret i1 [[CMP]] 287; 288 %shl = shl i32 1, %x 289 %and = and i32 %shl, 8 290 %cmp = icmp ne i32 %and, 0 291 ret i1 %cmp 292} 293 294define <2 x i1> @test20vec(<2 x i32> %x) { 295; CHECK-LABEL: @test20vec( 296; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %x, <i32 3, i32 3> 297; CHECK-NEXT: ret <2 x i1> [[CMP]] 298; 299 %shl = shl <2 x i32> <i32 1, i32 1>, %x 300 %and = and <2 x i32> %shl, <i32 8, i32 8> 301 %cmp = icmp ne <2 x i32> %and, zeroinitializer 302 ret <2 x i1> %cmp 303} 304 305define i1 @test20a(i32 %x) { 306; CHECK-LABEL: @test20a( 307; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %x, 3 308; CHECK-NEXT: ret i1 [[CMP]] 309; 310 %shl = shl i32 1, %x 311 %and = and i32 %shl, 7 312 %cmp = icmp ne i32 %and, 0 313 ret i1 %cmp 314} 315 316define <2 x i1> @test20a_vec(<2 x i32> %x) { 317; CHECK-LABEL: @test20a_vec( 318; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %x, <i32 3, i32 3> 319; CHECK-NEXT: ret <2 x i1> [[CMP]] 320; 321 %shl = shl <2 x i32> <i32 1, i32 1>, %x 322 %and = and <2 x i32> %shl, <i32 7, i32 7> 323 %cmp = icmp ne <2 x i32> %and, zeroinitializer 324 ret <2 x i1> %cmp 325} 326 327define i1 @test21(i8 %x, i8 %y) { 328; CHECK-LABEL: @test21( 329; CHECK-NEXT: [[B:%.*]] = icmp ugt i8 %x, 3 330; CHECK-NEXT: ret i1 [[B]] 331; 332 %A = or i8 %x, 1 333 %B = icmp ugt i8 %A, 3 334 ret i1 %B 335} 336 337define i1 @test22(i8 %x, i8 %y) { 338; CHECK-LABEL: @test22( 339; CHECK-NEXT: [[B:%.*]] = icmp ult i8 %x, 4 340; CHECK-NEXT: ret i1 [[B]] 341; 342 %A = or i8 %x, 1 343 %B = icmp ult i8 %A, 4 344 ret i1 %B 345} 346 347; PR2740 348define i1 @test23(i32 %x) { 349; CHECK-LABEL: @test23( 350; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 %x, 1328634634 351; CHECK-NEXT: ret i1 [[I4]] 352; 353 %i3 = sdiv i32 %x, -1328634635 354 %i4 = icmp eq i32 %i3, -1 355 ret i1 %i4 356} 357 358define <2 x i1> @test23vec(<2 x i32> %x) { 359; CHECK-LABEL: @test23vec( 360; CHECK-NEXT: [[I4:%.*]] = icmp sgt <2 x i32> %x, <i32 1328634634, i32 1328634634> 361; CHECK-NEXT: ret <2 x i1> [[I4]] 362; 363 %i3 = sdiv <2 x i32> %x, <i32 -1328634635, i32 -1328634635> 364 %i4 = icmp eq <2 x i32> %i3, <i32 -1, i32 -1> 365 ret <2 x i1> %i4 366} 367 368@X = global [1000 x i32] zeroinitializer 369 370; PR8882 371define i1 @test24(i64 %i) { 372; CHECK-LABEL: @test24( 373; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 %i, 1000 374; CHECK-NEXT: ret i1 [[CMP]] 375; 376 %p1 = getelementptr inbounds i32, i32* getelementptr inbounds ([1000 x i32], [1000 x i32]* @X, i64 0, i64 0), i64 %i 377 %cmp = icmp eq i32* %p1, getelementptr inbounds ([1000 x i32], [1000 x i32]* @X, i64 1, i64 0) 378 ret i1 %cmp 379} 380 381@X_as1 = addrspace(1) global [1000 x i32] zeroinitializer 382 383define i1 @test24_as1(i64 %i) { 384; CHECK-LABEL: @test24_as1( 385; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 %i to i16 386; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 1000 387; CHECK-NEXT: ret i1 [[CMP]] 388; 389 %p1 = getelementptr inbounds i32, i32 addrspace(1)* getelementptr inbounds ([1000 x i32], [1000 x i32] addrspace(1)* @X_as1, i64 0, i64 0), i64 %i 390 %cmp = icmp eq i32 addrspace(1)* %p1, getelementptr inbounds ([1000 x i32], [1000 x i32] addrspace(1)* @X_as1, i64 1, i64 0) 391 ret i1 %cmp 392} 393 394define i1 @test25(i32 %x, i32 %y, i32 %z) { 395; CHECK-LABEL: @test25( 396; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 %x, %y 397; CHECK-NEXT: ret i1 [[C]] 398; 399 %lhs = add nsw i32 %x, %z 400 %rhs = add nsw i32 %y, %z 401 %c = icmp sgt i32 %lhs, %rhs 402 ret i1 %c 403} 404 405; X + Z > Y + Z -> X > Y if there is no overflow. 406define i1 @test26(i32 %x, i32 %y, i32 %z) { 407; CHECK-LABEL: @test26( 408; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %x, %y 409; CHECK-NEXT: ret i1 [[C]] 410; 411 %lhs = add nuw i32 %x, %z 412 %rhs = add nuw i32 %y, %z 413 %c = icmp ugt i32 %lhs, %rhs 414 ret i1 %c 415} 416 417; X - Z > Y - Z -> X > Y if there is no overflow. 418define i1 @test27(i32 %x, i32 %y, i32 %z) { 419; CHECK-LABEL: @test27( 420; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 %x, %y 421; CHECK-NEXT: ret i1 [[C]] 422; 423 %lhs = sub nsw i32 %x, %z 424 %rhs = sub nsw i32 %y, %z 425 %c = icmp sgt i32 %lhs, %rhs 426 ret i1 %c 427} 428 429; X - Z > Y - Z -> X > Y if there is no overflow. 430define i1 @test28(i32 %x, i32 %y, i32 %z) { 431; CHECK-LABEL: @test28( 432; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %x, %y 433; CHECK-NEXT: ret i1 [[C]] 434; 435 %lhs = sub nuw i32 %x, %z 436 %rhs = sub nuw i32 %y, %z 437 %c = icmp ugt i32 %lhs, %rhs 438 ret i1 %c 439} 440 441; X + Y > X -> Y > 0 if there is no overflow. 442define i1 @test29(i32 %x, i32 %y) { 443; CHECK-LABEL: @test29( 444; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 %y, 0 445; CHECK-NEXT: ret i1 [[C]] 446; 447 %lhs = add nsw i32 %x, %y 448 %c = icmp sgt i32 %lhs, %x 449 ret i1 %c 450} 451 452; X + Y > X -> Y > 0 if there is no overflow. 453define i1 @test30(i32 %x, i32 %y) { 454; CHECK-LABEL: @test30( 455; CHECK-NEXT: [[C:%.*]] = icmp ne i32 %y, 0 456; CHECK-NEXT: ret i1 [[C]] 457; 458 %lhs = add nuw i32 %x, %y 459 %c = icmp ugt i32 %lhs, %x 460 ret i1 %c 461} 462 463; X > X + Y -> 0 > Y if there is no overflow. 464define i1 @test31(i32 %x, i32 %y) { 465; CHECK-LABEL: @test31( 466; CHECK-NEXT: [[C:%.*]] = icmp slt i32 %y, 0 467; CHECK-NEXT: ret i1 [[C]] 468; 469 %rhs = add nsw i32 %x, %y 470 %c = icmp sgt i32 %x, %rhs 471 ret i1 %c 472} 473 474; X > X + Y -> 0 > Y if there is no overflow. 475define i1 @test32(i32 %x, i32 %y) { 476; CHECK-LABEL: @test32( 477; CHECK-NEXT: ret i1 false 478; 479 %rhs = add nuw i32 %x, %y 480 %c = icmp ugt i32 %x, %rhs 481 ret i1 %c 482} 483 484; X - Y > X -> 0 > Y if there is no overflow. 485define i1 @test33(i32 %x, i32 %y) { 486; CHECK-LABEL: @test33( 487; CHECK-NEXT: [[C:%.*]] = icmp slt i32 %y, 0 488; CHECK-NEXT: ret i1 [[C]] 489; 490 %lhs = sub nsw i32 %x, %y 491 %c = icmp sgt i32 %lhs, %x 492 ret i1 %c 493} 494 495; X - Y > X -> 0 > Y if there is no overflow. 496define i1 @test34(i32 %x, i32 %y) { 497; CHECK-LABEL: @test34( 498; CHECK-NEXT: ret i1 false 499; 500 %lhs = sub nuw i32 %x, %y 501 %c = icmp ugt i32 %lhs, %x 502 ret i1 %c 503} 504 505; X > X - Y -> Y > 0 if there is no overflow. 506define i1 @test35(i32 %x, i32 %y) { 507; CHECK-LABEL: @test35( 508; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 %y, 0 509; CHECK-NEXT: ret i1 [[C]] 510; 511 %rhs = sub nsw i32 %x, %y 512 %c = icmp sgt i32 %x, %rhs 513 ret i1 %c 514} 515 516; X > X - Y -> Y > 0 if there is no overflow. 517define i1 @test36(i32 %x, i32 %y) { 518; CHECK-LABEL: @test36( 519; CHECK-NEXT: [[C:%.*]] = icmp ne i32 %y, 0 520; CHECK-NEXT: ret i1 [[C]] 521; 522 %rhs = sub nuw i32 %x, %y 523 %c = icmp ugt i32 %x, %rhs 524 ret i1 %c 525} 526 527; X - Y > X - Z -> Z > Y if there is no overflow. 528define i1 @test37(i32 %x, i32 %y, i32 %z) { 529; CHECK-LABEL: @test37( 530; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 %z, %y 531; CHECK-NEXT: ret i1 [[C]] 532; 533 %lhs = sub nsw i32 %x, %y 534 %rhs = sub nsw i32 %x, %z 535 %c = icmp sgt i32 %lhs, %rhs 536 ret i1 %c 537} 538 539; X - Y > X - Z -> Z > Y if there is no overflow. 540define i1 @test38(i32 %x, i32 %y, i32 %z) { 541; CHECK-LABEL: @test38( 542; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %z, %y 543; CHECK-NEXT: ret i1 [[C]] 544; 545 %lhs = sub nuw i32 %x, %y 546 %rhs = sub nuw i32 %x, %z 547 %c = icmp ugt i32 %lhs, %rhs 548 ret i1 %c 549} 550 551; PR9343 #1 552define i1 @test39(i32 %X, i32 %Y) { 553; CHECK-LABEL: @test39( 554; CHECK-NEXT: [[B:%.*]] = icmp eq i32 %X, 0 555; CHECK-NEXT: ret i1 [[B]] 556; 557 %A = ashr exact i32 %X, %Y 558 %B = icmp eq i32 %A, 0 559 ret i1 %B 560} 561 562define <2 x i1> @test39vec(<2 x i32> %X, <2 x i32> %Y) { 563; CHECK-LABEL: @test39vec( 564; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i32> %X, zeroinitializer 565; CHECK-NEXT: ret <2 x i1> [[B]] 566; 567 %A = ashr exact <2 x i32> %X, %Y 568 %B = icmp eq <2 x i32> %A, zeroinitializer 569 ret <2 x i1> %B 570} 571 572define i1 @test40(i32 %X, i32 %Y) { 573; CHECK-LABEL: @test40( 574; CHECK-NEXT: [[B:%.*]] = icmp ne i32 %X, 0 575; CHECK-NEXT: ret i1 [[B]] 576; 577 %A = lshr exact i32 %X, %Y 578 %B = icmp ne i32 %A, 0 579 ret i1 %B 580} 581 582define <2 x i1> @test40vec(<2 x i32> %X, <2 x i32> %Y) { 583; CHECK-LABEL: @test40vec( 584; CHECK-NEXT: [[B:%.*]] = icmp ne <2 x i32> %X, zeroinitializer 585; CHECK-NEXT: ret <2 x i1> [[B]] 586; 587 %A = lshr exact <2 x i32> %X, %Y 588 %B = icmp ne <2 x i32> %A, zeroinitializer 589 ret <2 x i1> %B 590} 591 592define i1 @shr_exact(i132 %x) { 593; CHECK-LABEL: @shr_exact( 594; CHECK-NEXT: [[CMP:%.*]] = icmp eq i132 %x, 32 595; CHECK-NEXT: ret i1 [[CMP]] 596; 597 %sh = ashr exact i132 %x, 4 598 %cmp = icmp eq i132 %sh, 2 599 ret i1 %cmp 600} 601 602define <2 x i1> @shr_exact_vec(<2 x i132> %x) { 603; CHECK-LABEL: @shr_exact_vec( 604; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i132> %x, <i132 32, i132 32> 605; CHECK-NEXT: ret <2 x i1> [[CMP]] 606; 607 %sh = lshr exact <2 x i132> %x, <i132 4, i132 4> 608 %cmp = icmp ne <2 x i132> %sh, <i132 2, i132 2> 609 ret <2 x i1> %cmp 610} 611 612; PR9343 #3 613define i1 @test41(i32 %X, i32 %Y) { 614; CHECK-LABEL: @test41( 615; CHECK-NEXT: ret i1 true 616; 617 %A = urem i32 %X, %Y 618 %B = icmp ugt i32 %Y, %A 619 ret i1 %B 620} 621 622define i1 @test42(i32 %X, i32 %Y) { 623; CHECK-LABEL: @test42( 624; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 %Y, -1 625; CHECK-NEXT: ret i1 [[B]] 626; 627 %A = srem i32 %X, %Y 628 %B = icmp slt i32 %A, %Y 629 ret i1 %B 630} 631 632define i1 @test43(i32 %X, i32 %Y) { 633; CHECK-LABEL: @test43( 634; CHECK-NEXT: [[B:%.*]] = icmp slt i32 %Y, 0 635; CHECK-NEXT: ret i1 [[B]] 636; 637 %A = srem i32 %X, %Y 638 %B = icmp slt i32 %Y, %A 639 ret i1 %B 640} 641 642define i1 @test44(i32 %X, i32 %Y) { 643; CHECK-LABEL: @test44( 644; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 %Y, -1 645; CHECK-NEXT: ret i1 [[B]] 646; 647 %A = srem i32 %X, %Y 648 %B = icmp slt i32 %A, %Y 649 ret i1 %B 650} 651 652define i1 @test45(i32 %X, i32 %Y) { 653; CHECK-LABEL: @test45( 654; CHECK-NEXT: [[B:%.*]] = icmp slt i32 %Y, 0 655; CHECK-NEXT: ret i1 [[B]] 656; 657 %A = srem i32 %X, %Y 658 %B = icmp slt i32 %Y, %A 659 ret i1 %B 660} 661 662; PR9343 #4 663define i1 @test46(i32 %X, i32 %Y, i32 %Z) { 664; CHECK-LABEL: @test46( 665; CHECK-NEXT: [[C:%.*]] = icmp ult i32 %X, %Y 666; CHECK-NEXT: ret i1 [[C]] 667; 668 %A = ashr exact i32 %X, %Z 669 %B = ashr exact i32 %Y, %Z 670 %C = icmp ult i32 %A, %B 671 ret i1 %C 672} 673 674; PR9343 #5 675define i1 @test47(i32 %X, i32 %Y, i32 %Z) { 676; CHECK-LABEL: @test47( 677; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %X, %Y 678; CHECK-NEXT: ret i1 [[C]] 679; 680 %A = ashr exact i32 %X, %Z 681 %B = ashr exact i32 %Y, %Z 682 %C = icmp ugt i32 %A, %B 683 ret i1 %C 684} 685 686; PR9343 #8 687define i1 @test48(i32 %X, i32 %Y, i32 %Z) { 688; CHECK-LABEL: @test48( 689; CHECK-NEXT: [[C:%.*]] = icmp eq i32 %X, %Y 690; CHECK-NEXT: ret i1 [[C]] 691; 692 %A = sdiv exact i32 %X, %Z 693 %B = sdiv exact i32 %Y, %Z 694 %C = icmp eq i32 %A, %B 695 ret i1 %C 696} 697 698; PR8469 699define <2 x i1> @test49(<2 x i32> %tmp3) { 700; CHECK-LABEL: @test49( 701; CHECK-NEXT: entry: 702; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true> 703; 704entry: 705 %tmp11 = and <2 x i32> %tmp3, <i32 3, i32 3> 706 %cmp = icmp ult <2 x i32> %tmp11, <i32 4, i32 4> 707 ret <2 x i1> %cmp 708} 709 710; PR9343 #7 711define i1 @test50(i16 %X, i32 %Y) { 712; CHECK-LABEL: @test50( 713; CHECK-NEXT: ret i1 true 714; 715 %A = zext i16 %X to i32 716 %B = srem i32 %A, %Y 717 %C = icmp sgt i32 %B, -1 718 ret i1 %C 719} 720 721define i1 @test51(i32 %X, i32 %Y) { 722; CHECK-LABEL: @test51( 723; CHECK-NEXT: [[A:%.*]] = and i32 %X, -2147483648 724; CHECK-NEXT: [[B:%.*]] = srem i32 [[A]], %Y 725; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[B]], -1 726; CHECK-NEXT: ret i1 [[C]] 727; 728 %A = and i32 %X, 2147483648 729 %B = srem i32 %A, %Y 730 %C = icmp sgt i32 %B, -1 731 ret i1 %C 732} 733 734define i1 @test52(i32 %x1) { 735; CHECK-LABEL: @test52( 736; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x1, 16711935 737; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 4980863 738; CHECK-NEXT: ret i1 [[TMP2]] 739; 740 %conv = and i32 %x1, 255 741 %cmp = icmp eq i32 %conv, 127 742 %tmp2 = lshr i32 %x1, 16 743 %tmp3 = trunc i32 %tmp2 to i8 744 %cmp15 = icmp eq i8 %tmp3, 76 745 746 %A = and i1 %cmp, %cmp15 747 ret i1 %A 748} 749 750; PR9838 751define i1 @test53(i32 %a, i32 %b) { 752; CHECK-LABEL: @test53( 753; CHECK-NEXT: [[X:%.*]] = sdiv exact i32 %a, 30 754; CHECK-NEXT: [[Y:%.*]] = sdiv i32 %b, 30 755; CHECK-NEXT: [[Z:%.*]] = icmp eq i32 [[X]], [[Y]] 756; CHECK-NEXT: ret i1 [[Z]] 757; 758 %x = sdiv exact i32 %a, 30 759 %y = sdiv i32 %b, 30 760 %z = icmp eq i32 %x, %y 761 ret i1 %z 762} 763 764define i1 @test54(i8 %a) { 765; CHECK-LABEL: @test54( 766; CHECK-NEXT: [[AND:%.*]] = and i8 %a, -64 767; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[AND]], -128 768; CHECK-NEXT: ret i1 [[RET]] 769; 770 %ext = zext i8 %a to i32 771 %and = and i32 %ext, 192 772 %ret = icmp eq i32 %and, 128 773 ret i1 %ret 774} 775 776define i1 @test55(i32 %a) { 777; CHECK-LABEL: @test55( 778; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, -123 779; CHECK-NEXT: ret i1 [[CMP]] 780; 781 %sub = sub i32 0, %a 782 %cmp = icmp eq i32 %sub, 123 783 ret i1 %cmp 784} 785 786define <2 x i1> @test55vec(<2 x i32> %a) { 787; CHECK-LABEL: @test55vec( 788; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %a, <i32 -123, i32 -123> 789; CHECK-NEXT: ret <2 x i1> [[CMP]] 790; 791 %sub = sub <2 x i32> zeroinitializer, %a 792 %cmp = icmp eq <2 x i32> %sub, <i32 123, i32 123> 793 ret <2 x i1> %cmp 794} 795 796define i1 @test56(i32 %a) { 797; CHECK-LABEL: @test56( 798; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, -113 799; CHECK-NEXT: ret i1 [[CMP]] 800; 801 %sub = sub i32 10, %a 802 %cmp = icmp eq i32 %sub, 123 803 ret i1 %cmp 804} 805 806define <2 x i1> @test56vec(<2 x i32> %a) { 807; CHECK-LABEL: @test56vec( 808; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %a, <i32 -113, i32 -113> 809; CHECK-NEXT: ret <2 x i1> [[CMP]] 810; 811 %sub = sub <2 x i32> <i32 10, i32 10>, %a 812 %cmp = icmp eq <2 x i32> %sub, <i32 123, i32 123> 813 ret <2 x i1> %cmp 814} 815 816; PR10267 Don't make icmps more expensive when no other inst is subsumed. 817declare void @foo(i32) 818define i1 @test57(i32 %a) { 819; CHECK-LABEL: @test57( 820; CHECK-NEXT: [[AND:%.*]] = and i32 %a, -2 821; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 822; CHECK-NEXT: call void @foo(i32 [[AND]]) 823; CHECK-NEXT: ret i1 [[CMP]] 824; 825 %and = and i32 %a, -2 826 %cmp = icmp ne i32 %and, 0 827 call void @foo(i32 %and) 828 ret i1 %cmp 829} 830 831; rdar://problem/10482509 832define zeroext i1 @cmpabs1(i64 %val) { 833; CHECK-LABEL: @cmpabs1( 834; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 %val, 0 835; CHECK-NEXT: ret i1 [[TOBOOL]] 836; 837 %sub = sub nsw i64 0, %val 838 %cmp = icmp slt i64 %val, 0 839 %sub.val = select i1 %cmp, i64 %sub, i64 %val 840 %tobool = icmp ne i64 %sub.val, 0 841 ret i1 %tobool 842} 843 844define zeroext i1 @cmpabs2(i64 %val) { 845; CHECK-LABEL: @cmpabs2( 846; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 %val, 0 847; CHECK-NEXT: ret i1 [[TOBOOL]] 848; 849 %sub = sub nsw i64 0, %val 850 %cmp = icmp slt i64 %val, 0 851 %sub.val = select i1 %cmp, i64 %val, i64 %sub 852 %tobool = icmp ne i64 %sub.val, 0 853 ret i1 %tobool 854} 855 856define void @test58() { 857; CHECK-LABEL: @test58( 858; CHECK-NEXT: [[CALL:%.*]] = call i32 @test58_d(i64 36029346783166592) 859; CHECK-NEXT: ret void 860; 861 %cast = bitcast <1 x i64> <i64 36029346783166592> to i64 862 %call = call i32 @test58_d( i64 %cast) 863 ret void 864} 865declare i32 @test58_d(i64) 866 867define i1 @test59(i8* %foo) { 868; CHECK-LABEL: @test59( 869; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, i8* %foo, i64 8 870; CHECK-NEXT: [[USE:%.*]] = ptrtoint i8* [[GEP1]] to i64 871; CHECK-NEXT: [[CALL:%.*]] = call i32 @test58_d(i64 [[USE]]) 872; CHECK-NEXT: ret i1 true 873; 874 %bit = bitcast i8* %foo to i32* 875 %gep1 = getelementptr inbounds i32, i32* %bit, i64 2 876 %gep2 = getelementptr inbounds i8, i8* %foo, i64 10 877 %cast1 = bitcast i32* %gep1 to i8* 878 %cmp = icmp ult i8* %cast1, %gep2 879 %use = ptrtoint i8* %cast1 to i64 880 %call = call i32 @test58_d(i64 %use) 881 ret i1 %cmp 882} 883 884define i1 @test59_as1(i8 addrspace(1)* %foo) { 885; CHECK-LABEL: @test59_as1( 886; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* %foo, i16 8 887; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[GEP1]] to i16 888; CHECK-NEXT: [[USE:%.*]] = zext i16 [[TMP1]] to i64 889; CHECK-NEXT: [[CALL:%.*]] = call i32 @test58_d(i64 [[USE]]) 890; CHECK-NEXT: ret i1 true 891; 892 %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)* 893 %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i64 2 894 %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i64 10 895 %cast1 = bitcast i32 addrspace(1)* %gep1 to i8 addrspace(1)* 896 %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2 897 %use = ptrtoint i8 addrspace(1)* %cast1 to i64 898 %call = call i32 @test58_d(i64 %use) 899 ret i1 %cmp 900} 901 902define i1 @test60(i8* %foo, i64 %i, i64 %j) { 903; CHECK-LABEL: @test60( 904; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nuw i64 %i, 2 905; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[GEP1_IDX]], %j 906; CHECK-NEXT: ret i1 [[TMP1]] 907; 908 %bit = bitcast i8* %foo to i32* 909 %gep1 = getelementptr inbounds i32, i32* %bit, i64 %i 910 %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j 911 %cast1 = bitcast i32* %gep1 to i8* 912 %cmp = icmp ult i8* %cast1, %gep2 913 ret i1 %cmp 914} 915 916define i1 @test60_as1(i8 addrspace(1)* %foo, i64 %i, i64 %j) { 917; CHECK-LABEL: @test60_as1( 918; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 %i to i16 919; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 %j to i16 920; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nuw i16 [[TMP1]], 2 921; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i16 [[TMP2]], [[GEP1_IDX]] 922; CHECK-NEXT: ret i1 [[TMP3]] 923; 924 %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)* 925 %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i64 %i 926 %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i64 %j 927 %cast1 = bitcast i32 addrspace(1)* %gep1 to i8 addrspace(1)* 928 %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2 929 ret i1 %cmp 930} 931 932; Same as test60, but look through an addrspacecast instead of a 933; bitcast. This uses the same sized addrspace. 934define i1 @test60_addrspacecast(i8* %foo, i64 %i, i64 %j) { 935; CHECK-LABEL: @test60_addrspacecast( 936; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nuw i64 %i, 2 937; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[GEP1_IDX]], %j 938; CHECK-NEXT: ret i1 [[TMP1]] 939; 940 %bit = addrspacecast i8* %foo to i32 addrspace(3)* 941 %gep1 = getelementptr inbounds i32, i32 addrspace(3)* %bit, i64 %i 942 %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j 943 %cast1 = addrspacecast i32 addrspace(3)* %gep1 to i8* 944 %cmp = icmp ult i8* %cast1, %gep2 945 ret i1 %cmp 946} 947 948define i1 @test60_addrspacecast_smaller(i8* %foo, i16 %i, i64 %j) { 949; CHECK-LABEL: @test60_addrspacecast_smaller( 950; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nuw i16 %i, 2 951; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 %j to i16 952; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i16 [[TMP1]], [[GEP1_IDX]] 953; CHECK-NEXT: ret i1 [[TMP2]] 954; 955 %bit = addrspacecast i8* %foo to i32 addrspace(1)* 956 %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %bit, i16 %i 957 %gep2 = getelementptr inbounds i8, i8* %foo, i64 %j 958 %cast1 = addrspacecast i32 addrspace(1)* %gep1 to i8* 959 %cmp = icmp ult i8* %cast1, %gep2 960 ret i1 %cmp 961} 962 963define i1 @test60_addrspacecast_larger(i8 addrspace(1)* %foo, i32 %i, i16 %j) { 964; CHECK-LABEL: @test60_addrspacecast_larger( 965; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %i to i16 966; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[TMP1]], 2 967; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i16 [[SHL]], %j 968; CHECK-NEXT: ret i1 [[TMP2]] 969; 970 %bit = addrspacecast i8 addrspace(1)* %foo to i32 addrspace(2)* 971 %gep1 = getelementptr inbounds i32, i32 addrspace(2)* %bit, i32 %i 972 %gep2 = getelementptr inbounds i8, i8 addrspace(1)* %foo, i16 %j 973 %cast1 = addrspacecast i32 addrspace(2)* %gep1 to i8 addrspace(1)* 974 %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2 975 ret i1 %cmp 976} 977 978define i1 @test61(i8* %foo, i64 %i, i64 %j) { 979; CHECK-LABEL: @test61( 980; CHECK-NEXT: [[BIT:%.*]] = bitcast i8* %foo to i32* 981; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i32, i32* [[BIT]], i64 %i 982; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, i8* %foo, i64 %j 983; CHECK-NEXT: [[CAST1:%.*]] = bitcast i32* [[GEP1]] to i8* 984; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8* [[CAST1]], [[GEP2]] 985; CHECK-NEXT: ret i1 [[CMP]] 986; 987 %bit = bitcast i8* %foo to i32* 988 %gep1 = getelementptr i32, i32* %bit, i64 %i 989 %gep2 = getelementptr i8, i8* %foo, i64 %j 990 %cast1 = bitcast i32* %gep1 to i8* 991 %cmp = icmp ult i8* %cast1, %gep2 992 ret i1 %cmp 993; Don't transform non-inbounds GEPs. 994} 995 996define i1 @test61_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) { 997; CHECK-LABEL: @test61_as1( 998; CHECK-NEXT: [[BIT:%.*]] = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)* 999; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i32, i32 addrspace(1)* [[BIT]], i16 %i 1000; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, i8 addrspace(1)* %foo, i16 %j 1001; CHECK-NEXT: [[CAST1:%.*]] = bitcast i32 addrspace(1)* [[GEP1]] to i8 addrspace(1)* 1002; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 addrspace(1)* [[CAST1]], [[GEP2]] 1003; CHECK-NEXT: ret i1 [[CMP]] 1004; 1005 %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)* 1006 %gep1 = getelementptr i32, i32 addrspace(1)* %bit, i16 %i 1007 %gep2 = getelementptr i8, i8 addrspace(1)* %foo, i16 %j 1008 %cast1 = bitcast i32 addrspace(1)* %gep1 to i8 addrspace(1)* 1009 %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2 1010 ret i1 %cmp 1011; Don't transform non-inbounds GEPs. 1012} 1013 1014define i1 @test62(i8* %a) { 1015; CHECK-LABEL: @test62( 1016; CHECK-NEXT: ret i1 true 1017; 1018 %arrayidx1 = getelementptr inbounds i8, i8* %a, i64 1 1019 %arrayidx2 = getelementptr inbounds i8, i8* %a, i64 10 1020 %cmp = icmp slt i8* %arrayidx1, %arrayidx2 1021 ret i1 %cmp 1022} 1023 1024define i1 @test62_as1(i8 addrspace(1)* %a) { 1025; CHECK-LABEL: @test62_as1( 1026; CHECK-NEXT: ret i1 true 1027; 1028 %arrayidx1 = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 1 1029 %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 10 1030 %cmp = icmp slt i8 addrspace(1)* %arrayidx1, %arrayidx2 1031 ret i1 %cmp 1032} 1033 1034define i1 @test63(i8 %a, i32 %b) { 1035; CHECK-LABEL: @test63( 1036; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %b to i8 1037; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[TMP1]], %a 1038; CHECK-NEXT: ret i1 [[C]] 1039; 1040 %z = zext i8 %a to i32 1041 %t = and i32 %b, 255 1042 %c = icmp eq i32 %z, %t 1043 ret i1 %c 1044} 1045 1046define i1 @test64(i8 %a, i32 %b) { 1047; CHECK-LABEL: @test64( 1048; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %b to i8 1049; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[TMP1]], %a 1050; CHECK-NEXT: ret i1 [[C]] 1051; 1052 %t = and i32 %b, 255 1053 %z = zext i8 %a to i32 1054 %c = icmp eq i32 %t, %z 1055 ret i1 %c 1056} 1057 1058define i1 @test65(i64 %A, i64 %B) { 1059; CHECK-LABEL: @test65( 1060; CHECK-NEXT: ret i1 true 1061; 1062 %s1 = add i64 %A, %B 1063 %s2 = add i64 %A, %B 1064 %cmp = icmp eq i64 %s1, %s2 1065 ret i1 %cmp 1066} 1067 1068define i1 @test66(i64 %A, i64 %B) { 1069; CHECK-LABEL: @test66( 1070; CHECK-NEXT: ret i1 true 1071; 1072 %s1 = add i64 %A, %B 1073 %s2 = add i64 %B, %A 1074 %cmp = icmp eq i64 %s1, %s2 1075 ret i1 %cmp 1076} 1077 1078define i1 @test67(i32 %x) { 1079; CHECK-LABEL: @test67( 1080; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 96 1081; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 1082; CHECK-NEXT: ret i1 [[CMP]] 1083; 1084 %and = and i32 %x, 127 1085 %cmp = icmp sgt i32 %and, 31 1086 ret i1 %cmp 1087} 1088 1089; The test above relies on 3 different folds. 1090; This test only checks the last of those (icmp ugt -> icmp ne). 1091 1092define <2 x i1> @test67vec(<2 x i32> %x) { 1093; CHECK-LABEL: @test67vec( 1094; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %x, <i32 96, i32 96> 1095; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer 1096; CHECK-NEXT: ret <2 x i1> [[CMP]] 1097; 1098 %and = and <2 x i32> %x, <i32 96, i32 96> 1099 %cmp = icmp ugt <2 x i32> %and, <i32 31, i32 31> 1100 ret <2 x i1> %cmp 1101} 1102 1103; FIXME: Vector constant for the 'and' should use less bits. 1104define <2 x i1> @test67vec2(<2 x i32> %x) { 1105; CHECK-LABEL: @test67vec2( 1106; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %x, <i32 127, i32 127> 1107; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[AND]], <i32 31, i32 31> 1108; CHECK-NEXT: ret <2 x i1> [[CMP]] 1109; 1110 %and = and <2 x i32> %x, <i32 127, i32 127> 1111 %cmp = icmp ugt <2 x i32> %and, <i32 31, i32 31> 1112 ret <2 x i1> %cmp 1113} 1114 1115define i1 @test68(i32 %x) { 1116; CHECK-LABEL: @test68( 1117; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 127 1118; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[AND]], 30 1119; CHECK-NEXT: ret i1 [[CMP]] 1120; 1121 %and = and i32 %x, 127 1122 %cmp = icmp sgt i32 %and, 30 1123 ret i1 %cmp 1124} 1125 1126; PR14708 1127define i1 @test69(i32 %c) { 1128; CHECK-LABEL: @test69( 1129; CHECK-NEXT: [[TMP1:%.*]] = or i32 %c, 32 1130; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 97 1131; CHECK-NEXT: ret i1 [[TMP2]] 1132; 1133 %1 = icmp eq i32 %c, 97 1134 %2 = icmp eq i32 %c, 65 1135 %3 = or i1 %1, %2 1136 ret i1 %3 1137} 1138 1139; PR15940 1140define i1 @test70(i32 %X) { 1141; CHECK-LABEL: @test70( 1142; CHECK-NEXT: [[A:%.*]] = srem i32 5, %X 1143; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A]], 2 1144; CHECK-NEXT: ret i1 [[C]] 1145; 1146 %A = srem i32 5, %X 1147 %B = add i32 %A, 2 1148 %C = icmp ne i32 %B, 4 1149 ret i1 %C 1150} 1151 1152define <2 x i1> @test70vec(<2 x i32> %X) { 1153; CHECK-LABEL: @test70vec( 1154; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i32> %X, <i32 2, i32 2> 1155; CHECK-NEXT: ret <2 x i1> [[C]] 1156; 1157 %B = add <2 x i32> %X, <i32 2, i32 2> 1158 %C = icmp ne <2 x i32> %B, <i32 4, i32 4> 1159 ret <2 x i1> %C 1160} 1161 1162define i1 @icmp_sext16trunc(i32 %x) { 1163; CHECK-LABEL: @icmp_sext16trunc( 1164; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %x to i16 1165; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[TMP1]], 36 1166; CHECK-NEXT: ret i1 [[CMP]] 1167; 1168 %trunc = trunc i32 %x to i16 1169 %sext = sext i16 %trunc to i32 1170 %cmp = icmp slt i32 %sext, 36 1171 ret i1 %cmp 1172} 1173 1174define i1 @icmp_sext8trunc(i32 %x) { 1175; CHECK-LABEL: @icmp_sext8trunc( 1176; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %x to i8 1177; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 36 1178; CHECK-NEXT: ret i1 [[CMP]] 1179; 1180 %trunc = trunc i32 %x to i8 1181 %sext = sext i8 %trunc to i32 1182 %cmp = icmp slt i32 %sext, 36 1183 ret i1 %cmp 1184} 1185 1186; FIXME: Vectors should fold the same way. 1187define <2 x i1> @icmp_sext8trunc_vec(<2 x i32> %x) { 1188; CHECK-LABEL: @icmp_sext8trunc_vec( 1189; CHECK-NEXT: [[SEXT1:%.*]] = shl <2 x i32> %x, <i32 24, i32 24> 1190; CHECK-NEXT: [[SEXT:%.*]] = ashr <2 x i32> [[SEXT:%.*]]1, <i32 24, i32 24> 1191; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[SEXT]], <i32 36, i32 36> 1192; CHECK-NEXT: ret <2 x i1> [[CMP]] 1193; 1194 %trunc = trunc <2 x i32> %x to <2 x i8> 1195 %sext = sext <2 x i8> %trunc to <2 x i32> 1196 %cmp = icmp slt <2 x i32> %sext, <i32 36, i32 36> 1197 ret <2 x i1> %cmp 1198} 1199 1200define i1 @icmp_shl16(i32 %x) { 1201; CHECK-LABEL: @icmp_shl16( 1202; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %x to i16 1203; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[TMP1]], 36 1204; CHECK-NEXT: ret i1 [[CMP]] 1205; 1206 %shl = shl i32 %x, 16 1207 %cmp = icmp slt i32 %shl, 2359296 1208 ret i1 %cmp 1209} 1210 1211; D25952: Don't create illegal types like i15 in InstCombine 1212 1213define i1 @icmp_shl17(i32 %x) { 1214; CHECK-LABEL: @icmp_shl17( 1215; CHECK-NEXT: [[SHL:%.*]] = shl i32 %x, 17 1216; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 2359296 1217; CHECK-NEXT: ret i1 [[CMP]] 1218; 1219 %shl = shl i32 %x, 17 1220 %cmp = icmp slt i32 %shl, 2359296 1221 ret i1 %cmp 1222} 1223 1224define <2 x i1> @icmp_shl16_vec(<2 x i32> %x) { 1225; CHECK-LABEL: @icmp_shl16_vec( 1226; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> %x to <2 x i16> 1227; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i16> [[TMP1]], <i16 36, i16 36> 1228; CHECK-NEXT: ret <2 x i1> [[CMP]] 1229; 1230 %shl = shl <2 x i32> %x, <i32 16, i32 16> 1231 %cmp = icmp slt <2 x i32> %shl, <i32 2359296, i32 2359296> 1232 ret <2 x i1> %cmp 1233} 1234 1235define i1 @icmp_shl24(i32 %x) { 1236; CHECK-LABEL: @icmp_shl24( 1237; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %x to i8 1238; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 36 1239; CHECK-NEXT: ret i1 [[CMP]] 1240; 1241 %shl = shl i32 %x, 24 1242 %cmp = icmp slt i32 %shl, 603979776 1243 ret i1 %cmp 1244} 1245 1246define i1 @icmp_shl_eq(i32 %x) { 1247; CHECK-LABEL: @icmp_shl_eq( 1248; CHECK-NEXT: [[MUL_MASK:%.*]] = and i32 %x, 134217727 1249; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[MUL_MASK]], 0 1250; CHECK-NEXT: ret i1 [[CMP]] 1251; 1252 %mul = shl i32 %x, 5 1253 %cmp = icmp eq i32 %mul, 0 1254 ret i1 %cmp 1255} 1256 1257define <2 x i1> @icmp_shl_eq_vec(<2 x i32> %x) { 1258; CHECK-LABEL: @icmp_shl_eq_vec( 1259; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> %x, <i32 134217727, i32 134217727> 1260; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[MUL_MASK]], zeroinitializer 1261; CHECK-NEXT: ret <2 x i1> [[CMP]] 1262; 1263 %mul = shl <2 x i32> %x, <i32 5, i32 5> 1264 %cmp = icmp eq <2 x i32> %mul, zeroinitializer 1265 ret <2 x i1> %cmp 1266} 1267 1268define i1 @icmp_shl_nsw_ne(i32 %x) { 1269; CHECK-LABEL: @icmp_shl_nsw_ne( 1270; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 %x, 0 1271; CHECK-NEXT: ret i1 [[CMP]] 1272; 1273 %mul = shl nsw i32 %x, 7 1274 %cmp = icmp ne i32 %mul, 0 1275 ret i1 %cmp 1276} 1277 1278define <2 x i1> @icmp_shl_nsw_ne_vec(<2 x i32> %x) { 1279; CHECK-LABEL: @icmp_shl_nsw_ne_vec( 1280; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, zeroinitializer 1281; CHECK-NEXT: ret <2 x i1> [[CMP]] 1282; 1283 %mul = shl nsw <2 x i32> %x, <i32 7, i32 7> 1284 %cmp = icmp ne <2 x i32> %mul, zeroinitializer 1285 ret <2 x i1> %cmp 1286} 1287 1288define i1 @icmp_shl_ne(i32 %x) { 1289; CHECK-LABEL: @icmp_shl_ne( 1290; CHECK-NEXT: [[MUL_MASK:%.*]] = and i32 %x, 33554431 1291; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[MUL_MASK]], 0 1292; CHECK-NEXT: ret i1 [[CMP]] 1293; 1294 %mul = shl i32 %x, 7 1295 %cmp = icmp ne i32 %mul, 0 1296 ret i1 %cmp 1297} 1298 1299define <2 x i1> @icmp_shl_ne_vec(<2 x i32> %x) { 1300; CHECK-LABEL: @icmp_shl_ne_vec( 1301; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> %x, <i32 33554431, i32 33554431> 1302; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[MUL_MASK]], zeroinitializer 1303; CHECK-NEXT: ret <2 x i1> [[CMP]] 1304; 1305 %mul = shl <2 x i32> %x, <i32 7, i32 7> 1306 %cmp = icmp ne <2 x i32> %mul, zeroinitializer 1307 ret <2 x i1> %cmp 1308} 1309 1310define <2 x i1> @icmp_shl_nuw_ne_vec(<2 x i32> %x) { 1311; CHECK-LABEL: @icmp_shl_nuw_ne_vec( 1312; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, <i32 2, i32 2> 1313; CHECK-NEXT: ret <2 x i1> [[CMP]] 1314; 1315 %shl = shl nuw <2 x i32> %x, <i32 7, i32 7> 1316 %cmp = icmp ne <2 x i32> %shl, <i32 256, i32 256> 1317 ret <2 x i1> %cmp 1318} 1319 1320; If the (mul x, C) preserved the sign and this is sign test, 1321; compare the LHS operand instead 1322define i1 @icmp_mul_nsw(i32 %x) { 1323; CHECK-LABEL: @icmp_mul_nsw( 1324; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 %x, 0 1325; CHECK-NEXT: ret i1 [[CMP]] 1326; 1327 %mul = mul nsw i32 %x, 12 1328 %cmp = icmp sgt i32 %mul, 0 1329 ret i1 %cmp 1330} 1331 1332define i1 @icmp_mul_nsw1(i32 %x) { 1333; CHECK-LABEL: @icmp_mul_nsw1( 1334; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %x, 0 1335; CHECK-NEXT: ret i1 [[CMP]] 1336; 1337 %mul = mul nsw i32 %x, 12 1338 %cmp = icmp sle i32 %mul, -1 1339 ret i1 %cmp 1340} 1341 1342define i1 @icmp_mul_nsw_neg(i32 %x) { 1343; CHECK-LABEL: @icmp_mul_nsw_neg( 1344; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %x, 1 1345; CHECK-NEXT: ret i1 [[CMP]] 1346; 1347 %mul = mul nsw i32 %x, -12 1348 %cmp = icmp sge i32 %mul, 0 1349 ret i1 %cmp 1350} 1351 1352define i1 @icmp_mul_nsw_neg1(i32 %x) { 1353; CHECK-LABEL: @icmp_mul_nsw_neg1( 1354; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %x, 0 1355; CHECK-NEXT: ret i1 [[CMP]] 1356; 1357 %mul = mul nsw i32 %x, -12 1358 %cmp = icmp sge i32 %mul, 1 1359 ret i1 %cmp 1360} 1361 1362define <2 x i1> @icmp_mul_nsw_neg1_vec(<2 x i32> %x) { 1363; CHECK-LABEL: @icmp_mul_nsw_neg1_vec( 1364; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %x, zeroinitializer 1365; CHECK-NEXT: ret <2 x i1> [[CMP]] 1366; 1367 %mul = mul nsw <2 x i32> %x, <i32 -12, i32 -12> 1368 %cmp = icmp sge <2 x i32> %mul, <i32 1, i32 1> 1369 ret <2 x i1> %cmp 1370} 1371 1372define i1 @icmp_mul_nsw_0(i32 %x) { 1373; CHECK-LABEL: @icmp_mul_nsw_0( 1374; CHECK-NEXT: ret i1 false 1375; 1376 %mul = mul nsw i32 %x, 0 1377 %cmp = icmp sgt i32 %mul, 0 1378 ret i1 %cmp 1379} 1380 1381define i1 @icmp_mul(i32 %x) { 1382; CHECK-LABEL: @icmp_mul( 1383; CHECK-NEXT: [[MUL:%.*]] = mul i32 %x, -12 1384; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[MUL]], -1 1385; CHECK-NEXT: ret i1 [[CMP]] 1386; 1387 %mul = mul i32 %x, -12 1388 %cmp = icmp sge i32 %mul, 0 1389 ret i1 %cmp 1390} 1391 1392; Checks for icmp (eq|ne) (mul x, C), 0 1393define i1 @icmp_mul_neq0(i32 %x) { 1394; CHECK-LABEL: @icmp_mul_neq0( 1395; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 %x, 0 1396; CHECK-NEXT: ret i1 [[CMP]] 1397; 1398 %mul = mul nsw i32 %x, -12 1399 %cmp = icmp ne i32 %mul, 0 1400 ret i1 %cmp 1401} 1402 1403define <2 x i1> @icmp_mul_neq0_vec(<2 x i32> %x) { 1404; CHECK-LABEL: @icmp_mul_neq0_vec( 1405; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %x, zeroinitializer 1406; CHECK-NEXT: ret <2 x i1> [[CMP]] 1407; 1408 %mul = mul nsw <2 x i32> %x, <i32 -12, i32 -12> 1409 %cmp = icmp ne <2 x i32> %mul, zeroinitializer 1410 ret <2 x i1> %cmp 1411} 1412 1413define i1 @icmp_mul_eq0(i32 %x) { 1414; CHECK-LABEL: @icmp_mul_eq0( 1415; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %x, 0 1416; CHECK-NEXT: ret i1 [[CMP]] 1417; 1418 %mul = mul nsw i32 %x, 12 1419 %cmp = icmp eq i32 %mul, 0 1420 ret i1 %cmp 1421} 1422 1423define i1 @icmp_mul0_eq0(i32 %x) { 1424; CHECK-LABEL: @icmp_mul0_eq0( 1425; CHECK-NEXT: ret i1 true 1426; 1427 %mul = mul i32 %x, 0 1428 %cmp = icmp eq i32 %mul, 0 1429 ret i1 %cmp 1430} 1431 1432define i1 @icmp_mul0_ne0(i32 %x) { 1433; CHECK-LABEL: @icmp_mul0_ne0( 1434; CHECK-NEXT: ret i1 false 1435; 1436 %mul = mul i32 %x, 0 1437 %cmp = icmp ne i32 %mul, 0 1438 ret i1 %cmp 1439} 1440 1441define i1 @icmp_sub1_sge(i32 %x, i32 %y) { 1442; CHECK-LABEL: @icmp_sub1_sge( 1443; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 %x, %y 1444; CHECK-NEXT: ret i1 [[CMP]] 1445; 1446 %sub = add nsw i32 %x, -1 1447 %cmp = icmp sge i32 %sub, %y 1448 ret i1 %cmp 1449} 1450 1451define i1 @icmp_add1_sgt(i32 %x, i32 %y) { 1452; CHECK-LABEL: @icmp_add1_sgt( 1453; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 %x, %y 1454; CHECK-NEXT: ret i1 [[CMP]] 1455; 1456 %add = add nsw i32 %x, 1 1457 %cmp = icmp sgt i32 %add, %y 1458 ret i1 %cmp 1459} 1460 1461define i1 @icmp_sub1_slt(i32 %x, i32 %y) { 1462; CHECK-LABEL: @icmp_sub1_slt( 1463; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 %x, %y 1464; CHECK-NEXT: ret i1 [[CMP]] 1465; 1466 %sub = add nsw i32 %x, -1 1467 %cmp = icmp slt i32 %sub, %y 1468 ret i1 %cmp 1469} 1470 1471define i1 @icmp_add1_sle(i32 %x, i32 %y) { 1472; CHECK-LABEL: @icmp_add1_sle( 1473; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %x, %y 1474; CHECK-NEXT: ret i1 [[CMP]] 1475; 1476 %add = add nsw i32 %x, 1 1477 %cmp = icmp sle i32 %add, %y 1478 ret i1 %cmp 1479} 1480 1481define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) { 1482; CHECK-LABEL: @icmp_add20_sge_add57( 1483; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 %y, 37 1484; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], %x 1485; CHECK-NEXT: ret i1 [[CMP]] 1486; 1487 %1 = add nsw i32 %x, 20 1488 %2 = add nsw i32 %y, 57 1489 %cmp = icmp sge i32 %1, %2 1490 ret i1 %cmp 1491} 1492 1493define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) { 1494; CHECK-LABEL: @icmp_sub57_sge_sub20( 1495; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 %x, -37 1496; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[TMP1]], %y 1497; CHECK-NEXT: ret i1 [[CMP]] 1498; 1499 %1 = add nsw i32 %x, -57 1500 %2 = add nsw i32 %y, -20 1501 %cmp = icmp sge i32 %1, %2 1502 ret i1 %cmp 1503} 1504 1505define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { 1506; CHECK-LABEL: @icmp_and_shl_neg_ne_0( 1507; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %B 1508; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], %A 1509; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0 1510; CHECK-NEXT: ret i1 [[CMP]] 1511; 1512 %neg = xor i32 %A, -1 1513 %shl = shl i32 1, %B 1514 %and = and i32 %shl, %neg 1515 %cmp = icmp ne i32 %and, 0 1516 ret i1 %cmp 1517} 1518 1519define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) { 1520; CHECK-LABEL: @icmp_and_shl_neg_eq_0( 1521; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %B 1522; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], %A 1523; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 0 1524; CHECK-NEXT: ret i1 [[CMP]] 1525; 1526 %neg = xor i32 %A, -1 1527 %shl = shl i32 1, %B 1528 %and = and i32 %shl, %neg 1529 %cmp = icmp eq i32 %and, 0 1530 ret i1 %cmp 1531} 1532 1533define i1 @icmp_add_and_shr_ne_0(i32 %X) { 1534; CHECK-LABEL: @icmp_add_and_shr_ne_0( 1535; CHECK-NEXT: [[AND:%.*]] = and i32 %X, 240 1536; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 224 1537; CHECK-NEXT: ret i1 [[TOBOOL]] 1538; 1539 %shr = lshr i32 %X, 4 1540 %and = and i32 %shr, 15 1541 %add = add i32 %and, -14 1542 %tobool = icmp ne i32 %add, 0 1543 ret i1 %tobool 1544} 1545 1546define <2 x i1> @icmp_add_and_shr_ne_0_vec(<2 x i32> %X) { 1547; CHECK-LABEL: @icmp_add_and_shr_ne_0_vec( 1548; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %X, <i32 240, i32 240> 1549; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <2 x i32> [[AND]], <i32 224, i32 224> 1550; CHECK-NEXT: ret <2 x i1> [[TOBOOL]] 1551; 1552 %shr = lshr <2 x i32> %X, <i32 4, i32 4> 1553 %and = and <2 x i32> %shr, <i32 15, i32 15> 1554 %add = add <2 x i32> %and, <i32 -14, i32 -14> 1555 %tobool = icmp ne <2 x i32> %add, zeroinitializer 1556 ret <2 x i1> %tobool 1557} 1558 1559; PR16244 1560define i1 @test71(i8* %x) { 1561; CHECK-LABEL: @test71( 1562; CHECK-NEXT: ret i1 false 1563; 1564 %a = getelementptr i8, i8* %x, i64 8 1565 %b = getelementptr inbounds i8, i8* %x, i64 8 1566 %c = icmp ugt i8* %a, %b 1567 ret i1 %c 1568} 1569 1570define i1 @test71_as1(i8 addrspace(1)* %x) { 1571; CHECK-LABEL: @test71_as1( 1572; CHECK-NEXT: ret i1 false 1573; 1574 %a = getelementptr i8, i8 addrspace(1)* %x, i64 8 1575 %b = getelementptr inbounds i8, i8 addrspace(1)* %x, i64 8 1576 %c = icmp ugt i8 addrspace(1)* %a, %b 1577 ret i1 %c 1578} 1579 1580define i1 @icmp_shl_1_V_ult_32(i32 %V) { 1581; CHECK-LABEL: @icmp_shl_1_V_ult_32( 1582; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %V, 5 1583; CHECK-NEXT: ret i1 [[CMP]] 1584; 1585 %shl = shl i32 1, %V 1586 %cmp = icmp ult i32 %shl, 32 1587 ret i1 %cmp 1588} 1589 1590define <2 x i1> @icmp_shl_1_V_ult_32_vec(<2 x i32> %V) { 1591; CHECK-LABEL: @icmp_shl_1_V_ult_32_vec( 1592; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %V, <i32 5, i32 5> 1593; CHECK-NEXT: ret <2 x i1> [[CMP]] 1594; 1595 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1596 %cmp = icmp ult <2 x i32> %shl, <i32 32, i32 32> 1597 ret <2 x i1> %cmp 1598} 1599 1600define i1 @icmp_shl_1_V_eq_32(i32 %V) { 1601; CHECK-LABEL: @icmp_shl_1_V_eq_32( 1602; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %V, 5 1603; CHECK-NEXT: ret i1 [[CMP]] 1604; 1605 %shl = shl i32 1, %V 1606 %cmp = icmp eq i32 %shl, 32 1607 ret i1 %cmp 1608} 1609 1610define <2 x i1> @icmp_shl_1_V_eq_32_vec(<2 x i32> %V) { 1611; CHECK-LABEL: @icmp_shl_1_V_eq_32_vec( 1612; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %V, <i32 5, i32 5> 1613; CHECK-NEXT: ret <2 x i1> [[CMP]] 1614; 1615 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1616 %cmp = icmp eq <2 x i32> %shl, <i32 32, i32 32> 1617 ret <2 x i1> %cmp 1618} 1619 1620define i1 @icmp_shl_1_V_ult_30(i32 %V) { 1621; CHECK-LABEL: @icmp_shl_1_V_ult_30( 1622; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %V, 5 1623; CHECK-NEXT: ret i1 [[CMP]] 1624; 1625 %shl = shl i32 1, %V 1626 %cmp = icmp ult i32 %shl, 30 1627 ret i1 %cmp 1628} 1629 1630define <2 x i1> @icmp_shl_1_V_ult_30_vec(<2 x i32> %V) { 1631; CHECK-LABEL: @icmp_shl_1_V_ult_30_vec( 1632; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %V, <i32 5, i32 5> 1633; CHECK-NEXT: ret <2 x i1> [[CMP]] 1634; 1635 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1636 %cmp = icmp ult <2 x i32> %shl, <i32 30, i32 30> 1637 ret <2 x i1> %cmp 1638} 1639 1640define i1 @icmp_shl_1_V_ugt_30(i32 %V) { 1641; CHECK-LABEL: @icmp_shl_1_V_ugt_30( 1642; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %V, 4 1643; CHECK-NEXT: ret i1 [[CMP]] 1644; 1645 %shl = shl i32 1, %V 1646 %cmp = icmp ugt i32 %shl, 30 1647 ret i1 %cmp 1648} 1649 1650define <2 x i1> @icmp_shl_1_V_ugt_30_vec(<2 x i32> %V) { 1651; CHECK-LABEL: @icmp_shl_1_V_ugt_30_vec( 1652; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %V, <i32 4, i32 4> 1653; CHECK-NEXT: ret <2 x i1> [[CMP]] 1654; 1655 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1656 %cmp = icmp ugt <2 x i32> %shl, <i32 30, i32 30> 1657 ret <2 x i1> %cmp 1658} 1659 1660define i1 @icmp_shl_1_V_ule_30(i32 %V) { 1661; CHECK-LABEL: @icmp_shl_1_V_ule_30( 1662; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %V, 5 1663; CHECK-NEXT: ret i1 [[CMP]] 1664; 1665 %shl = shl i32 1, %V 1666 %cmp = icmp ule i32 %shl, 30 1667 ret i1 %cmp 1668} 1669 1670define <2 x i1> @icmp_shl_1_V_ule_30_vec(<2 x i32> %V) { 1671; CHECK-LABEL: @icmp_shl_1_V_ule_30_vec( 1672; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %V, <i32 5, i32 5> 1673; CHECK-NEXT: ret <2 x i1> [[CMP]] 1674; 1675 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1676 %cmp = icmp ule <2 x i32> %shl, <i32 30, i32 30> 1677 ret <2 x i1> %cmp 1678} 1679 1680define i1 @icmp_shl_1_V_uge_30(i32 %V) { 1681; CHECK-LABEL: @icmp_shl_1_V_uge_30( 1682; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %V, 4 1683; CHECK-NEXT: ret i1 [[CMP]] 1684; 1685 %shl = shl i32 1, %V 1686 %cmp = icmp uge i32 %shl, 30 1687 ret i1 %cmp 1688} 1689 1690define <2 x i1> @icmp_shl_1_V_uge_30_vec(<2 x i32> %V) { 1691; CHECK-LABEL: @icmp_shl_1_V_uge_30_vec( 1692; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %V, <i32 4, i32 4> 1693; CHECK-NEXT: ret <2 x i1> [[CMP]] 1694; 1695 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1696 %cmp = icmp uge <2 x i32> %shl, <i32 30, i32 30> 1697 ret <2 x i1> %cmp 1698} 1699 1700define i1 @icmp_shl_1_V_uge_2147483648(i32 %V) { 1701; CHECK-LABEL: @icmp_shl_1_V_uge_2147483648( 1702; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %V, 31 1703; CHECK-NEXT: ret i1 [[CMP]] 1704; 1705 %shl = shl i32 1, %V 1706 %cmp = icmp uge i32 %shl, 2147483648 1707 ret i1 %cmp 1708} 1709 1710define <2 x i1> @icmp_shl_1_V_uge_2147483648_vec(<2 x i32> %V) { 1711; CHECK-LABEL: @icmp_shl_1_V_uge_2147483648_vec( 1712; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> %V, <i32 31, i32 31> 1713; CHECK-NEXT: ret <2 x i1> [[CMP]] 1714; 1715 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1716 %cmp = icmp uge <2 x i32> %shl, <i32 2147483648, i32 2147483648> 1717 ret <2 x i1> %cmp 1718} 1719 1720define i1 @icmp_shl_1_V_ult_2147483648(i32 %V) { 1721; CHECK-LABEL: @icmp_shl_1_V_ult_2147483648( 1722; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 %V, 31 1723; CHECK-NEXT: ret i1 [[CMP]] 1724; 1725 %shl = shl i32 1, %V 1726 %cmp = icmp ult i32 %shl, 2147483648 1727 ret i1 %cmp 1728} 1729 1730define <2 x i1> @icmp_shl_1_V_ult_2147483648_vec(<2 x i32> %V) { 1731; CHECK-LABEL: @icmp_shl_1_V_ult_2147483648_vec( 1732; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> %V, <i32 31, i32 31> 1733; CHECK-NEXT: ret <2 x i1> [[CMP]] 1734; 1735 %shl = shl <2 x i32> <i32 1, i32 1>, %V 1736 %cmp = icmp ult <2 x i32> %shl, <i32 2147483648, i32 2147483648> 1737 ret <2 x i1> %cmp 1738} 1739 1740define i1 @or_icmp_eq_B_0_icmp_ult_A_B(i64 %a, i64 %b) { 1741; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B( 1742; CHECK-NEXT: [[TMP1:%.*]] = add i64 %b, -1 1743; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[TMP1]], %a 1744; CHECK-NEXT: ret i1 [[TMP2]] 1745; 1746 %1 = icmp eq i64 %b, 0 1747 %2 = icmp ult i64 %a, %b 1748 %3 = or i1 %1, %2 1749 ret i1 %3 1750} 1751 1752define i1 @icmp_add_ult_2(i32 %X) { 1753; CHECK-LABEL: @icmp_add_ult_2( 1754; CHECK-NEXT: [[TMP1:%.*]] = and i32 %X, -2 1755; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 14 1756; CHECK-NEXT: ret i1 [[CMP]] 1757; 1758 %add = add i32 %X, -14 1759 %cmp = icmp ult i32 %add, 2 1760 ret i1 %cmp 1761} 1762 1763define <2 x i1> @icmp_add_X_-14_ult_2_vec(<2 x i32> %X) { 1764; CHECK-LABEL: @icmp_add_X_-14_ult_2_vec( 1765; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %X, <i32 -2, i32 -2> 1766; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 14, i32 14> 1767; CHECK-NEXT: ret <2 x i1> [[CMP]] 1768; 1769 %add = add <2 x i32> %X, <i32 -14, i32 -14> 1770 %cmp = icmp ult <2 x i32> %add, <i32 2, i32 2> 1771 ret <2 x i1> %cmp 1772} 1773 1774define i1 @icmp_sub_3_X_ult_2(i32 %X) { 1775; CHECK-LABEL: @icmp_sub_3_X_ult_2( 1776; CHECK-NEXT: [[TMP1:%.*]] = or i32 %X, 1 1777; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 3 1778; CHECK-NEXT: ret i1 [[CMP]] 1779; 1780 %add = sub i32 3, %X 1781 %cmp = icmp ult i32 %add, 2 1782 ret i1 %cmp 1783} 1784 1785define <2 x i1> @icmp_sub_3_X_ult_2_vec(<2 x i32> %X) { 1786; CHECK-LABEL: @icmp_sub_3_X_ult_2_vec( 1787; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> %X, <i32 1, i32 1> 1788; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 3, i32 3> 1789; CHECK-NEXT: ret <2 x i1> [[CMP]] 1790; 1791 %add = sub <2 x i32> <i32 3, i32 3>, %X 1792 %cmp = icmp ult <2 x i32> %add, <i32 2, i32 2> 1793 ret <2 x i1> %cmp 1794} 1795 1796define i1 @icmp_add_X_-14_uge_2(i32 %X) { 1797; CHECK-LABEL: @icmp_add_X_-14_uge_2( 1798; CHECK-NEXT: [[TMP1:%.*]] = and i32 %X, -2 1799; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 14 1800; CHECK-NEXT: ret i1 [[CMP]] 1801; 1802 %add = add i32 %X, -14 1803 %cmp = icmp uge i32 %add, 2 1804 ret i1 %cmp 1805} 1806 1807define <2 x i1> @icmp_add_X_-14_uge_2_vec(<2 x i32> %X) { 1808; CHECK-LABEL: @icmp_add_X_-14_uge_2_vec( 1809; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %X, <i32 -2, i32 -2> 1810; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], <i32 14, i32 14> 1811; CHECK-NEXT: ret <2 x i1> [[CMP]] 1812; 1813 %add = add <2 x i32> %X, <i32 -14, i32 -14> 1814 %cmp = icmp uge <2 x i32> %add, <i32 2, i32 2> 1815 ret <2 x i1> %cmp 1816} 1817 1818define i1 @icmp_sub_3_X_uge_2(i32 %X) { 1819; CHECK-LABEL: @icmp_sub_3_X_uge_2( 1820; CHECK-NEXT: [[TMP1:%.*]] = or i32 %X, 1 1821; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 3 1822; CHECK-NEXT: ret i1 [[CMP]] 1823; 1824 %add = sub i32 3, %X 1825 %cmp = icmp uge i32 %add, 2 1826 ret i1 %cmp 1827} 1828 1829define <2 x i1> @icmp_sub_3_X_uge_2_vec(<2 x i32> %X) { 1830; CHECK-LABEL: @icmp_sub_3_X_uge_2_vec( 1831; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> %X, <i32 1, i32 1> 1832; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], <i32 3, i32 3> 1833; CHECK-NEXT: ret <2 x i1> [[CMP]] 1834; 1835 %add = sub <2 x i32> <i32 3, i32 3>, %X 1836 %cmp = icmp uge <2 x i32> %add, <i32 2, i32 2> 1837 ret <2 x i1> %cmp 1838} 1839 1840define i1 @icmp_and_X_-16_eq-16(i32 %X) { 1841; CHECK-LABEL: @icmp_and_X_-16_eq-16( 1842; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %X, -17 1843; CHECK-NEXT: ret i1 [[CMP]] 1844; 1845 %and = and i32 %X, -16 1846 %cmp = icmp eq i32 %and, -16 1847 ret i1 %cmp 1848} 1849 1850define <2 x i1> @icmp_and_X_-16_eq-16_vec(<2 x i32> %X) { 1851; CHECK-LABEL: @icmp_and_X_-16_eq-16_vec( 1852; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %X, <i32 -17, i32 -17> 1853; CHECK-NEXT: ret <2 x i1> [[CMP]] 1854; 1855 %and = and <2 x i32> %X, <i32 -16, i32 -16> 1856 %cmp = icmp eq <2 x i32> %and, <i32 -16, i32 -16> 1857 ret <2 x i1> %cmp 1858} 1859 1860define i1 @icmp_and_X_-16_ne-16(i32 %X) { 1861; CHECK-LABEL: @icmp_and_X_-16_ne-16( 1862; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %X, -16 1863; CHECK-NEXT: ret i1 [[CMP]] 1864; 1865 %and = and i32 %X, -16 1866 %cmp = icmp ne i32 %and, -16 1867 ret i1 %cmp 1868} 1869 1870define <2 x i1> @icmp_and_X_-16_ne-16_vec(<2 x i32> %X) { 1871; CHECK-LABEL: @icmp_and_X_-16_ne-16_vec( 1872; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %X, <i32 -16, i32 -16> 1873; CHECK-NEXT: ret <2 x i1> [[CMP]] 1874; 1875 %and = and <2 x i32> %X, <i32 -16, i32 -16> 1876 %cmp = icmp ne <2 x i32> %and, <i32 -16, i32 -16> 1877 ret <2 x i1> %cmp 1878} 1879 1880define i1 @shrink_constant(i32 %X) { 1881; CHECK-LABEL: @shrink_constant( 1882; CHECK-NEXT: [[XOR:%.*]] = xor i32 %X, -12 1883; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[XOR]], 4 1884; CHECK-NEXT: ret i1 [[CMP]] 1885; 1886 %xor = xor i32 %X, -9 1887 %cmp = icmp ult i32 %xor, 4 1888 ret i1 %cmp 1889} 1890 1891; FIXME: This doesn't change because of a limitation in 'DemandedBitsLHSMask'. 1892define <2 x i1> @shrink_constant_vec(<2 x i32> %X) { 1893; CHECK-LABEL: @shrink_constant_vec( 1894; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> %X, <i32 -9, i32 -9> 1895; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[XOR]], <i32 4, i32 4> 1896; CHECK-NEXT: ret <2 x i1> [[CMP]] 1897; 1898 %xor = xor <2 x i32> %X, <i32 -9, i32 -9> 1899 %cmp = icmp ult <2 x i32> %xor, <i32 4, i32 4> 1900 ret <2 x i1> %cmp 1901} 1902 1903; This test requires 3 different transforms to get to the result. 1904define i1 @icmp_sub_-1_X_ult_4(i32 %X) { 1905; CHECK-LABEL: @icmp_sub_-1_X_ult_4( 1906; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %X, -5 1907; CHECK-NEXT: ret i1 [[CMP]] 1908; 1909 %sub = sub i32 -1, %X 1910 %cmp = icmp ult i32 %sub, 4 1911 ret i1 %cmp 1912} 1913 1914define <2 x i1> @icmp_xor_neg4_X_ult_4_vec(<2 x i32> %X) { 1915; CHECK-LABEL: @icmp_xor_neg4_X_ult_4_vec( 1916; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %X, <i32 -5, i32 -5> 1917; CHECK-NEXT: ret <2 x i1> [[CMP]] 1918; 1919 %xor = xor <2 x i32> %X, <i32 -4, i32 -4> 1920 %cmp = icmp ult <2 x i32> %xor, <i32 4, i32 4> 1921 ret <2 x i1> %cmp 1922} 1923 1924define i1 @icmp_sub_-1_X_uge_4(i32 %X) { 1925; CHECK-LABEL: @icmp_sub_-1_X_uge_4( 1926; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %X, -4 1927; CHECK-NEXT: ret i1 [[CMP]] 1928; 1929 %sub = sub i32 -1, %X 1930 %cmp = icmp uge i32 %sub, 4 1931 ret i1 %cmp 1932} 1933 1934define <2 x i1> @icmp_xor_neg4_X_uge_4_vec(<2 x i32> %X) { 1935; CHECK-LABEL: @icmp_xor_neg4_X_uge_4_vec( 1936; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %X, <i32 -4, i32 -4> 1937; CHECK-NEXT: ret <2 x i1> [[CMP]] 1938; 1939 %xor = xor <2 x i32> %X, <i32 -4, i32 -4> 1940 %cmp = icmp uge <2 x i32> %xor, <i32 4, i32 4> 1941 ret <2 x i1> %cmp 1942} 1943 1944define i1 @icmp_swap_operands_for_cse(i32 %X, i32 %Y) { 1945; CHECK-LABEL: @icmp_swap_operands_for_cse( 1946; CHECK-NEXT: entry: 1947; CHECK-NEXT: [[SUB:%.*]] = sub i32 %X, %Y 1948; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %X, %Y 1949; CHECK-NEXT: br i1 [[CMP]], label %true, label %false 1950; CHECK: true: 1951; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[SUB]], 1 1952; CHECK-NEXT: br label %end 1953; CHECK: false: 1954; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SUB]], 16 1955; CHECK-NEXT: br label %end 1956; CHECK: end: 1957; CHECK-NEXT: [[RES_IN:%.*]] = phi i32 [ [[TMP0]], %true ], [ [[TMP1]], %false ] 1958; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[RES:%.*]].in, 0 1959; CHECK-NEXT: ret i1 [[RES]] 1960; 1961entry: 1962 %sub = sub i32 %X, %Y 1963 %cmp = icmp ugt i32 %Y, %X 1964 br i1 %cmp, label %true, label %false 1965true: 1966 %restrue = trunc i32 %sub to i1 1967 br label %end 1968false: 1969 %shift = lshr i32 %sub, 4 1970 %resfalse = trunc i32 %shift to i1 1971 br label %end 1972end: 1973 %res = phi i1 [%restrue, %true], [%resfalse, %false] 1974 ret i1 %res 1975} 1976 1977define i1 @icmp_swap_operands_for_cse2(i32 %X, i32 %Y) { 1978; CHECK-LABEL: @icmp_swap_operands_for_cse2( 1979; CHECK-NEXT: entry: 1980; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %X, %Y 1981; CHECK-NEXT: br i1 [[CMP]], label %true, label %false 1982; CHECK: true: 1983; CHECK-NEXT: [[SUB:%.*]] = sub i32 %X, %Y 1984; CHECK-NEXT: [[SUB1:%.*]] = sub i32 %X, %Y 1985; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]] 1986; CHECK-NEXT: br label %end 1987; CHECK: false: 1988; CHECK-NEXT: [[SUB2:%.*]] = sub i32 %Y, %X 1989; CHECK-NEXT: br label %end 1990; CHECK: end: 1991; CHECK-NEXT: [[RES_IN_IN:%.*]] = phi i32 [ [[ADD]], %true ], [ [[SUB2]], %false ] 1992; CHECK-NEXT: [[RES_IN:%.*]] = and i32 [[RES_IN:%.*]].in, 1 1993; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[RES:%.*]].in, 0 1994; CHECK-NEXT: ret i1 [[RES]] 1995; 1996entry: 1997 %cmp = icmp ugt i32 %Y, %X 1998 br i1 %cmp, label %true, label %false 1999true: 2000 %sub = sub i32 %X, %Y 2001 %sub1 = sub i32 %X, %Y 2002 %add = add i32 %sub, %sub1 2003 %restrue = trunc i32 %add to i1 2004 br label %end 2005false: 2006 %sub2 = sub i32 %Y, %X 2007 %resfalse = trunc i32 %sub2 to i1 2008 br label %end 2009end: 2010 %res = phi i1 [%restrue, %true], [%resfalse, %false] 2011 ret i1 %res 2012} 2013 2014define i1 @icmp_do_not_swap_operands_for_cse(i32 %X, i32 %Y) { 2015; CHECK-LABEL: @icmp_do_not_swap_operands_for_cse( 2016; CHECK-NEXT: entry: 2017; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %Y, %X 2018; CHECK-NEXT: br i1 [[CMP]], label %true, label %false 2019; CHECK: true: 2020; CHECK-NEXT: [[SUB:%.*]] = sub i32 %X, %Y 2021; CHECK-NEXT: br label %end 2022; CHECK: false: 2023; CHECK-NEXT: [[SUB2:%.*]] = sub i32 %Y, %X 2024; CHECK-NEXT: br label %end 2025; CHECK: end: 2026; CHECK-NEXT: [[RES_IN_IN:%.*]] = phi i32 [ [[SUB]], %true ], [ [[SUB2]], %false ] 2027; CHECK-NEXT: [[RES_IN:%.*]] = and i32 [[RES_IN:%.*]].in, 1 2028; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[RES:%.*]].in, 0 2029; CHECK-NEXT: ret i1 [[RES]] 2030; 2031entry: 2032 %cmp = icmp ugt i32 %Y, %X 2033 br i1 %cmp, label %true, label %false 2034true: 2035 %sub = sub i32 %X, %Y 2036 %restrue = trunc i32 %sub to i1 2037 br label %end 2038false: 2039 %sub2 = sub i32 %Y, %X 2040 %resfalse = trunc i32 %sub2 to i1 2041 br label %end 2042end: 2043 %res = phi i1 [%restrue, %true], [%resfalse, %false] 2044 ret i1 %res 2045} 2046 2047define i1 @icmp_lshr_lshr_eq(i32 %a, i32 %b) { 2048; CHECK-LABEL: @icmp_lshr_lshr_eq( 2049; CHECK-NEXT: [[Z_UNSHIFTED:%.*]] = xor i32 %a, %b 2050; CHECK-NEXT: [[Z:%.*]] = icmp ult i32 [[Z:%.*]].unshifted, 1073741824 2051; CHECK-NEXT: ret i1 [[Z]] 2052; 2053 %x = lshr i32 %a, 30 2054 %y = lshr i32 %b, 30 2055 %z = icmp eq i32 %x, %y 2056 ret i1 %z 2057} 2058 2059define i1 @icmp_ashr_ashr_ne(i32 %a, i32 %b) { 2060; CHECK-LABEL: @icmp_ashr_ashr_ne( 2061; CHECK-NEXT: [[Z_UNSHIFTED:%.*]] = xor i32 %a, %b 2062; CHECK-NEXT: [[Z:%.*]] = icmp ugt i32 [[Z:%.*]].unshifted, 255 2063; CHECK-NEXT: ret i1 [[Z]] 2064; 2065 %x = ashr i32 %a, 8 2066 %y = ashr i32 %b, 8 2067 %z = icmp ne i32 %x, %y 2068 ret i1 %z 2069} 2070 2071define i1 @icmp_neg_cst_slt(i32 %a) { 2072; CHECK-LABEL: @icmp_neg_cst_slt( 2073; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 %a, 10 2074; CHECK-NEXT: ret i1 [[TMP1]] 2075; 2076 %1 = sub nsw i32 0, %a 2077 %2 = icmp slt i32 %1, -10 2078 ret i1 %2 2079} 2080 2081define i1 @icmp_and_or_lshr(i32 %x, i32 %y) { 2082; CHECK-LABEL: @icmp_and_or_lshr( 2083; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, %y 2084; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1 2085; CHECK-NEXT: [[AND3:%.*]] = and i32 [[OR2]], %x 2086; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND3]], 0 2087; CHECK-NEXT: ret i1 [[RET]] 2088; 2089 %shf = lshr i32 %x, %y 2090 %or = or i32 %shf, %x 2091 %and = and i32 %or, 1 2092 %ret = icmp ne i32 %and, 0 2093 ret i1 %ret 2094} 2095 2096define <2 x i1> @icmp_and_or_lshr_vec(<2 x i32> %x, <2 x i32> %y) { 2097; CHECK-LABEL: @icmp_and_or_lshr_vec( 2098; CHECK-NEXT: [[SHF1:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, %y 2099; CHECK-NEXT: [[OR2:%.*]] = or <2 x i32> [[SHF1]], <i32 1, i32 1> 2100; CHECK-NEXT: [[AND3:%.*]] = and <2 x i32> [[OR2]], %x 2101; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[AND3]], zeroinitializer 2102; CHECK-NEXT: ret <2 x i1> [[RET]] 2103; 2104 %shf = lshr <2 x i32> %x, %y 2105 %or = or <2 x i32> %shf, %x 2106 %and = and <2 x i32> %or, <i32 1, i32 1> 2107 %ret = icmp ne <2 x i32> %and, zeroinitializer 2108 ret <2 x i1> %ret 2109} 2110 2111define i1 @icmp_and_or_lshr_cst(i32 %x) { 2112; CHECK-LABEL: @icmp_and_or_lshr_cst( 2113; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 3 2114; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND1]], 0 2115; CHECK-NEXT: ret i1 [[RET]] 2116; 2117 %shf = lshr i32 %x, 1 2118 %or = or i32 %shf, %x 2119 %and = and i32 %or, 1 2120 %ret = icmp ne i32 %and, 0 2121 ret i1 %ret 2122} 2123 2124define <2 x i1> @icmp_and_or_lshr_cst_vec(<2 x i32> %x) { 2125; CHECK-LABEL: @icmp_and_or_lshr_cst_vec( 2126; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> %x, <i32 3, i32 3> 2127; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[AND1]], zeroinitializer 2128; CHECK-NEXT: ret <2 x i1> [[RET]] 2129; 2130 %shf = lshr <2 x i32> %x, <i32 1, i32 1> 2131 %or = or <2 x i32> %shf, %x 2132 %and = and <2 x i32> %or, <i32 1, i32 1> 2133 %ret = icmp ne <2 x i32> %and, zeroinitializer 2134 ret <2 x i1> %ret 2135} 2136 2137define i1 @shl_ap1_zero_ap2_non_zero_2(i32 %a) { 2138; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_2( 2139; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %a, 29 2140; CHECK-NEXT: ret i1 [[CMP]] 2141; 2142 %shl = shl i32 4, %a 2143 %cmp = icmp eq i32 %shl, 0 2144 ret i1 %cmp 2145} 2146 2147define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec(<2 x i32> %a) { 2148; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_2_vec( 2149; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 29, i32 29> 2150; CHECK-NEXT: ret <2 x i1> [[CMP]] 2151; 2152 %shl = shl <2 x i32> <i32 4, i32 4>, %a 2153 %cmp = icmp eq <2 x i32> %shl, zeroinitializer 2154 ret <2 x i1> %cmp 2155} 2156 2157define i1 @shl_ap1_zero_ap2_non_zero_4(i32 %a) { 2158; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_4( 2159; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %a, 30 2160; CHECK-NEXT: ret i1 [[CMP]] 2161; 2162 %shl = shl i32 -2, %a 2163 %cmp = icmp eq i32 %shl, 0 2164 ret i1 %cmp 2165} 2166 2167define i1 @shl_ap1_non_zero_ap2_non_zero_both_positive(i32 %a) { 2168; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_both_positive( 2169; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, 0 2170; CHECK-NEXT: ret i1 [[CMP]] 2171; 2172 %shl = shl i32 50, %a 2173 %cmp = icmp eq i32 %shl, 50 2174 ret i1 %cmp 2175} 2176 2177define i1 @shl_ap1_non_zero_ap2_non_zero_both_negative(i32 %a) { 2178; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_both_negative( 2179; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, 0 2180; CHECK-NEXT: ret i1 [[CMP]] 2181; 2182 %shl = shl i32 -50, %a 2183 %cmp = icmp eq i32 %shl, -50 2184 ret i1 %cmp 2185} 2186 2187define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_1(i32 %a) { 2188; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_ap1_1( 2189; CHECK-NEXT: ret i1 false 2190; 2191 %shl = shl i32 50, %a 2192 %cmp = icmp eq i32 %shl, 25 2193 ret i1 %cmp 2194} 2195 2196define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_2(i32 %a) { 2197; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_ap1_2( 2198; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, 1 2199; CHECK-NEXT: ret i1 [[CMP]] 2200; 2201 %shl = shl i32 25, %a 2202 %cmp = icmp eq i32 %shl, 50 2203 ret i1 %cmp 2204} 2205 2206define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_3(i32 %a) { 2207; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_ap1_3( 2208; CHECK-NEXT: ret i1 false 2209; 2210 %shl = shl i32 26, %a 2211 %cmp = icmp eq i32 %shl, 50 2212 ret i1 %cmp 2213} 2214 2215define i1 @icmp_sgt_zero_add_nsw(i32 %a) { 2216; CHECK-LABEL: @icmp_sgt_zero_add_nsw( 2217; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 %a, -1 2218; CHECK-NEXT: ret i1 [[CMP]] 2219; 2220 %add = add nsw i32 %a, 1 2221 %cmp = icmp sgt i32 %add, 0 2222 ret i1 %cmp 2223} 2224 2225define i1 @icmp_sge_zero_add_nsw(i32 %a) { 2226; CHECK-LABEL: @icmp_sge_zero_add_nsw( 2227; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 %a, -2 2228; CHECK-NEXT: ret i1 [[CMP]] 2229; 2230 %add = add nsw i32 %a, 1 2231 %cmp = icmp sge i32 %add, 0 2232 ret i1 %cmp 2233} 2234 2235define i1 @icmp_slt_zero_add_nsw(i32 %a) { 2236; CHECK-LABEL: @icmp_slt_zero_add_nsw( 2237; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %a, -1 2238; CHECK-NEXT: ret i1 [[CMP]] 2239; 2240 %add = add nsw i32 %a, 1 2241 %cmp = icmp slt i32 %add, 0 2242 ret i1 %cmp 2243} 2244 2245define i1 @icmp_sle_zero_add_nsw(i32 %a) { 2246; CHECK-LABEL: @icmp_sle_zero_add_nsw( 2247; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 %a, 0 2248; CHECK-NEXT: ret i1 [[CMP]] 2249; 2250 %add = add nsw i32 %a, 1 2251 %cmp = icmp sle i32 %add, 0 2252 ret i1 %cmp 2253} 2254 2255define zeroext i1 @icmp_cmpxchg_strong(i32* %sc, i32 %old_val, i32 %new_val) { 2256; CHECK-LABEL: @icmp_cmpxchg_strong( 2257; CHECK-NEXT: [[XCHG:%.*]] = cmpxchg i32* %sc, i32 %old_val, i32 %new_val seq_cst seq_cst 2258; CHECK-NEXT: [[ICMP:%.*]] = extractvalue { i32, i1 2259; 2260 %xchg = cmpxchg i32* %sc, i32 %old_val, i32 %new_val seq_cst seq_cst 2261 %xtrc = extractvalue { i32, i1 } %xchg, 0 2262 %icmp = icmp eq i32 %xtrc, %old_val 2263 ret i1 %icmp 2264} 2265 2266define i1 @f1(i64 %a, i64 %b) { 2267; CHECK-LABEL: @f1( 2268; CHECK-NEXT: [[V:%.*]] = icmp sge i64 %a, %b 2269; CHECK-NEXT: ret i1 [[V]] 2270; 2271 %t = sub nsw i64 %a, %b 2272 %v = icmp sge i64 %t, 0 2273 ret i1 %v 2274} 2275 2276define <2 x i1> @f1_vec(<2 x i64> %a, <2 x i64> %b) { 2277; CHECK-LABEL: @f1_vec( 2278; CHECK-NEXT: [[V:%.*]] = icmp sge <2 x i64> %a, %b 2279; CHECK-NEXT: ret <2 x i1> [[V]] 2280; 2281 %t = sub nsw <2 x i64> %a, %b 2282 %v = icmp sgt <2 x i64> %t, <i64 -1, i64 -1> 2283 ret <2 x i1> %v 2284} 2285 2286define i1 @f2(i64 %a, i64 %b) { 2287; CHECK-LABEL: @f2( 2288; CHECK-NEXT: [[V:%.*]] = icmp sgt i64 %a, %b 2289; CHECK-NEXT: ret i1 [[V]] 2290; 2291 %t = sub nsw i64 %a, %b 2292 %v = icmp sgt i64 %t, 0 2293 ret i1 %v 2294} 2295 2296define <2 x i1> @f2_vec(<2 x i64> %a, <2 x i64> %b) { 2297; CHECK-LABEL: @f2_vec( 2298; CHECK-NEXT: [[V:%.*]] = icmp sgt <2 x i64> %a, %b 2299; CHECK-NEXT: ret <2 x i1> [[V]] 2300; 2301 %t = sub nsw <2 x i64> %a, %b 2302 %v = icmp sgt <2 x i64> %t, zeroinitializer 2303 ret <2 x i1> %v 2304} 2305 2306define i1 @f3(i64 %a, i64 %b) { 2307; CHECK-LABEL: @f3( 2308; CHECK-NEXT: [[V:%.*]] = icmp slt i64 %a, %b 2309; CHECK-NEXT: ret i1 [[V]] 2310; 2311 %t = sub nsw i64 %a, %b 2312 %v = icmp slt i64 %t, 0 2313 ret i1 %v 2314} 2315 2316define <2 x i1> @f3_vec(<2 x i64> %a, <2 x i64> %b) { 2317; CHECK-LABEL: @f3_vec( 2318; CHECK-NEXT: [[V:%.*]] = icmp slt <2 x i64> %a, %b 2319; CHECK-NEXT: ret <2 x i1> [[V]] 2320; 2321 %t = sub nsw <2 x i64> %a, %b 2322 %v = icmp slt <2 x i64> %t, zeroinitializer 2323 ret <2 x i1> %v 2324} 2325 2326define i1 @f4(i64 %a, i64 %b) { 2327; CHECK-LABEL: @f4( 2328; CHECK-NEXT: [[V:%.*]] = icmp sle i64 %a, %b 2329; CHECK-NEXT: ret i1 [[V]] 2330; 2331 %t = sub nsw i64 %a, %b 2332 %v = icmp sle i64 %t, 0 2333 ret i1 %v 2334} 2335 2336define <2 x i1> @f4_vec(<2 x i64> %a, <2 x i64> %b) { 2337; CHECK-LABEL: @f4_vec( 2338; CHECK-NEXT: [[V:%.*]] = icmp sle <2 x i64> %a, %b 2339; CHECK-NEXT: ret <2 x i1> [[V]] 2340; 2341 %t = sub nsw <2 x i64> %a, %b 2342 %v = icmp slt <2 x i64> %t, <i64 1, i64 1> 2343 ret <2 x i1> %v 2344} 2345 2346define i32 @f5(i8 %a, i8 %b) { 2347; CHECK-LABEL: @f5( 2348; CHECK-NEXT: [[CONV:%.*]] = zext i8 %a to i32 2349; CHECK-NEXT: [[CONV3:%.*]] = zext i8 %b to i32 2350; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV3]] 2351; CHECK-NEXT: [[CMP4:%.*]] = icmp slt i32 [[SUB]], 0 2352; CHECK-NEXT: [[SUB7:%.*]] = sub nsw i32 0, [[SUB]] 2353; CHECK-NEXT: [[SUB7_SUB:%.*]] = select i1 [[CMP4]], i32 [[SUB7]], i32 [[SUB]] 2354; CHECK-NEXT: ret i32 [[SUB7_SUB]] 2355; 2356 %conv = zext i8 %a to i32 2357 %conv3 = zext i8 %b to i32 2358 %sub = sub nsw i32 %conv, %conv3 2359 %cmp4 = icmp slt i32 %sub, 0 2360 %sub7 = sub nsw i32 0, %sub 2361 %sub7.sub = select i1 %cmp4, i32 %sub7, i32 %sub 2362 ret i32 %sub7.sub 2363} 2364 2365define i32 @f6(i32 %a, i32 %b) { 2366; CHECK-LABEL: @f6( 2367; CHECK-NEXT: [[CMP_UNSHIFTED:%.*]] = xor i32 %a, %b 2368; CHECK-NEXT: [[CMP_MASK:%.*]] = and i32 [[CMP_UNSHIFTED]], 255 2369; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CMP:%.*]].mask, 0 2370; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP]], i32 10000, i32 0 2371; CHECK-NEXT: ret i32 [[S]] 2372; 2373 %sext = shl i32 %a, 24 2374 %conv = ashr i32 %sext, 24 2375 %sext6 = shl i32 %b, 24 2376 %conv4 = ashr i32 %sext6, 24 2377 %cmp = icmp eq i32 %conv, %conv4 2378 %s = select i1 %cmp, i32 10000, i32 0 2379 ret i32 %s 2380} 2381 2382define i32 @f7(i32 %a, i32 %b) { 2383; CHECK-LABEL: @f7( 2384; CHECK-NEXT: [[CMP_UNSHIFTED:%.*]] = xor i32 %a, %b 2385; CHECK-NEXT: [[CMP_MASK:%.*]] = and i32 [[CMP_UNSHIFTED]], 511 2386; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[CMP:%.*]].mask, 0 2387; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP]], i32 10000, i32 0 2388; CHECK-NEXT: ret i32 [[S]] 2389; 2390 %sext = shl i32 %a, 23 2391 %sext6 = shl i32 %b, 23 2392 %cmp = icmp ne i32 %sext, %sext6 2393 %s = select i1 %cmp, i32 10000, i32 0 2394 ret i32 %s 2395} 2396 2397define i1 @f8(i32 %val, i32 %lim) { 2398; CHECK-LABEL: @f8( 2399; CHECK-NEXT: [[R:%.*]] = icmp ne i32 %lim, 0 2400; CHECK-NEXT: ret i1 [[R]] 2401; 2402 %lim.sub = add i32 %lim, -1 2403 %val.and = and i32 %val, %lim.sub 2404 %r = icmp ult i32 %val.and, %lim 2405 ret i1 %r 2406} 2407 2408define i1 @f9(i32 %val, i32 %lim) { 2409; CHECK-LABEL: @f9( 2410; CHECK-NEXT: [[R:%.*]] = icmp ne i32 %lim, 0 2411; CHECK-NEXT: ret i1 [[R]] 2412; 2413 %lim.sub = sub i32 %lim, 1 2414 %val.and = and i32 %val, %lim.sub 2415 %r = icmp ult i32 %val.and, %lim 2416 ret i1 %r 2417} 2418 2419define i1 @f10(i16 %p) { 2420; CHECK-LABEL: @f10( 2421; CHECK-NEXT: [[CMP580:%.*]] = icmp uge i16 %p, mul (i16 zext (i8 ptrtoint (i1 (i16)* @f10 to i8) to i16), i16 zext (i8 ptrtoint (i1 (i16)* @f10 to i8) to i16)) 2422; CHECK-NEXT: ret i1 [[CMP580]] 2423; 2424 %cmp580 = icmp ule i16 mul (i16 zext (i8 ptrtoint (i1 (i16)* @f10 to i8) to i16), i16 zext (i8 ptrtoint (i1 (i16)* @f10 to i8) to i16)), %p 2425 ret i1 %cmp580 2426} 2427 2428define i1 @cmp_sgt_rhs_dec(float %x, i32 %i) { 2429; CHECK-LABEL: @cmp_sgt_rhs_dec( 2430; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32 2431; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[CONV]], %i 2432; CHECK-NEXT: ret i1 [[CMP]] 2433; 2434 %conv = fptosi float %x to i32 2435 %dec = sub nsw i32 %i, 1 2436 %cmp = icmp sgt i32 %conv, %dec 2437 ret i1 %cmp 2438} 2439 2440define i1 @cmp_sle_rhs_dec(float %x, i32 %i) { 2441; CHECK-LABEL: @cmp_sle_rhs_dec( 2442; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32 2443; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV]], %i 2444; CHECK-NEXT: ret i1 [[CMP]] 2445; 2446 %conv = fptosi float %x to i32 2447 %dec = sub nsw i32 %i, 1 2448 %cmp = icmp sle i32 %conv, %dec 2449 ret i1 %cmp 2450} 2451 2452define i1 @cmp_sge_rhs_inc(float %x, i32 %i) { 2453; CHECK-LABEL: @cmp_sge_rhs_inc( 2454; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32 2455; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], %i 2456; CHECK-NEXT: ret i1 [[CMP]] 2457; 2458 %conv = fptosi float %x to i32 2459 %inc = add nsw i32 %i, 1 2460 %cmp = icmp sge i32 %conv, %inc 2461 ret i1 %cmp 2462} 2463 2464define i1 @cmp_slt_rhs_inc(float %x, i32 %i) { 2465; CHECK-LABEL: @cmp_slt_rhs_inc( 2466; CHECK-NEXT: [[CONV:%.*]] = fptosi float %x to i32 2467; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], %i 2468; CHECK-NEXT: ret i1 [[CMP]] 2469; 2470 %conv = fptosi float %x to i32 2471 %inc = add nsw i32 %i, 1 2472 %cmp = icmp slt i32 %conv, %inc 2473 ret i1 %cmp 2474} 2475 2476define i1 @PR26407(i32 %x, i32 %y) { 2477; CHECK-LABEL: @PR26407( 2478; CHECK-NEXT: [[ADDX:%.*]] = add i32 %x, 2147483647 2479; CHECK-NEXT: [[ADDY:%.*]] = add i32 %y, 2147483647 2480; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[ADDX]], [[ADDY]] 2481; CHECK-NEXT: ret i1 [[CMP]] 2482; 2483 %addx = add i32 %x, 2147483647 2484 %addy = add i32 %y, 2147483647 2485 %cmp = icmp uge i32 %addx, %addy 2486 ret i1 %cmp 2487} 2488 2489define i1 @cmp_inverse_mask_bits_set_eq(i32 %x) { 2490; CHECK-LABEL: @cmp_inverse_mask_bits_set_eq( 2491; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, -43 2492; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], -43 2493; CHECK-NEXT: ret i1 [[CMP]] 2494; 2495 %or = or i32 %x, 42 2496 %cmp = icmp eq i32 %or, -1 2497 ret i1 %cmp 2498} 2499 2500define <2 x i1> @cmp_inverse_mask_bits_set_eq_vec(<2 x i32> %x) { 2501; CHECK-LABEL: @cmp_inverse_mask_bits_set_eq_vec( 2502; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %x, <i32 -43, i32 -43> 2503; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 -43, i32 -43> 2504; CHECK-NEXT: ret <2 x i1> [[CMP]] 2505; 2506 %or = or <2 x i32> %x, <i32 42, i32 42> 2507 %cmp = icmp eq <2 x i32> %or, <i32 -1, i32 -1> 2508 ret <2 x i1> %cmp 2509} 2510 2511define i1 @cmp_inverse_mask_bits_set_ne(i32 %x) { 2512; CHECK-LABEL: @cmp_inverse_mask_bits_set_ne( 2513; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, -43 2514; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], -43 2515; CHECK-NEXT: ret i1 [[CMP]] 2516; 2517 %or = or i32 %x, 42 2518 %cmp = icmp ne i32 %or, -1 2519 ret i1 %cmp 2520} 2521 2522; CHECK-LABEL: @idom_sign_bit_check_edge_dominates 2523define void @idom_sign_bit_check_edge_dominates(i64 %a) { 2524entry: 2525 %cmp = icmp slt i64 %a, 0 2526 br i1 %cmp, label %land.lhs.true, label %lor.rhs 2527 2528land.lhs.true: ; preds = %entry 2529 br label %lor.end 2530 2531; CHECK-LABEL: lor.rhs: 2532; CHECK-NOT: icmp sgt i64 %a, 0 2533; CHECK: icmp eq i64 %a, 0 2534lor.rhs: ; preds = %entry 2535 %cmp2 = icmp sgt i64 %a, 0 2536 br i1 %cmp2, label %land.rhs, label %lor.end 2537 2538land.rhs: ; preds = %lor.rhs 2539 br label %lor.end 2540 2541lor.end: ; preds = %land.rhs, %lor.rhs, %land.lhs.true 2542 ret void 2543} 2544 2545; CHECK-LABEL: @idom_sign_bit_check_edge_not_dominates 2546define void @idom_sign_bit_check_edge_not_dominates(i64 %a) { 2547entry: 2548 %cmp = icmp slt i64 %a, 0 2549 br i1 %cmp, label %land.lhs.true, label %lor.rhs 2550 2551land.lhs.true: ; preds = %entry 2552 br i1 undef, label %lor.end, label %lor.rhs 2553 2554; CHECK-LABEL: lor.rhs: 2555; CHECK: icmp sgt i64 %a, 0 2556; CHECK-NOT: icmp eq i64 %a, 0 2557lor.rhs: ; preds = %land.lhs.true, %entry 2558 %cmp2 = icmp sgt i64 %a, 0 2559 br i1 %cmp2, label %land.rhs, label %lor.end 2560 2561land.rhs: ; preds = %lor.rhs 2562 br label %lor.end 2563 2564lor.end: ; preds = %land.rhs, %lor.rhs, %land.lhs.true 2565 ret void 2566} 2567 2568; CHECK-LABEL: @idom_sign_bit_check_edge_dominates_select 2569define void @idom_sign_bit_check_edge_dominates_select(i64 %a, i64 %b) { 2570entry: 2571 %cmp = icmp slt i64 %a, 5 2572 br i1 %cmp, label %land.lhs.true, label %lor.rhs 2573 2574land.lhs.true: ; preds = %entry 2575 br label %lor.end 2576 2577; CHECK-LABEL: lor.rhs: 2578; CHECK-NOT: [[B:%.*]] = icmp sgt i64 %a, 5 2579; CHECK: [[C:%.*]] = icmp eq i64 %a, %b 2580; CHECK-NOT: [[D:%.*]] = select i1 [[B]], i64 %a, i64 5 2581; CHECK-NOT: icmp ne i64 [[D]], %b 2582; CHECK-NEXT: br i1 [[C]], label %lor.end, label %land.rhs 2583lor.rhs: ; preds = %entry 2584 %cmp2 = icmp sgt i64 %a, 5 2585 %select = select i1 %cmp2, i64 %a, i64 5 2586 %cmp3 = icmp ne i64 %select, %b 2587 br i1 %cmp3, label %land.rhs, label %lor.end 2588 2589land.rhs: ; preds = %lor.rhs 2590 br label %lor.end 2591 2592lor.end: ; preds = %land.rhs, %lor.rhs, %land.lhs.true 2593 ret void 2594} 2595 2596; CHECK-LABEL: @idom_zbranch 2597define void @idom_zbranch(i64 %a) { 2598entry: 2599 %cmp = icmp sgt i64 %a, 0 2600 br i1 %cmp, label %lor.end, label %lor.rhs 2601 2602; CHECK-LABEL: lor.rhs: 2603; CHECK: icmp slt i64 %a, 0 2604; CHECK-NOT: icmp eq i64 %a, 0 2605lor.rhs: ; preds = %entry 2606 %cmp2 = icmp slt i64 %a, 0 2607 br i1 %cmp2, label %land.rhs, label %lor.end 2608 2609land.rhs: ; preds = %lor.rhs 2610 br label %lor.end 2611 2612lor.end: ; preds = %land.rhs, %lor.rhs 2613 ret void 2614} 2615 2616; CHECK-LABEL: @idom_not_zbranch 2617define void @idom_not_zbranch(i32 %a, i32 %b) { 2618entry: 2619 %cmp = icmp sgt i32 %a, 0 2620 br i1 %cmp, label %return, label %if.end 2621 2622; CHECK-LABEL: if.end: 2623; CHECK-NOT: [[B:%.*]] = icmp slt i32 %a, 0 2624; CHECK: [[C:%.*]] = icmp eq i32 %a, %b 2625; CHECK-NOT: [[D:%.*]] = select i1 [[B]], i32 %a, i32 0 2626; CHECK-NOT: icmp ne i32 [[D]], %b 2627; CHECK-NEXT: br i1 [[C]], label %return, label %if.then3 2628if.end: ; preds = %entry 2629 %cmp1 = icmp slt i32 %a, 0 2630 %a. = select i1 %cmp1, i32 %a, i32 0 2631 %cmp2 = icmp ne i32 %a., %b 2632 br i1 %cmp2, label %if.then3, label %return 2633 2634if.then3: ; preds = %if.end 2635 br label %return 2636 2637return: ; preds = %if.end, %entry, %if.then3 2638 ret void 2639} 2640 2641; When canonicalizing to 'gt/lt', make sure the constant is correct. 2642 2643define i1 @PR27792(i128 %a) { 2644; CHECK-LABEL: @PR27792( 2645; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i128 %a, -1 2646; CHECK-NEXT: ret i1 [[CMP]] 2647; 2648 %cmp = icmp sge i128 %a, 0 2649 ret i1 %cmp 2650} 2651 2652define i1 @PR27792_2(i128 %a) { 2653; CHECK-LABEL: @PR27792_2( 2654; CHECK-NEXT: [[B:%.*]] = icmp ne i128 %a, 0 2655; CHECK-NEXT: ret i1 [[B]] 2656; 2657 %b = icmp uge i128 %a, 1 2658 ret i1 %b 2659} 2660 2661define i1 @ugtMaxSignedVal(i8 %a) { 2662; CHECK-LABEL: @ugtMaxSignedVal( 2663; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 %a, 0 2664; CHECK-NEXT: ret i1 [[CMP]] 2665; 2666 %cmp = icmp ugt i8 %a, 127 2667 ret i1 %cmp 2668} 2669 2670define <2 x i1> @ugtMaxSignedValVec(<2 x i8> %a) { 2671; CHECK-LABEL: @ugtMaxSignedValVec( 2672; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %a, zeroinitializer 2673; CHECK-NEXT: ret <2 x i1> [[CMP]] 2674; 2675 %cmp = icmp ugt <2 x i8> %a, <i8 127, i8 127> 2676 ret <2 x i1> %cmp 2677} 2678 2679define i1 @ugtKnownBits(i8 %a) { 2680; CHECK-LABEL: @ugtKnownBits( 2681; CHECK-NEXT: [[B:%.*]] = and i8 %a, 17 2682; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[B]], 17 2683; CHECK-NEXT: ret i1 [[CMP]] 2684; 2685 %b = and i8 %a, 17 2686 %cmp = icmp ugt i8 %b, 16 2687 ret i1 %cmp 2688} 2689 2690define <2 x i1> @ugtKnownBitsVec(<2 x i8> %a) { 2691; CHECK-LABEL: @ugtKnownBitsVec( 2692; CHECK-NEXT: [[B:%.*]] = and <2 x i8> %a, <i8 17, i8 17> 2693; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[B]], <i8 17, i8 17> 2694; CHECK-NEXT: ret <2 x i1> [[CMP]] 2695; 2696 %b = and <2 x i8> %a, <i8 17, i8 17> 2697 %cmp = icmp ugt <2 x i8> %b, <i8 16, i8 16> 2698 ret <2 x i1> %cmp 2699} 2700 2701define i1 @or_ptrtoint_mismatch(i8* %p, i32* %q) { 2702; CHECK-LABEL: define i1 @or_ptrtoint_mismatch(i8* %p, i32* %q) 2703; CHECK: [[pc:%.*]] = icmp eq i8* %p, null 2704; CHECK: [[qc:%.*]] = icmp eq i32* %q, null 2705; CHECK: [[b:%.*]] = and i1 [[pc]], [[qc]] 2706; CHECK: ret i1 [[b]] 2707 2708 %pp = ptrtoint i8* %p to i64 2709 %qq = ptrtoint i32* %q to i64 2710 %o = or i64 %pp, %qq 2711 %b = icmp eq i64 %o, 0 2712 ret i1 %b 2713} 2714